CN108010966B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN108010966B
CN108010966B CN201610966683.5A CN201610966683A CN108010966B CN 108010966 B CN108010966 B CN 108010966B CN 201610966683 A CN201610966683 A CN 201610966683A CN 108010966 B CN108010966 B CN 108010966B
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spacer
material layer
modified
forming
plasma
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CN108010966A (en
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张海洋
王彦
蒋鑫
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming a target material layer on the semiconductor substrate; forming a plurality of first gap walls arranged at intervals on the target material layer; carrying out first plasma treatment to modify the first gap wall to form a modified first gap wall; forming a second spacer material layer to cover the modified first spacer and a portion of the surface of the target material layer; performing a second plasma treatment to modify portions of the second spacer material layer on top of the modified first spacer and on a surface of the target material layer to form a modified second spacer material layer; and removing the modified first spacer and the modified second spacer material layer to form a plurality of second spacers arranged at intervals. The manufacturing method of the invention improves the yield and the performance of the device.

Description

Method for manufacturing semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
As the demand for high-capacity semiconductor memory devices has increased, the integration density of semiconductor memory devices has attracted attention, and in order to increase the integration density of semiconductor memory devices, many different methods have been used in the prior art, and Double-Patterning (DP) is widely accepted and applied as a solution in the fabrication of semiconductor devices.
Double-Patterning (DP) overcomes the K1 limitation by pitch fragmentation, and is widely used in the fabrication of semiconductor devices. Currently, Self-aligned Double Patterning (SADP), photo-Etch-photo-Etch (LELE), and Freeze-coat-Etch (LFL) are available in Double-Patterning (DP) technology.
Self-aligned dual patterning (SADP) is widely used in back-end-of-line (BEOL) of FinFET devices due to the limitations of photolithography, and Self-aligned four-patterning (SAQP) photolithography has been used to fabricate smaller-node devices, which has been shown to provide smaller process variations in back-end-of-line processing. The conventional four-step photolithography technique also has disadvantages, such as the complicated film layer stack must be introduced to realize the pattern transfer, which forms a spacer on the mandrel located at the upper layer, the spacer defines the contour of the mandrel located at the lower layer, and the mandrel located at the lower layer needs to be ensured to be in a square pattern (square pattern) in the process. Therefore, the traditional process has the defects of complex process, high process cost and poor surface roughness of the formed spacer, and film layers need to be deposited for multiple times. In addition, when the mandrel is removed by etching, the oxide hard mask layers on two sides of the spacer are easily over-etched, so that the oxide on two sides of each spacer is highly inconsistent, and therefore when the spacer is used as a mask to etch a semiconductor substrate to form a target pattern, the formed target pattern is distorted, the pitch is deviated, the pattern transfer quality is poor, and negative effects are caused on the robustness of a device.
Therefore, it is necessary to provide a method for manufacturing a semiconductor device to solve the above-mentioned technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, and forming a target material layer on the semiconductor substrate;
forming a plurality of first gap walls arranged at intervals on the target material layer;
carrying out first plasma treatment to modify the first gap wall to form a modified first gap wall;
forming a second spacer material layer to cover the modified first spacer and a portion of the surface of the target material layer;
performing a second plasma treatment to modify portions of the second spacer material layer on top of the modified first spacer and on a surface of the target material layer to form a modified second spacer material layer;
and removing the modified first spacer and the modified second spacer material layer to form a plurality of second spacers arranged at intervals.
Further, the step of forming the first spacer includes:
forming a plurality of mandrels which are arranged at intervals on the target material layer;
forming a first spacer material layer to cover the mandrel and the surface of the semiconductor substrate;
performing a third plasma treatment to modify a portion of the first spacer material layer on the mandrel top surface and a portion on the target material layer surface to form a modified first spacer material layer;
wet etching to remove the modified first spacer material layer to form the first spacer on the sidewall of the mandrel;
and removing the mandrel.
Further, after forming the second spacer, the method further includes the steps of:
and etching the target material layer by taking the second gap wall as a mask so as to transfer the pattern of the second gap wall to the target material layer.
Further, the method also comprises the step of carrying out ribbon plasma beam ion implantation on the first clearance wall after the first clearance wall is formed so as to improve the surface roughness of the first clearance wall, and/or the step of carrying out ribbon plasma beam ion implantation on the second clearance wall after the second clearance wall is formed so as to improve the surface roughness of the second clearance wall.
Further, the first gap wall and the second gap wall are both square in shape.
Further, the plasma used for the first plasma treatment includes H2And/or plasma of He; the plasma used for the second plasma treatment comprises H2And/or plasma of He.
Further, the modified first spacer and the modified second spacer material layer are removed by wet etching.
Further, the wet etching uses diluted hydrofluoric acid as an etchant.
Further, the material of the first spacer includes nitride, and the material of the second spacer includes nitride.
Further, the target material layer includes titanium dioxide.
In summary, according to the manufacturing method of the present invention, the process fluctuation in the implementation process of the SAQP technique can be reduced, the robustness of the SAQP technique and the integrated (AIO) etching is improved, the quality of image transfer is improved, and the yield and performance of the device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1C are schematic structural diagrams obtained in the related steps of manufacturing a device according to a conventional SADP technique;
fig. 2A to 2H are schematic structural views of a device obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Fig. 1A to 1C are schematic structural views obtained in the related steps of manufacturing a device according to a conventional SADP technique, and the related steps of the conventional SADP technique will be briefly described with reference to fig. 1A to 1C.
First, as shown in fig. 1A, a semiconductor substrate 100 on which a hard mask stack is formed is provided, and a core (core)101 is formed on the hard mask stack.
Next, as shown in fig. 1A, a spacer material layer 1021 is formed to cover the core 101 and the surface of the hard mask stack, wherein the hard mask stack is located on the top layer, which is typically an oxide hard mask.
Next, as shown in fig. 1B, the spacer material layer on the surface of the hard mask stack and on the top surface of the core is etched away to form spacers 102 on the sidewalls of the core 101.
As shown in fig. 1B, the core 101 is etched away to form a spacer 102 isolated by an opening, wherein during the process of removing the core, the hard mask layer stack outside the spacer is easily over-etched, and a step height (StepHeight) is formed in the hard mask layer stack, so that the spacer is asymmetric, and the asymmetric effect (asymmetry) of the spacer dominates the problems that the pitch of the fin structure formed by finally etching the semiconductor substrate is not uniform, and the fin structure 103 is not perpendicular to the surface of the semiconductor substrate.
Different etching amounts of oxide on two sides of the spacer form asymmetric hard mask oxide pattern profiles (due to different heights of the oxide on two sides of the spacer), which finally cause fin pitch deviation, cause great process fluctuation and affect the yield and performance of devices.
Due to the above technical problems, it is necessary to provide a new manufacturing method to improve the SAQP technology and achieve the fabrication of smaller node devices.
Example one
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, the method mainly includes the following steps:
step S301, providing a semiconductor substrate, and forming a target material layer on the semiconductor substrate;
step S302, forming a plurality of first gap walls arranged at intervals on the target material layer;
step S303, performing a first plasma treatment to modify the first spacer wall to form a modified first spacer wall;
step S304, forming a second spacer material layer to cover the modified first spacer and a part of the surface of the semiconductor substrate;
step S305, performing second plasma treatment to modify the part of the second spacer material layer on the top surface of the modified first spacer and the part of the second spacer material layer on the surface of the target material layer, thereby forming a modified second spacer material layer;
step S306, removing the modified first spacer and the modified second spacer material layer to form a plurality of second spacers arranged at intervals.
According to the manufacturing method provided by the invention, the process fluctuation in the implementation process of the SAQP technology can be smaller, the robustness of the SAQP technology and integrated (AIO) etching is improved, the quality of image transfer is improved, and the yield and the performance of the device are improved.
A method for manufacturing a semiconductor device according to the present invention is described in detail below with reference to fig. 2A to 2H, where fig. 2A to 2H are schematic structural views of a device obtained in accordance with relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
First, as shown in fig. 2A, a semiconductor substrate (not shown) on which a target material layer 201 is formed is provided.
The semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
The target material layer 201 may be an interconnect wiring layer, an interlayer dielectric layer, a gate material layer, or a hard mask layer formed on the substrate. The constituent material of the interconnect wiring layer is at least one selected from tungsten, tungsten silicide, aluminum, titanium, and titanium nitride. The constituent material of the interlayer dielectric layer may be selected from a low dielectric constant (k) material or an ultra-low k material. The gate material layer is made of one material selected from polysilicon and aluminum. The hard mask layer is made of at least one material selected from oxide, undoped silicon glass, silicon on glass, SiON, SiN, SiBN, BN and high-k material, and may be a metal hard mask layer, such as TiO2Titanium nitride, etc., in this embodiment, the target material layer 201 may be low temperature TiO2It may be used as a process for forming vias using an all-in-one (AIO) etch in the back-end-of-line (BELO) process of FinFET devices. It should be noted that the target material layer is optional, not necessary, and may be selected according to actual situations.
Next, as shown in fig. 2A, mandrels 202 are formed on the target material layer 201 in a spaced arrangement.
Illustratively, the material of the mandrel 202 may be any suitable material that facilitates forming and removal. In the present embodiment, the material of the mandrel 202 is silicon, and specifically may be amorphous silicon.
The method of forming the mandrel 202 includes: a layer of mandrel material is deposited over the layer of target material 201 and patterned to form a mandrel 202.
Next, as shown in fig. 2B, a first spacer material layer 203a is formed to cover the mandrel 202 and the surface of the target material layer 201.
The material of the first spacer material layer 203a may include nitride, oxynitride or a combination thereof, and in this embodiment, preferably, the material of the first spacer material layer 203a includes nitride, especially silicon nitride.
The first spacer material layer 203a may be formed using any suitable deposition method, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Illustratively, silicon nitride may be deposited using an atomic layer deposition method to form the first spacer material layer 203 a.
The thickness of the first spacer material layer 203a may be set reasonably according to actual process requirements, and is not limited herein.
Next, plasma treatment is performed to modify the portion of the first spacer material layer 203a on the top surface of the mandrel 202 and the portion on the surface of the target material layer 201, so as to form a modified first spacer material layer, wherein the plasma treatment is performed in a direction perpendicular to the surface of the semiconductor substrate, which modifies the portion of the first spacer material layer 203a on the top surface of the mandrel 202 and the portion on the surface of the target material layer 201, while the first spacer material layer on the sidewall of the mandrel 202 is not affected and is not modified.
Illustratively, the plasma used for the plasma treatment comprises H2And/or He, or any other plasma capable of modifying the first spacer material layer.
Further, said H2Or He plasma generation method can be selected from the methods commonly used in the art, such as H in one embodiment of the present invention2Or He gas as working gas, then plasmatizing in the plasma source, selecting H2Or He plasma treating the chamber at a pressure of 1-7torr, optionally 2-5torr, and H2Or the flow rate of He is 300-4000sccm, optionally 500-800sccm, and the bias power(Bias power) is set to 10-2000w, for example, the Bias power (Bias power) is set to 10w or more, and plasma is generated to process the first spacer material layer.
The treatment time in the step is 50-3600 s, and can be selected to be 50-1000 s, and a person skilled in the art can select the treatment time according to actual needs.
In general, the larger the power, the longer the processing time, and the larger the thickness of the modified first spacer material layer.
Next, as shown in fig. 2C, the modified first spacer material layer is removed by wet etching to form the first spacer 203 on the sidewall of the mandrel 202.
This step uses diluted hydrofluoric acid DHF (containing HF and H)2O) selectively etching to remove the modified first spacer material layer, wherein the concentration of DHF is not strictly limited, and in the present invention, HF: H2The volume ratio of O may be in the range of 1:1000 to 1: 2.
The modified first spacer material layer has a high etching selectivity ratio relative to the unmodified first spacer material layer, for example, the etching selectivity ratio may be in a range of 1:3 to 1:100, so that when the modified first spacer material layer is removed by etching, the unmodified first spacer material layer and the mandrel 202 are not over-etched.
Thereafter, as shown in fig. 2D, the mandrel 202 is removed. Illustratively, the mandrel 202 is removed by a wet etching method with a high etching selectivity of the first spacer 203 relative to the mandrel 202, and finally, a plurality of first spacers 203 are formed on the target material layer at intervals, and each first spacer 203 has a regular square profile.
Specifically, a suitable etchant is selected according to the material of the mandrel 202, for example, when the material of the mandrel 202 is silicon, an inorganic base, such as KOH, NaOH, or NH, or an organic base solution is used as the etchant4OH, etc., the organic base may be tetramethylammonium hydroxide (TMAH) solution orEDP (including ethylenediamine, hydroquinone, and water), etc., in this embodiment, it is preferable to remove the mandrel 202 using a tetramethylammonium hydroxide (TMAH) solution.
In one example, the first spacer 203 may also be selectively ion implanted to improve the surface roughness of the first spacer 203. Illustratively, the ion implantation is performed by using a plasma ribbon beam (plasma ribbon beam), the implanted ions are neutral atoms or radicals, such as phosphorus, argon, arsenic, etc., and the implantation dose is 1E 14-2E 16atoms/cm2The implantation energy is schematically 40 to 80 keV.
Next, as shown in fig. 2E, a plasma treatment is performed to modify the first spacer to form a modified first spacer 2031, and the plasma treatment process converts all of the first spacers into the modified first spacer 2031.
Illustratively, in this step, the plasma used for the plasma treatment includes H2And/or He, or any other plasma capable of modifying the first spacer.
Further, said H2Or He plasma generation method can be selected from the methods commonly used in the art, such as H in one embodiment of the present invention2Or He gas as working gas, then plasmatizing in the plasma source, selecting H2Or He plasma treating the chamber at a pressure of 1-7torr, optionally 2-5torr, and H2Or He flow rate of 300-.
The treatment time in the step is 50-3600 s, and can be selected to be 50-1000 s, and a person skilled in the art can select the treatment time according to actual needs.
In general, the larger the power, the longer the processing time, and the larger the thickness of the modified first spacer.
Next, as shown in fig. 2F, a second spacer material layer 204 is formed to cover the modified first spacer 2031 and a portion of the surface of the target material layer 201.
Illustratively, the second spacer material layer 204 and the first spacer 203 are made of the same material, for example, the material of the second spacer material layer may include nitride, oxynitride or a combination thereof, and in this embodiment, preferably, the material of the second spacer material layer 204 includes nitride, especially silicon nitride.
The second spacer material layer 204 may be formed using any suitable deposition method, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Illustratively, an atomic layer deposition process may be used to deposit and form silicon nitride as the second spacer material layer 204.
The thickness of the second spacer material layer 204 can be set reasonably according to actual process requirements, and is not limited herein.
Next, as shown in fig. 2G, plasma treatment is performed to modify the portion of the second spacer material layer on the top surface of the modified first spacer and the portion on the surface of the target material layer, thereby forming a modified second spacer material layer 2041.
Illustratively, in this step, the plasma used for the plasma treatment includes H2And/or He, or any other plasma capable of modifying the second spacer material layer.
Further, said H2Or He plasma generation method can be selected from the methods commonly used in the art, such as H in one embodiment of the present invention2Or He gas as working gas, then plasmatizing in the plasma source, selecting H2Or He plasma treating the chamber at a pressure of 1-7torr, optionally 2-5torr, and H2Or the flow rate of He is 300-4000sccm, optionally 500-800sccm, and the bias voltage is setThe power (Bias power) is 10-2000w, for example, the Bias power (Bias power) is set to 10w or more, and plasma is generated to process the second spacer material layer.
The treatment time in the step is 50-3600 s, and can be selected to be 50-1000 s, and a person skilled in the art can select the treatment time according to actual needs.
In general, the larger the power, the longer the processing time, and the larger the thickness of the modified second spacer material layer.
Here, since the second spacer material layer and the first spacer are made of the same material, the modified second spacer material layer 2041 and the modified first spacer 2031 formed by the same plasma treatment method have the same material.
The plasma treatment partially modifies the second spacer material layer in a direction perpendicular to the surface of the semiconductor substrate, wherein a portion of the second spacer material layer on the sidewalls of the modified first spacers 2031 remains unmodified.
Next, as shown in fig. 2H, the modified first spacer and the modified second spacer material layer are removed to form a plurality of second spacers 2042 arranged at intervals.
This step uses diluted hydrofluoric acid DHF (containing HF and H)2O) selectively etching to remove the modified first spacer and the modified second spacer material layer, wherein the concentration of DHF is not strictly limited, and in the present invention, HF: H2The volume ratio of O may be in the range of 1:1000 to 1: 2.
The modified first gap wall and the modified second gap wall material layer are removed with a high etching selection ratio relative to the unmodified second gap wall material layer, for example, the etching selection ratio can be in a range of 1:3 to 1:100, so that when the modified first gap wall and the modified second gap wall material layer are removed by etching, the unmodified second gap wall material layer is not over-etchedWithout over-etching the target material layer 201, for example, the target material layer 201 is low temperature TiO2Therefore, the second spacer 2042 is finally formed, the second spacer 2042 has a regular square profile and is perpendicular to the surface of the semiconductor substrate, and the target material layers on both sides of the second spacer 2042 do not have a height difference, so that the pattern of the second spacer 2042 can be well transferred to the target material layer 201, the precision of pattern transfer is ensured, the fluctuation of the process is reduced, and the fabrication of smaller node devices can be realized.
In one example, the second spacer 2042 may also be selectively ion implanted to improve the surface roughness of the second spacer 2042. Illustratively, the ion implantation is performed by using a plasma ribbon beam (plasma ribbon beam), the implanted ions are neutral atoms or radicals, such as phosphorus, argon, arsenic, etc., and the implantation dose is 1E 14-2E 16atoms/cm2The implantation energy is schematically 40 to 80 keV.
It should be noted that the steps of depositing the spacer material layer, partially modifying the spacer material layer by plasma treatment, and removing the modified spacer material layer by wet etching may be performed several times to fabricate a mask pattern with a smaller pitch.
Finally, the method also comprises the step of etching the target material layer by taking the second gap wall as a mask so as to transfer the pattern of the second gap wall to the target material layer.
Thus, the introduction of the manufacturing method of the semiconductor device of the present invention is completed, and other process steps are required for the complete device fabrication, which is not described herein again.
In summary, in the manufacturing method of the present invention, by performing the plasma processing step for multiple times, a part of the spacer material layer is modified to further realize the etching rate difference, so as to remove the spacer material layer to be removed, and finally form the second spacer, where the second spacer has a regular square profile and is perpendicular to the surface of the semiconductor substrate, and there is no height difference between the target material layers on both sides of the second spacer, the pattern of the second spacer can be well transferred to the target material layer, and the precision of pattern transfer is ensured, so that the process fluctuation in the implementation process of the SAQP technique is smaller, the robustness of the SAQP technique and integrated (AIO) etching is improved, the quality of image transfer is improved, the fabrication of smaller node devices (for example, 5nm node devices) is realized, and the yield and performance of the devices are finally improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a target material layer on the semiconductor substrate;
forming a plurality of first gap walls arranged at intervals on the target material layer;
performing a first plasma treatment to modify all of the first spacers to form modified first spacers;
forming a second spacer material layer to cover the modified first spacer and a portion of the surface of the target material layer;
performing a second plasma treatment to modify portions of the second spacer material layer on top of the modified first spacer and on a surface of the target material layer to form a modified second spacer material layer, the modified first spacer and the modified second spacer material layer having a high etch selectivity relative to the unmodified second spacer material layer;
and removing the modified first spacer and the modified second spacer material layer to form a plurality of second spacers arranged at intervals.
2. The method of manufacturing of claim 1, wherein the step of forming the first spacer comprises:
forming a plurality of mandrels which are arranged at intervals on the target material layer;
forming a first spacer material layer to cover the mandrel and the surface of the semiconductor substrate;
performing a third plasma treatment to modify a portion of the first spacer material layer on the mandrel top surface and a portion on the target material layer surface to form a modified first spacer material layer having a high etch selectivity ratio relative to the unmodified first spacer material layer;
wet etching to remove the modified first spacer material layer to form the first spacer on the sidewall of the mandrel;
and removing the mandrel.
3. The method of manufacturing according to claim 1, further comprising, after forming the second spacer, the steps of:
and etching the target material layer by taking the second gap wall as a mask so as to transfer the pattern of the second gap wall to the target material layer.
4. The method according to claim 1, further comprising a step of performing a ribbon plasma ion implantation on the first spacer after the forming of the first spacer to improve a surface roughness of the first spacer, and/or a step of performing a ribbon plasma ion implantation on the second spacer after the forming of the second spacer to improve a surface roughness of the second spacer.
5. The method of manufacturing according to claim 1, wherein the first spacer and the second spacer are each square in shape.
6. The method of claim 1, wherein the plasma used for the first plasma treatment comprises H2And/or plasma of He; the plasma used for the second plasma treatment comprises H2And/or plasma of He.
7. The method of manufacturing of claim 1, wherein the modified first spacer and the modified second spacer material layer are removed using a wet etch process.
8. The manufacturing method according to claim 7, wherein the wet etching uses diluted hydrofluoric acid as an etchant.
9. The method of manufacturing according to claim 1, wherein a material of the first spacer comprises a nitride, and a material of the second spacer comprises a nitride.
10. The manufacturing method according to claim 1, wherein the target material layer includes titanium dioxide.
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