CN105826197A - Semiconductor device and manufacturing method thereof, and electronic device - Google Patents
Semiconductor device and manufacturing method thereof, and electronic device Download PDFInfo
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- CN105826197A CN105826197A CN201510008991.2A CN201510008991A CN105826197A CN 105826197 A CN105826197 A CN 105826197A CN 201510008991 A CN201510008991 A CN 201510008991A CN 105826197 A CN105826197 A CN 105826197A
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Abstract
The invention relates to a semiconductor device and a manufacturing method thereof, and an electronic device. The method comprises steps: S1, a semiconductor substrate is provided, and a plurality of oxide virtual cores arranged at intervals are formed on the semiconductor substrate; S2, a gap wall material layer is deposited to cover the oxide virtual cores and the semiconductor substrate; S3, plasma processing is carried out on the gap wall material layer in a horizontal direction, and a modification layer is thus formed above the semiconductor substrate and the top of the oxide virtual core; S4, the modification layer is removed to enable a gap wall to be formed on the side wall of the oxide virtual core; and S5, the oxide virtual core is removed to obtain a fin pattern. The method of the invention has the advantages that the dual-pattern manufacturing method is more robust, and a manufactured FinFET has better performance and yield.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular it relates to a kind of semiconductor device and manufacture method, electronic installation.
Background technology
The raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing IC-components.At present, have evolved to smaller technical matters node owing to pursuing the semi-conductor industry of high device density, high-performance and low cost, promote the development of three dimensional design such as FinFET (FinFET) from the challenge manufactured with design aspect.
Relative to existing planar transistor, FinFET has more superior performance at aspects such as raceway groove control and reduction shallow channel effects；Wherein, planar gate is arranged at above described raceway groove, and arranges around described fin at grid described in FinFET, can control electrostatic from three faces, and therefore the performance in terms of Electrostatic Control is the most prominent.
Along with constantly reducing of dimensions of semiconductor devices, double patterning technology (Double-Patterning, DP) is just being accepted widely in the preparation process of FinFET as a kind of solution route and is being applied.
At present at double patterning technology (Double-Patterning, DP) technology has self-aligned double patterning case (Self-aligneddoublepatterning, SADP), photoetching-etching-photoetching-etching (Litho-Etch-Litho-Etch, LELE) and freeze coating etching (Litho-Freeze-Litho, LFL).
In device fabrication process, select which kind of technology, need the height considering the motility of every kind of technology, the suitability and cost to select.Wherein self-aligned double patterning case technology (Self-aligneddoublepatterning, SADP) is realizing the etch capabilities of minimum spacing beyond the expectation to the method.
nullWherein，Clearance wall is widely used in self-aligned double patterning case technology (Self-aligneddoublepatterning，SADP) in，Generally select the method for photoetching-etching-thin film deposition-etching-removal core-etching (Litho Etch filmdeposition-Etch Strip Etch.) to prepare semiconductor device，Such as select amorphous carbon A-C and pattern as the core (core) in double patterning，Then low temperature deposition method is selected to form gap wall layer on described A-C，Finally remove described A-C core，Described method would generally form taper core the most also can cause dielectric anti reflective layer (dielectricAnti-reflectivecoating，Burden is produced when DRAC) covering，In addition，Odd-even (Even-odd) problem occurs，Such as odd-even critical size the most homogeneous (Even-oddCDloading)，Prior art is generally selected polysilicon replace described A-C to prepare polysilicon core，But polysilicon is easily oxidized in preparation process，Odd-even (Even-odd) problem can be caused equally，Make the fin critical size finally prepared the most homogeneous.
It is thus desirable to current described preparation method is improved further, in order to eliminate various problems present in prior art.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will further describe in detailed description of the invention part.The Summary of the present invention is not meant to key feature and the essential features attempting to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
The present invention is in order to overcome the problem of presently, there are, it is provided that the manufacture method of a kind of semiconductor device, including:
Step S1: Semiconductor substrate is provided, is formed with some spaced oxide virtual core on the semiconductor substrate；
Step S2: deposition spacer material layer, to cover described oxide virtual core and described Semiconductor substrate；
Step S3: the described spacer material layer in horizontal direction is carried out Cement Composite Treated by Plasma, forms modified layer with side on the semiconductor substrate and described oxide virtual core over top；
Step S4: remove described modified layer, to form clearance wall on the sidewall of described oxide virtual core；
Step S5: remove described oxide virtual core, to obtain fin pattern.
Alternatively, in described step S1, between described Semiconductor substrate and oxide virtual core, it is also formed with covering the SiGe layer of described Semiconductor substrate.
Alternatively, in described step S3, the spacer material layer that described spacer material layer is non-modified being positioned on described oxide virtual core sidewall.
Alternatively, in described step S2, described spacer material layer selects nitride.
Alternatively, in described step S3, select H2Or described spacer material layer is processed by He plasma.
Alternatively, in described step S4, wet etching is selected to remove described modified layer, to form described clearance wall.
Alternatively, in described step S4, DHF is selected to remove described modified layer, to form described clearance wall.
Alternatively, in described step S5, DHF is selected to remove described oxide virtual core.
Alternatively, described step S1 includes:
Step S11: sequentially form SiGe layer, oxide skin(coating) and mask stack on the semiconductor substrate；
Step S12: pattern described mask stack, to obtain virtual core pattern；
Step S13: oxide skin(coating) described in described mask stack as mask etch, to obtain described oxide virtual core.
Present invention also offers a kind of semiconductor device prepared based on above-mentioned method.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor device.
The present invention is in order to change various problems present in prior art, provide the preparation method of a kind of semiconductor device, first described method is formed in described oxide virtual core spacer material layer, then described spacer material layer is carried out Cement Composite Treated by Plasma, so that the spacer material layer in horizontal direction is become modified layer, then the described modified layer of selective removal is to form clearance wall on the sidewall of described oxide virtual core, finally remove described oxide virtual core, obtain fin pattern, can avoid during double patterning, cause the substantial amounts of loss of oxide by described method, the inhomogenous problem of odd-even size selecting silicon virtual core or A-C virtual core to bring can also be avoided simultaneously, improve performance and the yield of semiconductor device.
It is an advantage of the current invention that to make described double patterning preparation method more sane, the FinFET prepared has better performance and yield.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 a-1e is the process schematic manufacturing semiconductor device in prior art；
Fig. 2 a-2f is the process schematic manufacturing semiconductor device in an embodiment of the present invention；
Fig. 3 present invention manufactures the process chart of semiconductor device.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It is understood that, when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or during layer, its can directly on other element or layer, adjacent thereto, be connected or coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can being used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not be limited by these terms.These terms are used merely to distinguish an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, under without departing from present invention teach that, the first element discussed below, parts, district, floor or part are represented by the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ", " ... on ", " above " etc., here can describe for convenience and be used thus shown in description figure a element or feature and other element or the relation of feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other orientation) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and the restriction not as the present invention.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but be not excluded for one or more other the existence of feature, integer, step, operation, element, parts and/or group or interpolation.When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have other embodiments.
It is photoetching-etching-thin film deposition-etching-removal core-etching (Litho Etch filmdeposition-Etch Strip Etch.) that SADP described in prior art prepares the method for semiconductor device, as shown in Fig. 1 a-1e, wherein, first Semiconductor substrate 101 is provided, described Semiconductor substrate 101 is formed unformed silicon 102, the material layers such as nitride oxide can also be formed between described Semiconductor substrate 101 and described unformed silicon, then on described hard mask layer, form organic layer and the photoresist core 103 of anti-reflecting layer and patterning, as shown in Figure 1a.
Then with described photoresist and as mask etch described in unformed silicon 102, to form unformed silicon core 1021, as shown in Figure 1 b, then remove described photoresist core 103.
Then on described unformed silicon core 1021, deposit spacer material layer 104, to cover described unformed silicon core 1021, pattern described spacer material layer 104, to form clearance wall 1041 on described unformed silicon core 1021, as illustrated in figure 1 c.
Then described unformed silicon core 1021 is removed, Semiconductor substrate 101 described in finally with described clearance wall 1041 as mask etch, to transfer a pattern in described Semiconductor substrate 101, obtain the device architecture as described in Fig. 1 d.
The deposition of clearance wall described in described method and etching process make line width roughness (linewidthroughness, LWR) performance reduce, thus affect the performance of semiconductor device.Simultaneously because described unformed silicon can be oxidized, odd-even critical size the most homogeneous (Even-oddCDloading) occurs, as shown in right figure in Fig. 1 e, spacing, insufficient height between fin are homogeneous, thus cause the problems such as thin film deposition in subsequent step, Lithography Etching and process window skew.
It is thus desirable to the preparation method of current described semiconductor device is improved further, in order to eliminate the problems referred to above.
Embodiment 1
The method of the invention is further described by 2a-2f below in conjunction with the accompanying drawings, prepares the process schematic of semiconductor device during wherein Fig. 2 a-2f is an embodiment of the present invention based on double patterning method.
Step 201 is first carried out, it is provided that Semiconductor substrate 201, described Semiconductor substrate 201 is formed SiGe layer, oxide skin(coating) 202 and the mask layer 203 of patterning.
Specifically, as shown in Figure 2 a, at least one during described Semiconductor substrate 201 can be the following material being previously mentioned: stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacking silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Alternatively, it is also possible in described Semiconductor substrate, form isolation structure, described isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Form shallow trench isolation in the present invention, described Semiconductor substrate is also formed with various trap (well) structure and the channel layer of substrate surface.
Additionally, active area can be defined in Semiconductor substrate.Other active device can also be included on the active region, for convenience, do not indicate in shown figure.
Then, forming boundary layer on the semiconductor substrate, wherein said boundary layer can be selected boundary material commonly used in the art, such as oxide skin(coating), nitride etc., but be not limited to a certain kind, not repeat them here.
Forming SiGe layer and layer of oxide material 202 on described boundary layer, wherein said layer of oxide material 202 can select SiO2, but it being not limited to this material, wherein said SiGe layer is as the stop-layer of modified layer described in selective removal in subsequent step.
Finally in described layer of oxide material 202, form organic distribution layer (Organicdistributionlayer, ODL), siliceous bottom antireflective coating (Si-BARC), goes up the photoresist layer of deposit patterned at described siliceous bottom antireflective coating (Si-BARC).
Wherein, described photoresist layer forms multiple spaced virtual core pattern as shown in Figure 2 a.
Performing step 202, layer of oxide material 202 described in the mask layer 203 of described patterning as mask etch, to form described oxide virtual core 2021 in described layer of oxide material 202.
As shown in Figure 2 b, selecting layer of oxide material 202 described in dry etching in this step, described etching atmosphere can select, so that described layer of oxide material 202 and described SiGe layer have bigger etching selectivity according to the material selected.
Specifically, with described photoresist layer as mask layer, etch described organic distribution layer, bottom antireflective coating, to transfer a pattern in described organic distribution layer, bottom antireflective coating, then layer of oxide material 202 described in the described organic distribution layer of described etching, bottom antireflective coating as mask etch, to form described oxide virtual core 2021 in described layer of oxide material 202.
Select layer of oxide material 202 described in dry etching in this step, the most described dry etching can be selected CF4、CHF3Additionally plus N2、CO2、O2In one as etching atmosphere, wherein gas flow is CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s.
Perform step 203, deposit spacer material layer 204, to cover described oxide virtual core 2021 and described Semiconductor substrate 201.
Specifically, as shown in Figure 2 c, the most described spacer material layer 204 selects nitride, such as, select SiN, but be not limited to this material.
Wherein, described spacer material layer 204 selects ald (ALD) to be formed.
Alternatively, the thickness of described spacer material layer 204 is not limited to a certain numerical range.
Perform step 204, the described spacer material layer 204 in horizontal direction is carried out Cement Composite Treated by Plasma, form modified layer 205 with the over top of side and described oxide virtual core 2021 on the semiconductor substrate.
Specifically, as shown in Figure 2 d, in this step, described spacer material layer 204 is carried out Cement Composite Treated by Plasma, so that the described spacer material layer 204 in horizontal direction is modified, form modified layer 205, and in the vertical direction, described spacer material layer 204 not modification on described oxide virtual core sidewall, both have bigger etching selectivity, therefore the most selective can remove described modified layer, the sidewall of described oxide virtual core is formed clearance wall.
Alternatively, H is selected2Or described spacer material layer 204 is processed by He plasma.
Further, described H2Or the production method of He plasma can select method commonly used in the art, select H the most in one embodiment of this invention2Or He gas is as working gas, in described plasma source, then carry out plasma, select H2Or the pressure that described in He Cement Composite Treated by Plasma, during chamber, described gas ions processes is 1-7torr, it is chosen as 2-5torr, described H2Or the flow velocity of He is 300-4000sccm, being chosen as 500-800sccm, described power is 100-2000w, such as, described HFRF power is set to more than 100w, produces plasma to process described chamber.
The time that processes in this step is 0.5-5 hour, is chosen as 0.5-1 hour, and those skilled in the art can select according to actual needs.
Perform step 205, remove described modified layer, to form clearance wall 2041 on the sidewall of described oxide virtual core 2021.
Specifically, as shown in Figure 2 e, wet etching is selected optionally to remove described modified layer, to form described clearance wall 2041 in this step.
Alternatively, DHF is selected to remove described modified layer, to form described clearance wall 2041.
Wherein, specifically, (HF, H are wherein comprised with the Fluohydric acid. DHF of dilution in this step2O2And H2O) selective etch removes described modified layer.
Wherein, the concentration of described DHF the most strictly limits, in the present invention preferably HF:H2O2:H2O=0.1-1.5:1:5.
Perform step 206, remove described oxide virtual core 2021, to obtain fin pattern.
Specifically, as shown in figure 2f, DHF is selected to remove described oxide virtual core 2021, to obtain the fin pattern that clearance wall is formed.
Further, (HF, H are wherein comprised with the Fluohydric acid. DHF of dilution in this step2O2And H2O) wet method peels off described clearance wall.Wherein, the concentration of described DHF the most strictly limits, in the present invention preferably HF:H2O2:H2O=0.1-1.5:1:5.
So far, the introduction of the correlation step of the manufacture method of the semiconductor device of the embodiment of the present invention is completed.After step 206, it is also possible to including other correlation step, here is omitted.Further, in addition to the foregoing steps, the manufacture method of the present embodiment can also include other steps among each step above-mentioned or between different step, and these steps all can be realized by various techniques of the prior art, and here is omitted.
The present invention is in order to change various problems present in prior art, provide the preparation method of a kind of semiconductor device, first described method is formed in described oxide virtual core spacer material layer, then described spacer material layer is carried out Cement Composite Treated by Plasma, so that the spacer material layer in horizontal direction is become modified layer, then the described modified layer of selective removal is to form clearance wall on the sidewall of described oxide virtual core, finally remove described oxide virtual core, obtain fin pattern, can avoid during double patterning, cause the substantial amounts of loss of oxide by described method, the inhomogenous problem of odd-even size selecting silicon virtual core or A-C virtual core to bring can also be avoided simultaneously, improve performance and the yield of semiconductor device.
It is an advantage of the current invention that to make described double patterning preparation method more sane, the FinFET prepared has better performance and yield.
Fig. 3 is the preparation technology flow chart of semiconductor device described in the embodiment of the invention, specifically includes following steps:
Step S1: Semiconductor substrate is provided, is formed with some spaced oxide virtual core on the semiconductor substrate；
Step S2: deposition spacer material layer, to cover described oxide virtual core and described Semiconductor substrate；
Step S3: the described spacer material layer in horizontal direction is carried out Cement Composite Treated by Plasma, forms modified layer with side on the semiconductor substrate and described oxide virtual core over top；
Step S4: remove described modified layer, to form clearance wall on the sidewall of described oxide virtual core；
Step S5: remove described oxide virtual core, to obtain fin pattern.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device selects the method described in embodiment 1 to prepare.The pattern being prepared by the method for the present invention the semiconductor device obtained has good homogeneity and concordance, to improve performance and the yield of semiconductor device further.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment 2.Wherein, semiconductor device is the semiconductor device described in embodiment 2, or the semiconductor device obtained according to the preparation method described in embodiment 1.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, it is possible to for any intermediate products including described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a manufacture method for semiconductor device, including:
Step S1: Semiconductor substrate is provided, is formed with some spaced oxide virtual core on the semiconductor substrate；
Step S2: deposition spacer material layer, to cover described oxide virtual core and described Semiconductor substrate；
Step S3: the described spacer material layer in horizontal direction is carried out Cement Composite Treated by Plasma, forms modified layer with side on the semiconductor substrate and described oxide virtual core over top；
Step S4: remove described modified layer, to form clearance wall on the sidewall of described oxide virtual core；
Step S5: remove described oxide virtual core, to obtain fin pattern.
Method the most according to claim 1, it is characterised in that in described step S1, is also formed with covering the SiGe layer of described Semiconductor substrate between described Semiconductor substrate and oxide virtual core.
Method the most according to claim 1, it is characterised in that in described step S3, the spacer material layer that described spacer material layer is non-modified being positioned on described oxide virtual core sidewall.
Method the most according to claim 1, it is characterised in that in described step S2, described spacer material layer selects nitride.
5., according to the method described in claim 1 or 4, it is characterised in that in described step S3, select H2Or described spacer material layer is processed by He plasma.
Method the most according to claim 1, it is characterised in that in described step S4, selects wet etching to remove described modified layer, to form described clearance wall.
7., according to the method described in claim 1 or 6, it is characterised in that in described step S4, select DHF to remove described modified layer, to form described clearance wall.
Method the most according to claim 1, it is characterised in that in described step S5, selects DHF to remove described oxide virtual core.
Method the most according to claim 1, it is characterised in that described step S1 includes:
Step S11: sequentially form SiGe layer, oxide skin(coating) and mask stack on the semiconductor substrate；
Step S12: pattern described mask stack, to obtain virtual core pattern；
Step S13: oxide skin(coating) described in described mask stack as mask etch, to obtain described oxide virtual core.
10. the semiconductor device prepared based on the method one of claim 1 to 9 Suo Shu.
11. 1 kinds of electronic installations, including the semiconductor device described in claim 10.
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| US11217477B2 (en) | 2017-06-30 | 2022-01-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a liner layer with a configured profile |
| US11545390B2 (en) | 2017-06-30 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating a semiconductor device having a liner layer with a configured profile |
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Application publication date: 20160803 |