CN110544688A - Active array, method for manufacturing active array, and random access memory - Google Patents
Active array, method for manufacturing active array, and random access memory Download PDFInfo
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- CN110544688A CN110544688A CN201810529033.3A CN201810529033A CN110544688A CN 110544688 A CN110544688 A CN 110544688A CN 201810529033 A CN201810529033 A CN 201810529033A CN 110544688 A CN110544688 A CN 110544688A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 10
- 230000000903 blocking effect Effects 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 2
- 239000011295 pitch Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 9
- 239000011159 matrix material Substances 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
The invention provides an active array, a manufacturing method of the active array and a random access memory, wherein the manufacturing method of the active array comprises the steps of providing a semiconductor substrate, forming photoresist arranged at intervals on the semiconductor substrate, depositing a first barrier layer, a sacrificial layer and a second barrier layer, and forming a spacing unit consisting of an active area unit and an isolation gap through etching to construct the active array; the active array comprises a semiconductor substrate, a spacing unit formed by an active area unit and an isolation gap, wherein the minimum size of photoresist exposure and development is odd times of the spacing unit; the random access memory comprises an active array, a device unit and a shallow trench isolation structure, wherein the device unit is formed on an active area unit, and an isolation gap is filled to form the shallow trench isolation structure. The invention improves the photoetching limit precision by changing the deposition mode and the etching mode of materials in the manufacturing of the active array so as to obtain the spacing units with smaller sizes, thereby meeting the requirement of the specific small-spacing units in the random access memory.
Description
Technical Field
the present invention relates to the field of semiconductor integrated circuits, and more particularly, to an active array, a method for manufacturing the active array, and a random access memory.
background
In random access memory, an Active array (Active array) currently popular is shown in fig. 1, and the spacing between a single device Cell 1(Cell, formed by an Active area Cell line in the Active array) and its adjacent shallow trench isolation structure 2(STI, formed by an isolation gap space in the Active array) is called a Pitch Cell 3 (Pitch).
In the prior art, a Pitch doubling process is adopted, and an original Pitch is divided into two pitches, so that the size of the Pitch is reduced, but due to the limitation of the exposure active area unit width, the size of a Pitch unit and the active area unit width obtained by photoetching in the prior art cannot meet the size requirements of certain smaller Pitch units.
disclosure of Invention
the present invention provides an active array, a method of manufacturing the active array, and a random access memory, to solve at least one technical problem in the above prior art.
to achieve the above object, the present invention provides a method for manufacturing an active array, comprising:
Providing a semiconductor substrate, wherein photoresist is arranged on the semiconductor substrate at intervals;
forming a first barrier layer on the semiconductor substrate and the photoresist;
Forming a sacrificial layer on the first barrier layer, wherein the sacrificial layer between two adjacent photoresists forms a groove;
Forming a second barrier layer on the sacrificial layer to fill the groove;
Removing the second barrier layer downwards along the upper surface of the second barrier layer to expose the upper surface of the sacrificial layer, wherein the second barrier layer in the groove forms a shielding part;
etching the sacrificial layer and the first barrier layer downwards from the upper surface of the sacrificial layer by taking the shielding part as a mask until the upper surface of the photoresist is exposed, wherein the first barrier layer is provided with a mask part attached to the side surface of the photoresist and a protection part positioned between the sacrificial layer and the semiconductor substrate, and the longitudinal thickness of the mask part is greater than that of the protection part;
removing the photoresist, and etching the sacrificial layer downwards along the exposed part of the sacrificial layer until the protection part of the first barrier layer is exposed, and continuing to etch the exposed protection part of the first barrier layer until the semiconductor substrate is exposed, so as to form a plurality of barrier structures consisting of the mask part of the first barrier layer and the shielding part comprising the second barrier layer on the semiconductor substrate; and
Forming a spacing unit for constructing the active array, wherein the step of etching the semiconductor substrate by taking the blocking structure as a mask so as to form an isolation gap; removing the barrier structure to form an active area unit; wherein one of the active area cells and its adjacent one of the isolation gaps constitute a pitch cell.
in one embodiment, the minimum dimension of the exposure development between adjacent photoresists is an odd multiple of the pitch cell dimension.
in one embodiment, the photoresist comprises a first side and a second side opposite to the first side, and the distance between the first sides of two adjacent photoresists is the minimum dimension of exposure development, wherein the semiconductor substrate comprises three pitch units at the position corresponding to the minimum dimension of exposure development.
In one embodiment, the pitch cell size comprises 30 nm.
In one embodiment, 1/2 of the thickness of the sacrificial layer is equal to or greater than the thickness of the first barrier layer, and the sum of the lateral thickness of the sacrificial layer at the first side and the lateral thickness of the first barrier layer at the first side is less than 1/2 of the spacing between adjacent photoresists.
in one embodiment, the size of the photoresist, and the thicknesses of the first barrier layer and the sacrificial layer at the first side and the second side of the photoresist are adjusted to adjust the width of the active area cells and the size of the isolation gap.
In one embodiment, the first barrier layer and the second barrier layer each comprise silicon nitride, and the sacrificial layer comprises silicon oxide.
In one embodiment, the plurality of blocking structures including the blocked portion of the second blocking layer further includes the sacrificial layer and the first blocking layer under the blocked portion to constitute a mask stack layer.
to achieve the above object, the present invention provides an active array, comprising:
a semiconductor substrate; and
a plurality of active region units formed on the semiconductor substrate according to the manufacturing method described in the above embodiment and an isolation gap between the adjacent active region units;
wherein the minimum feature size of the exposure development size of the photoresist is an odd multiple of the feature size of the pitch unit.
In one embodiment, the feature size of the pitch unit comprises 30nm
To achieve the above object, the present invention provides a random access memory, comprising
An active array as described in the previous embodiments;
a plurality of device cells formed on the active region cells; and
And the shallow trench isolation structure is formed in the semiconductor substrate by filling an isolation material in the isolation gap.
the invention improves the photoetching limit precision by changing the deposition mode and the etching mode of materials in the manufacturing of the active array so as to obtain the spacing units with smaller sizes, so that the active array and the random access memory obtain the spacing units with smaller sizes, thereby meeting the requirement of the specific small-spacing units.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a block diagram of an active array in the prior art.
FIG. 2 is a flow chart of active array fabrication in an embodiment of the present invention.
Fig. 3 is a structural diagram of the step S10 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 4 is a structural diagram of the step S20 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 5 is a structural diagram of the step S30 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 6 is a structural diagram of the step S40 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 7 is a structural diagram of the step S50 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 8 is a structural diagram of the step S60 of manufacturing an active matrix in an embodiment of the present invention.
Fig. 9 is a structural diagram of the step S70 of manufacturing an active matrix in an embodiment of the present invention.
fig. 10 is a structural diagram of an active array in a semiconductor device in an embodiment of the present invention.
reference numbers in fig. 1:
1: device unit, 2: shallow trench isolation structure, 3: and (5) a distance unit.
reference numerals in fig. 3 to 10:
A semiconductor substrate of a semiconductor substrate 110,
120 of a photoresist layer is formed on the surface of the substrate,
121 on a first side thereof,
122 on the second side of the first side,
130 of the first barrier layer 130, and,
131 a mask portion for masking the surface of the wafer,
132 a protective part for protecting the optical fiber cable,
140 a sacrificial layer of a dielectric material, and,
141 of a plurality of grooves, and a plurality of grooves,
150 of the second barrier layer, and a second barrier layer,
151 of the light-shielding part,
The unit of 160 pitches is used to make the back plate,
the gap is separated by a distance of 160A,
160B active area cells.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Example one
a method for manufacturing an active array in this embodiment, as shown in fig. 2, includes:
Step S10: referring to fig. 3, a semiconductor substrate 110 is provided, and photoresists 120 are formed on the semiconductor substrate 110 at intervals.
Step S20: referring to fig. 4, a first barrier layer 130 is formed on the semiconductor substrate 110 and the photoresist 120.
Step S30: referring to fig. 5, a sacrificial layer 140 is formed on the first barrier layer 130, wherein the sacrificial layer 140 between two adjacent photoresists 120 forms a groove 141. The materials of the first barrier layer 130 and the sacrificial layer 140 are different so as not to affect each other when separately etched.
step S40: referring to fig. 6, a second barrier layer 150 is formed on the sacrificial layer 140 to fill the groove 141. The materials of the second barrier layer 150 and the sacrificial layer 140 are different so as not to affect each other when separately etched.
Step S50: referring to fig. 7, the second barrier layer 150 is removed downward along the upper surface of the second barrier layer 150 to expose the upper surface of the sacrificial layer 140, wherein the second barrier layer 150 in the groove 141 forms a blocking portion 151.
Step S60: referring to fig. 8, the sacrificial layer 140 and the first barrier layer 130 are etched downward from the upper surface of the sacrificial layer 140 using the shielding portion 151 as a mask until the upper surface of the photoresist 120 is exposed. The first barrier layer 130 has a mask portion 131 attached to a side surface of the photoresist 120 and a protection portion 132 between the sacrificial layer 140 and the semiconductor substrate 110, and a longitudinal thickness of the mask portion 131 is greater than a longitudinal thickness of the protection portion 132. The etching exposes all the upper surfaces of the photoresists 120 and stops etching, so that all the photoresists 120 on the semiconductor substrate 110 can be conveniently removed.
Step S70: referring to fig. 9, the photoresist 120 is removed, and the sacrificial layer is etched down along the exposed portion of the sacrificial layer 140 until the protection portion 132 of the first barrier layer 130 is exposed, and the exposed protection portion 132 of the first barrier layer 130 is continuously etched until the semiconductor substrate 110 is exposed, so as to form a plurality of barrier structures on the semiconductor substrate 110, wherein the barrier structures are formed by the mask portion 131 of the first barrier layer 130 and the shielding portion 151 including the second barrier layer 150. The barrier structure further includes the sacrificial layer 140 and the first barrier layer 130 under the blocking portion 151 to constitute a mask stack layer. In the etching process of the sacrificial layer 140, the sacrificial layer is recessed towards both sides due to the large thickness, and the recessed portion does not affect the etching portion of the first barrier layer 130.
step S80: referring to fig. 10, forming the pitch unit 160 for constructing an active array includes etching the semiconductor substrate 110 with the barrier structure as a mask to form an isolation gap 160A; removing the barrier structure to form an active area unit 160B; and one of the active region cells 160B and its adjacent one of the isolation gaps 160A constitute one pitch cell 160. The pitch of one active region cell 160B and its adjacent one isolation gap 160A is one cell pitch.
In the present embodiment, under the condition that the size of the photoresist 120 cannot be reduced, the deposition manner and the etching manner of the material on the semiconductor substrate 110 are changed to form a plurality of active region units 160B and isolation gaps 160A, so as to improve the photolithography limit accuracy, so as to form smaller-sized pitch units 160, so that the active array obtains smaller-sized pitch units 160, thereby satisfying the requirement of the specific small-pitch units 160.
in one embodiment, the minimum dimension of the exposure development between adjacent photoresists 120 is an odd multiple of the dimension of the pitch unit 160.
in one embodiment, referring to fig. 3 and 10, the photoresist 120 includes a first side 121 and a second side 122 opposite to the first side 121, and a distance between the first sides 121 of two adjacent photoresists 121 is a minimum dimension of exposure and development (the minimum dimension of exposure and development is a and is labeled in fig. 3 and 10), wherein the semiconductor substrate 110 includes three pitch units 160 at positions corresponding to the minimum dimension of exposure and development (the pitch of a pitch unit 160 is B and is labeled in fig. 10) so as to reduce the size of each pitch unit 160, thereby obtaining a smaller pitch unit 160 size. Generally, the minimum dimension of the exposure and development of the photoresist is 80-90 nm, and the dimension of the acquired pitch unit is about 30 nm. In fig. 3 and 10, a and B each represent a distance, a being a spacing distance of exposure and development, and B being a cell pitch.
In one embodiment, the pitch unit 160 has a size of 30nm, and the minimum size of the pitch unit 160 manufactured in this embodiment can reach 30nm to meet the size of the pitch unit 160 required by 30 nm.
in one embodiment, 1/2 of the thickness of the sacrificial layer 140 is equal to or greater than the thickness of the first barrier layer 130, and the sum of the lateral thickness of the sacrificial layer 140 at the first side and the lateral thickness of the first barrier layer 130 at the first side is less than 1/2 of the spacing between adjacent photoresists 120 to form the groove 141.
in one embodiment, the size of the photoresist 120, and the thicknesses of the first barrier layer 130 and the sacrificial layer 140 on the first side and the second side of the photoresist 120 are adjusted to adjust the width of the active area unit 160B and the size of the isolation gap 160A.
Specifically, the size of the photoresist 120 is proportional to the size of the isolation gap 160A, the thickness of the first barrier layer 130 is proportional to the active area cell width of the active area cell 160B, and the thickness of the sacrificial layer 140 is proportional to the size of the isolation gap 160A.
in this embodiment, the size of the photoresist 120 and the thickness of the deposition layer are changed to affect the size of the pitch unit 160 formed finally, and the specific size needs to be adjusted according to the manufacturing requirement.
In one embodiment, the first barrier layer 130 comprises silicon nitride, the sacrificial layer 140 comprises silicon oxide, and the second barrier layer 150 comprises silicon nitride.
In an embodiment, the etching includes dry etching, and the removing includes chemical mechanical polishing, and the embodiment can control the position and range of etching by dry etching and chemical mechanical polishing, so as to ensure that the size meets the requirements in the active array manufacturing process.
Example two
Based on embodiment 1, referring to fig. 10, this embodiment is an active array, including:
a semiconductor substrate; and
a plurality of active region cells 160B formed on the semiconductor substrate according to the manufacturing method described in the first embodiment and an isolation gap 160A between adjacent active region cells 160B;
Wherein the minimum feature size of the exposure and development size of the photoresist is an odd multiple of the feature size of the pitch unit 160.
In one embodiment, the feature size of the pitch unit 160 comprises 30nm
The active array of the present embodiment includes a semiconductor substrate and a pitch unit 160 composed of an active region unit 160B and an isolation gap 160A, and the feature size of the pitch unit 160 includes 30nm, which improves the minimum precision of photolithography, so that the random access memory device can satisfy some specific pitch unit 160 sizes.
EXAMPLE III
To achieve the above object, the present invention provides a random access memory including an active array as described in the above embodiments, a plurality of device units and a shallow trench isolation structure.
a plurality of device cells are formed on the active region unit 160B.
a shallow trench isolation structure is formed in the semiconductor substrate 110 by filling an isolation material in the isolation gap 160A.
wherein, when the feature size of the pitch unit 160 includes 30nm, the pitch between the unit and the shallow trench isolation structure also includes 30 nm.
the distance between the shallow trench isolation structure and the cell on the semiconductor substrate 110 of the ram device in this embodiment may be 30nm, and the memory array including the spacing cell 160 composed of the active region cell 160B and the isolation gap 160A on the semiconductor substrate 110 of the ram device satisfies the size requirements of some smaller spacing cells 160 of the ram device, and improves the performance of the ram device.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
in the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
the above disclosure provides many different embodiments, or examples, for implementing different features of the invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Claims (11)
1. A method of fabricating an active array, comprising:
Providing a semiconductor substrate, wherein photoresist is arranged on the semiconductor substrate at intervals;
Forming a first barrier layer on the semiconductor substrate and the photoresist;
Forming a sacrificial layer on the first barrier layer, wherein the sacrificial layer between two adjacent photoresists forms a groove;
Forming a second barrier layer on the sacrificial layer to fill the groove;
Removing the second barrier layer downwards along the upper surface of the second barrier layer to expose the upper surface of the sacrificial layer, wherein the second barrier layer in the groove forms a shielding part;
etching the sacrificial layer and the first barrier layer downwards from the upper surface of the sacrificial layer by taking the shielding part as a mask until the upper surface of the photoresist is exposed, wherein the first barrier layer is provided with a mask part attached to the side surface of the photoresist and a protection part positioned between the sacrificial layer and the semiconductor substrate, and the longitudinal thickness of the mask part is greater than that of the protection part;
Removing the photoresist, and etching the sacrificial layer downwards along the exposed part of the sacrificial layer until the protection part of the first barrier layer is exposed, and continuing to etch the exposed protection part of the first barrier layer until the semiconductor substrate is exposed, so as to form a plurality of barrier structures consisting of the mask part of the first barrier layer and the shielding part comprising the second barrier layer on the semiconductor substrate; and
Forming a spacing unit for constructing the active array, wherein the step of etching the semiconductor substrate by taking the blocking structure as a mask so as to form an isolation gap; removing the barrier structure to form an active area unit; wherein one of the active area cells and its adjacent one of the isolation gaps constitute a pitch cell.
2. The method of manufacturing according to claim 1, wherein a minimum dimension of exposure development between adjacent photoresists is an odd multiple of the pitch cell dimension.
3. The manufacturing method according to claim 2, wherein the photoresist comprises a first side and a second side opposite to the first side, and a distance between the first sides of two adjacent photoresists is a minimum dimension of exposure development, wherein the semiconductor substrate comprises three pitch units at positions corresponding to the minimum dimension of the exposure development.
4. The method of manufacturing of claim 2, wherein the pitch cell size comprises 30 nm.
5. the method of manufacturing of claim 3, wherein 1/2 a thickness of the sacrificial layer is equal to or greater than a thickness of the first barrier layer, and a sum of a lateral thickness of the sacrificial layer at the first side and a lateral thickness of the first barrier layer at the first side is less than 1/2 a spacing between adjacent photoresists.
6. the manufacturing method according to claim 3, wherein the size of the photoresist and the thicknesses of the first barrier layer and the sacrificial layer at the first side and the second side of the photoresist are adjusted to adjust the width of the active area unit and the size of the isolation gap.
7. The method of manufacturing according to claim 1, wherein the first barrier layer and the second barrier layer each comprise silicon nitride, and the sacrificial layer comprises silicon oxide.
8. The method of manufacturing according to claim 1, wherein the plurality of barrier structures including the shielding portion of the second barrier layer further include the sacrificial layer and the first barrier layer under the shielding portion to constitute a mask stack layer.
9. An active array, comprising:
A semiconductor substrate; and
A plurality of active region cells formed in the semiconductor substrate by the manufacturing method according to any one of claims 1 to 8 and an isolation gap between the adjacent active region cells;
wherein the minimum feature size of the exposure development size of the photoresist is an odd multiple of the feature size of the pitch unit.
10. The active array of claim 9, wherein a feature size of the pitch cells comprises 30 nm.
11. A random access memory, comprising:
An active array as claimed in claim 9;
A plurality of device cells formed on the active region cells; and
and the shallow trench isolation structure is formed in the semiconductor substrate by filling an isolation material in the isolation gap.
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| CN201810529033.3A CN110544688A (en) | 2018-05-29 | 2018-05-29 | Active array, method for manufacturing active array, and random access memory |
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| CN201810529033.3A CN110544688A (en) | 2018-05-29 | 2018-05-29 | Active array, method for manufacturing active array, and random access memory |
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