CN107968046A - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN107968046A CN107968046A CN201610915624.5A CN201610915624A CN107968046A CN 107968046 A CN107968046 A CN 107968046A CN 201610915624 A CN201610915624 A CN 201610915624A CN 107968046 A CN107968046 A CN 107968046A
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- photoetching agent
- agent pattern
- etching
- semiconductor substrate
- barrier layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.This method includes：Semiconductor substrate is provided, barrier layer is formed on the surface of the Semiconductor substrate；The photoetching agent pattern of inverted trapezoidal is formed on the barrier layer；Isotropic etching is carried out to the photoetching agent pattern, so that the side wall of the photoetching agent pattern is vertical with the surface of the Semiconductor substrate；Anisotropic etching is carried out, the barrier layer of the photoetching agent pattern side-wall outer side is removed with etching；Clearance wall is formed on the side wall of the photoetching agent pattern；Remove the photoetching agent pattern and the barrier layer.Manufacturing method according to the invention, optimizes the profile of target pattern, improves the uniformity of the critical size (CD) of target pattern, and this method cost is low, and On-line Control is easy, and then improves the yield and performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
With the increasingly increase of the semiconductor storage demand to high power capacity, the integration density of semiconductor storage by
To the concern of people, in order to increase the integration density of semiconductor storage, many different methods are employed in the prior art,
Double patterning technology (Double-Patterning, DP) is just as a kind of solution route in the semiconductor devices less than 32nm nodes
Widely received and applied in preparation process.
Double patterning technology (Double-Patterning, DP) is overcome by pitch fragment (pitch fragmentation)
K1 limitations, so as to be widely used in the preparation of semiconductor devices.At present in double patterning technology (Double-
Patterning, DP) have in technology self-aligned double patterning case (Self-aligned double patterning, SADP), photoetching-
Etching-photoetching-etching (Litho-Etch-Litho-Etch, LELE) and freeze coating etching (Litho-Freeze-
Litho, LFL).
Which kind of technology is selected in device fabrication process, it is necessary to consider the flexibility of every kind of technology, applicability and
The height of cost makes choice.Wherein self-aligned double patterning case technology (Self-aligned double patterning, SADP)
Realizing the etch capabilities of minimum spacing beyond the expectation to this method.
Positive photoetching rubber is usually selected during SADP and is patterned as the core (core) in double patterning, then is selected ultralow
Warm deposition process forms gap wall layer on the photoresist core, and the gap wall layer described in deposition process is to the photoresist core
Certain stress is produced, causes the sidewall performance of photoresist core to reduce, or even the inclination that deforms is serious, so as to turn to pattern
Shifting impacts, and makes the pattern contour serious distortion of transfer, the final performance and yield for influencing device.
Therefore, it is necessary to a kind of manufacture method of new semiconductor devices is proposed, to solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, including：
Semiconductor substrate is provided, barrier layer is formed on the surface of the Semiconductor substrate；
The photoetching agent pattern of inverted trapezoidal is formed on the barrier layer；
Isotropic etching is carried out to the photoetching agent pattern, so that the side wall of the photoetching agent pattern and the semiconductor
The surface of substrate is vertical；
Anisotropic etching is carried out, the barrier layer of the photoetching agent pattern side-wall outer side is removed with etching；
Clearance wall is formed on the side wall of the photoetching agent pattern；
Remove the photoetching agent pattern and the barrier layer.
Further, forming the method for the photoetching agent pattern of the inverted trapezoidal includes：
Spin coating negative photoresist on the semiconductor substrate；
The negative photoresist is exposed using light field light shield；
The negative photoresist not being exposed is developed and is removed, to form the photoetching agent pattern of the inverted trapezoidal.
Further, the developer solution used that develops includes n-butyl acetate.
Further, the barrier layer is low temperature oxide layer.
Further, forming the method for the low temperature oxide layer includes：Implement plasma at a temperature of less than 200 DEG C
Strengthen chemical vapor deposition.
Further, the isotropic etching is implemented using plasma etching.
Further, the plasma etching uses the etching gas for including HBr and He, alternatively, using includes oxygen
Etching gas.
Further, the anisotropic etching, the etching gas of the plasma etching are implemented using plasma etching
Body includes fluorocarbon.
Further, after the step of removing the photoetching agent pattern and the barrier layer, step is further included：
Using the clearance wall as Semiconductor substrate described in mask etch, transfer a pattern in the Semiconductor substrate.
Further, procedure below is included in the step of formation clearance wall on the side wall of the photoetching agent pattern：
Conformal deposited spacer material layer, to cover the photoetching agent pattern, the barrier layer and the part semiconductor
The surface that substrate exposes；
Etch-back removes the gap on the photoetching agent pattern top surface and on the semiconductor substrate surface of part
The wall material bed of material, to form the clearance wall.
Manufacturing method according to the invention, forms the photoetching agent pattern of inverted trapezoidal, then profit using negativity lithographic technology
With isotropic etching and anisotropic etching, the photoetching agent pattern of inverted trapezoidal is trimmed, so that the photoetching agent pattern
Side wall it is vertical with the surface of the Semiconductor substrate, and then ensure clearance wall and the institute formed on the side wall of photoetching agent pattern
State that the surface of Semiconductor substrate is vertical, be conducive to the pattern of clearance wall being transferred in Semiconductor substrate well, optimize mesh
The profile for case of marking on a map, improves the uniformity of the critical size (CD) of target pattern, and this method cost is low, and On-line Control is held
Easily, the yield and performance of device are improved and then.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A -1G are obtained by the correlation step based on double patterning technology manufacture semiconductor devices of an existing embodiment
The structure diagram of the device obtained；
Fig. 2A -2F manufacture the correlation step institute of semiconductor devices for existing another embodiment based on double patterning technology
The structure diagram of the device of acquisition；
Fig. 3 is the process flow chart according to the manufacture method of the semiconductor devices of one embodiment of the present invention；
Fig. 4 A-4F are obtained by a kind of correlation step that semiconductor devices is manufactured based on double patterning technology according to the present invention
Device structure diagram；
Fig. 5 A-5C trimmed by process to the photoetching agent pattern of inverted trapezoidal according to one embodiment of the present invention
Obtain the partial schematic diagram of device.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
The method that SADP described in the prior art prepares semiconductor devices has two kinds, the first, as shown in Figure 1A to Fig. 1 G,
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, sequentially form on a semiconductor substrate 100 advanced patterned film (APF,
Advanced Patterning Film) material 101 and bottom anti-reflection layer (BARC) 102, in bottom anti-reflection layer 102
Form patterned photoresist layer 103.
As shown in Figure 1B, the bottom anti-reflection layer 102 is patterned, to transfer a pattern to the bottom anti-reflection layer
In.
As shown in Figure 1 C, it is mask with bottom anti-reflection layer 102, the advanced composition membrane material 101 is etched, by pattern
It is transferred in advanced composition membrane material 101；
As shown in Fig. 1 D to Fig. 1 G, spacer material layer 104a is then deposited, to cover the advanced composition membrane material
101, the spacer material layer 104a is etched, to form clearance wall 104, then with clearance wall 104 is mask, etching semiconductor lining
Bottom 100, obtains target pattern.Need to deposit the spacer material layer using CVD method in the method, and in pattern
Needing to etch the hard mask layer during change, the etching condition of the hard mask layer is very harsh, and the method is not only cumbersome,
And cost is very high.
Second method can be selected in order to reduce cost, as shown in Fig. 2A to 2F, first, as shown in Figure 2 A, is directly existed
Photoetching agent pattern 201 is formed on the substrate 200, and the photoresist often uses positive photoresist, by photoetching process, exposure
The shape of photoetching agent pattern 201 after development is often trapezoid, and then, as shown in Figure 2 B, photoetching agent pattern 201 is lost
Trimming (trimming) is carved, to repair the shape of photoetching agent pattern 201, but the effect of the trimming in the step is very limited, repaiies
The side wall for cutting rear photoetching agent pattern 201 is still difficult vertical with the surface of Semiconductor substrate, then as shown in Figure 2 C, in the light
Spacer material layer 202a is deposited on photoresist pattern, but since the hardness of the photoresist is inadequate, be not enough to bear it is described between
The pressure when pressure of the gap wall material bed of material and etching, is also easy to be deformed photoetching agent pattern 201, with deformed light
Photoresist pattern is photoresist core, and the clearance wall 202 of formation also deforms, and when performing double patterning technology, makes the target to be formed
Gross distortion occurs for pattern, as shown in Fig. 2 D to Fig. 2 F, and then influences the yield and performance of device.In addition, also have other logical
Crossing the methods of hydrogeneous plasma carries out cure process to photoetching agent pattern improves the method for hardness of photoetching agent pattern, to change
The profile of kind figure, but the effect that this method is played is also very limited.
Therefore, although double patterning technology exists in the prior art, all there are the problem of process is cumbersome, cost is excessive,
The quality of product cannot be guaranteed again if cost is reduced, and makes device that serious deformation occur, causes product qualification rate to reduce, therefore
Need to be improved the above method, to eliminate the problem of presently, there are.
Embodiment one
In order to solve foregoing technical problem, the present invention provides a kind of manufacture method of semiconductor devices, such as Fig. 3 institutes
Show, it is mainly included the following steps that：
Step S301, there is provided Semiconductor substrate, barrier layer is formed on the surface of the Semiconductor substrate；
Step S302, forms the photoetching agent pattern of inverted trapezoidal on the barrier layer；
Step S303, to the photoetching agent pattern carry out isotropic etching so that the side wall of the photoetching agent pattern with
The surface of the Semiconductor substrate is vertical；
Step S304, carries out anisotropic etching, and the stop of the photoetching agent pattern side-wall outer side is removed with etching
Layer；
Step S305, clearance wall is formed on the side wall of the photoetching agent pattern；
Step S306, removes the photoetching agent pattern and the barrier layer.
Manufacturing method according to the invention, forms the photoetching agent pattern of inverted trapezoidal using negativity developing technique, recycles each
To isotropic etch and anisotropic etching, the photoetching agent pattern of inverted trapezoidal is trimmed, so that the side of the photoetching agent pattern
Wall is vertical with the surface of the Semiconductor substrate, and then ensures the clearance wall and described half formed on the side wall of photoetching agent pattern
The surface of conductor substrate is vertical, is conducive to the pattern of clearance wall being transferred in Semiconductor substrate well, optimizes target figure
The profile of case, improves the uniformity of the critical size (CD) of target pattern, and this method cost is low, and On-line Control is easy, into
And improve the yield and performance of device.
In the following, the manufacture method of the semiconductor devices of the present invention is done in detail with reference to figure 4A- Fig. 4 F and Fig. 5 A to Fig. 5 C
Introduce, wherein, Fig. 4 A-4F are obtained by a kind of correlation step that semiconductor devices is manufactured based on double patterning technology according to the present invention
The structure diagram of the device obtained；Fig. 5 A-5C be according to the photoetching agent pattern to inverted trapezoidal of one embodiment of the present invention into
The process of row trimming obtains the partial schematic diagram of device.
First, as shown in Figure 4 A, there is provided Semiconductor substrate 400, forms on the surface of the Semiconductor substrate 400 and stop
Layer 401, then, forms the photoetching agent pattern 402 of inverted trapezoidal on the barrier layer.
Specifically, as shown in Figure 4 A, the Semiconductor substrate 400 can be at least one in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator (SOI), be laminated silicon (SSOI) on insulator, be laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.
Alternatively, isolation structure can also be formed in the Semiconductor substrate, the isolation structure is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.Shallow trench isolation, the semiconductor lining are formed in the present invention
The channel layer of various traps (well) structure and substrate surface is also formed with bottom.
In general, the ion doping conduction type and channel layer ion doping conduction type phase of trap (well) structure are formed
Together, but concentration is low compared with gate channel layer, and the depth of ion implanting is general to enclose relatively extensively, while need to reach the depth more than isolation structure
Degree.
In addition, active area can be defined in Semiconductor substrate.It can also include on the active region other active
Device, for convenience, does not indicate in shown figure.
Wherein, Semiconductor substrate 400 can also include target material layer, which can be formed on substrate
Interconnection wiring layer, interlayer dielectric layer, gate material layers or hard mask layer.The constituent material of the interconnection wiring layer is selected from
At least one of tungsten, tungsten silicide, aluminium, titanium and titanium nitride.It is normal that the constituent material of the interlayer dielectric layer can be selected from low dielectric
Number (k) material or ultralow-k material film.The one kind of the constituent material of the gate material layers in polysilicon and aluminium.It is described to cover firmly
The constituent material of film layer is in oxide, undoped silicon glass, silicon-on-glass, SiON, SiN, SiBN, BN and high-g value
It is at least one.It should be noted that target material layer be optional and optionally, can be accepted or rejected according to actual conditions.
Barrier layer 401 is formed on the surface of the Semiconductor substrate 400, is formed on the surface of Semiconductor substrate 400
When having target material layer, the barrier layer 401 is formed in target material layer, and the material on the barrier layer 401 can include nitrogen
Compound, oxide, nitrogen oxides, especially silicon nitride, silica or silicon oxynitride etc..
In the present embodiment, the barrier layer 401 can be low temperature oxide (low temperature oxide, abbreviation
LTO) layer, low temperature oxide includes silica, and at a temperature of not higher than 200 DEG C, passes through plasma enhanced chemical
(PECVD) method of vapour deposition, via silica precursor (such as the silicon source such as silane gas or tetraethyl orthosilicate, Yi Jifen
The oxygen sources such as sub- oxygen and ozone) and form the LTO layers.In various embodiments, low temperature oxide can be at 120~200 DEG C
At a temperature of, formed by PECVD, and there can be 50~1000 angstroms of thickness.
Above-mentioned deposition temperature range for other suitable temperature only as an example, be equally applicable to the present invention.
The photoetching agent pattern 402 of inverted trapezoidal is formed on the barrier layer 401, wherein, any suitable method can be used
The photoetching agent pattern 402 of the inverted trapezoidal is formed, for example, developed using negativity (negative tone development, referred to as
NTD) photoetching process.Wherein, which refers to that the face vertical for semiconductor substrate surface is gone to cut the photoetching agent pattern 402
The shape in the section obtained.
In one example, the step of forming photoetching agent pattern 402 of inverted trapezoidal includes procedure below：
First, spin coating negative photoresist, negative photoresist can be commonly used in the art appoint on the semiconductor substrate
What suitable negative photoresist, such as the negative photoresist can include the light-sensitive materials such as polyvinyl alcohol laurate.
Then, the negative photoresist is exposed using light field light shield (Mask), which includes transparent area
With light tight area, wherein, transparent area corresponds to predetermined shape of photoetching agent pattern 402 formed etc..Utilize light field light shield (Mask)
Segment beam is passed through, is irradiated on negative photoresist, is reacted with negative photoresist, under the action of light, negative photo
Double bond in glue in light-sensitive material molecule is opened, and makes to crosslink between chain and chain, forms a kind of insoluble netted knot
Structure, so that preliminary figure is defined, wherein, light beam can be ultraviolet light or electron beam etc..
Then, the negative photoresist not being exposed is developed and removed, to form the photoetching agent pattern 402 of the inverted trapezoidal.
Develop to the negative photoresist after exposure, developer solution is sprayed onto semiconductor substrate surface, will not be exposed
Negative photoresist development remove, form the photoetching agent pattern 402 of final inverted trapezoidal.Dimethylbenzene or n-butyl acetate can be selected
(nBA, n-butyl acetate) is used as developer solution, can also use other suitable developer solutions, the negative photo that will be exposed
Glue development removes.
Then, as shown in Figure 4 B, isotropic etching (isotropic is carried out to the photoetching agent pattern 402
Etching), so that the side wall of the photoetching agent pattern 402 is vertical with the surface of the Semiconductor substrate 400, and then carry out
Anisotropic etching (anisotropic etching), the resistance of 402 side-wall outer side of photoetching agent pattern is removed with etching
Barrier 401.
Specifically, as shown in Figure 5A, the photoetching agent pattern 402 of inverted trapezoidal is carried out by a step isotropic etching first
(Trimming) is repaiied, so that the side wall of the photoetching agent pattern 402 is vertical with the surface of the Semiconductor substrate 400, Jin Erke
It is also vertical with the surface of Semiconductor substrate 400 with the clearance wall being formed in after guarantee on the side wall of photoetching agent pattern 402.
Wherein it is possible to implement the isotropic etching in the step, dry method etch technology bag using the method for dry etching
Include but be not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting etc..
In the present embodiment, implement the isotropic etching using plasma etching, the plasma etching uses
Include the etching gas of HBr and He, alternatively, using the etching gas for including oxygen.
The etching has high etch-rate to photoetching agent pattern 402, has low etching to barrier layer 401 below
Speed, namely the etching have photoetching agent pattern 402 with respect to the high etching selectivity on barrier layer 401.
Isotropic etching for photoetching agent pattern 402, tri- directions of X, Y and Z all to the photoetching agent pattern 402 into
Row etching.
Afterwards, as shown in figs. 5 b and 5 c, anisotropic etching is carried out, 402 side of photoetching agent pattern is removed with etching
The barrier layer 401 on the outside of wall.
Any suitable engraving method can be used to implement the anisotropic etching, such as wet etching or dry method erosion
Carve, wherein, wet etching uses the method for having high etch-rate to barrier layer 401.
It is preferred that implementing the anisotropic etching using the method for dry etching, dry etching includes but not limited to：Instead
Answer ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting etc..
Exemplarily, the anisotropic etching, the etching of the plasma etching are implemented using plasma etching
Gas includes fluorocarbon, for example, the etching gas of the dry etching can include CF4、CHF3Or other fluorocarbons
(CxFy) gas.
As an example, in the present embodiment, described to be etched to dry etching, the technological parameter of the dry etching includes：
Etching gas includes CF4、CHF3Deng gas, its flow is respectively 50sccm~500sccm, 10sccm~100sccm, and pressure is
2mTorr~50mTorr, wherein, sccm represents cc/min, and mTorr represents milli millimetres of mercury.
After anisotropic etching, remaining photoetching agent pattern 402 and barrier layer 401 below are collectively as core
(Core) pattern.
And the anisotropic etching has high etch-rate to barrier layer 401, there is low erosion to photoetching agent pattern 402
Etching speed, the anisotropic etching lose barrier layer 401 along the direction (Z-direction) vertical with 400 surface of Semiconductor substrate
Carve and remove, and be also possible to etch the photoetching agent pattern 402 for eliminating segment thickness at the same time.
Then, as shown in Figure 4 C, conformal deposited spacer material layer 403a, to cover the photoetching agent pattern 402, described
The surface that barrier layer 401 and the part Semiconductor substrate 400 are exposed.
The spacer material layer 403a can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.
Between the methods of including but not limited to chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition can be used formation is somebody's turn to do
Gap wall material bed of material 403a, it is, for example, possible to use the method for low temperature chemical vapor deposition is formed.
Then, as shown in Figure 4 D, etch-back is removed on 402 top surface of photoetching agent pattern and the part semiconductor serves as a contrast
The spacer material layer on 400 surface of bottom, with the shape on the side wall of the photoetching agent pattern 402 and the barrier layer 401
Into clearance wall 403.
The method that the etch-back can use dry etching, dry method etch technology include but not limited to：Reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting.Dry method is carried out preferably by one or more RIE step
Etching.
After the etch-back process, by the spacer material layer and part semiconductor on 402 top surface of photoetching agent pattern
Spacer material layer etching on substrate surface removes, and only exposure is positioned at the photoetching agent pattern 402 and the barrier layer 401
Spacer material layer on side wall, forms clearance wall 403, which is used as the mask of the etching carried out afterwards, so that will
The pattern of clearance wall 403 is transferred in Semiconductor substrate 400 below.
Then, as shown in Figure 4 E, the photoetching agent pattern 402 and the barrier layer 401 are removed, retains the clearance wall
403 are used as mask.
Any commonly employed engraving method can be used to remove the photoetching agent pattern 402 and the barrier layer 401, including but not
It is limited to wet etching or dry etching, dry method etch technology includes but not limited to：Reactive ion etching (RIE), ion beam erosion
Quarter, plasma etching or laser cutting.Dry etching can select CF4、CHF3In addition N is added2、CO2、O2In a kind of work
To etch atmosphere, wherein gas flow is CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, institute
It is 30-150mTorr, etching period 5-120s to state etching pressure.
Finally, as illustrated in figure 4f, pattern is shifted for Semiconductor substrate 400 described in mask etch with the clearance wall 403
Into the Semiconductor substrate 400.
Wherein, can be to cover with the clearance wall 403 when on 400 surface of Semiconductor substrate formed with target material layer
Film, etches the target material layer, transfers a pattern in target material layer, and can also with the clearance wall 403 for mask,
Semiconductor substrate 400 is etched, is transferred a pattern in Semiconductor substrate 400, target pattern is formed, for example, fin structure etc..
It can include but not limited to wet method erosion according to the property for the material for being actually needed etching using suitable engraving method
Quarter or dry etching, it is preferred that using dry etching.And since the clearance wall 403 of formation is perpendicular to Semiconductor substrate 400
Surface, therefore, in the etching process of the step, can be very good to transfer a pattern in Semiconductor substrate, and ensure to turn
Pattern after shifting has good profile.
Finally, clearance wall 403 is removed.Exemplarily, in this step with diluted hydrofluoric acid DHF (wherein comprising HF,
H2O2And H2O) wet method peels off the clearance wall.Wherein, the concentration of the DHF does not limit strictly, in the present invention preferably
HF:H2O2:H2O=0.1-1.5:1:5.
So far, the introduction of the correlation step of the manufacture method of the semiconductor devices of the embodiment of the present invention is completed.Except upper
State outside step, the manufacture method of the present embodiment can also include other among above-mentioned each step or between different steps
Step, these steps can realize that details are not described herein again by the various techniques in current technique.
In conclusion manufacturing method according to the invention, uses the photoresist of negativity lithographic technology formation inverted trapezoidal
Pattern, recycles isotropic etching and anisotropic etching, the photoetching agent pattern of inverted trapezoidal is trimmed, so that the light
The side wall of photoresist pattern is vertical with the surface of the Semiconductor substrate, and then ensures between being formed on the side wall of photoetching agent pattern
Gap wall is vertical with the surface of the Semiconductor substrate, is conducive to the pattern of clearance wall being transferred in Semiconductor substrate well,
The profile of target pattern is optimized, improves the uniformity of the critical size (CD) of target pattern, and this method cost is low, online
Control is easy, and then improves the yield and performance of device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided, barrier layer is formed on the surface of the Semiconductor substrate；The photoetching agent pattern of inverted trapezoidal is formed on the barrier layer；Isotropic etching is carried out to the photoetching agent pattern, so that the side wall of the photoetching agent pattern and the Semiconductor substrate Surface it is vertical；Anisotropic etching is carried out, the barrier layer of the photoetching agent pattern side-wall outer side is removed with etching；Clearance wall is formed on the side wall of the photoetching agent pattern；Remove the photoetching agent pattern and the barrier layer.
- 2. manufacture method as claimed in claim 1, it is characterised in that form the method bag of the photoetching agent pattern of the inverted trapezoidal Include：Spin coating negative photoresist on the semiconductor substrate；The negative photoresist is exposed using light field light shield；The negative photoresist not being exposed is developed and is removed, to form the photoetching agent pattern of the inverted trapezoidal.
- 3. manufacture method as claimed in claim 2, it is characterised in that the developer solution used that develops includes the positive fourth of acetic acid Ester.
- 4. manufacture method as claimed in claim 1, it is characterised in that the barrier layer is low temperature oxide layer.
- 5. manufacture method as claimed in claim 4, it is characterised in that forming the method for the low temperature oxide layer includes： Implement plasma enhanced chemical vapor deposition at a temperature of less than 200 DEG C.
- 6. manufacture method as claimed in claim 1, it is characterised in that implement the isotropism using plasma etching and lose Carve.
- 7. manufacture method as claimed in claim 6, it is characterised in that the plasma etching, which uses, includes HBr's and He Etching gas, alternatively, using the etching gas for including oxygen.
- 8. manufacture method as claimed in claim 1, it is characterised in that implement the anisotropy using plasma etching and lose Carve, the etching gas of the plasma etching includes fluorocarbon.
- 9. manufacture method as claimed in claim 1, it is characterised in that removing the photoetching agent pattern and the barrier layer After step, step is further included：Using the clearance wall as Semiconductor substrate described in mask etch, transfer a pattern in the Semiconductor substrate.
- 10. manufacture method as claimed in claim 1, it is characterised in that form gap on the side wall of the photoetching agent pattern The step of wall, includes procedure below：Conformal deposited spacer material layer, to cover the photoetching agent pattern, the barrier layer and the part Semiconductor substrate The surface exposed；Etch-back removes the gap wall material on the photoetching agent pattern top surface and on the semiconductor substrate surface of part The bed of material, to form the clearance wall.
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