JP2007305970A - Method of forming integrated circuit pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern forming method which can suppress imbalance of characteristics and wasteful area on a chip area. <P>SOLUTION: The method includes: a step of forming a resist patter by means of a lithography process on a multilayer film formed on a substrate to be processed, processing a first film of a top layer of the multilayer film using the resist as a mask, forming a pattern of the first film, partially exposing the pattern of the first film by resist pattern formation, selectively slimming the exposed pattern of the first film, processing a second film using the first film as a mask, forming a multilayer pattern of the first and second films, partially exposing the multilayer pattern of the first and second films by resist pattern formation in the lithography process, removing the exposed first film by etching, forming a sidewall pattern of a third film on sidewalls of the pattern of the second film as well as the multilayer pattern of the first and second films, processing a fourth film using the pattern of the first to third films as a mask, and removing the first to third films. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pattern forming method for a semiconductor integrated circuit, and more particularly to a method for forming a fine pattern with high accuracy using a sidewall leaving process.

Acceleration of pattern dimension miniaturization in the development of semiconductor integrated circuits is unknown. Miniaturization is promoted by optical lithography technology, and it will continue for some time. The relationship between the pattern size (HP) expressed in half pitch, the wavelength (λ) of the exposure apparatus used to realize the pattern size, and the lens numerical aperture (NA) is expressed by the Rayleigh equation (HP = k ₁ * λ / NA). If the pattern size is determined by market requirements (cost, device performance), the k ₁ factor included in this equation is a value indicating the difficulty level of the lithography technology that realizes it (if the k ₁ factor is small, lithography is performed). Is difficult).

In general, the resolution limit of the pattern dimension by lithography is k ₁ = 0.25, and if k ₁ is less than 0.275, pattern formation by lithography becomes extremely difficult. Lithography in the region of k ₁ <0.275 results in two-beam interference due to strong deformation illumination in which light that has passed through only two outermost peripheral points of the pupil plane forms an image on the wafer. The illumination stop for producing this two-beam interference is a so-called dipole. Under such strong deformation illumination conditions, the resolution of patterns other than the target minimum pattern pitch is extremely deteriorated. For this reason, strong deformation illumination such as dipole illumination is often used with double exposure technology.

  In the case of double exposure, formation of the minimum pattern pitch uses dipole illumination, and formation of patterns other than the minimum pitch uses weak modified illumination such as annular illumination to form the entire LSI pattern. Such a double exposure technique is more easily applied to a memory device in which the minimum pattern pitch is defined only in the memory cell portion than a logic device having a strong pattern randomness. In this case, the memory cell portion is formed by strong deformation illumination such as dipole illumination, and the other pattern is formed by weak deformation illumination technology such as annular illumination.

However, the acceleration of miniaturization of semiconductor devices has required pattern dimensions lower than k ₁ <0.25. In this region, it is required to form a pattern pitch finer than the minimum pattern pitch that can be formed by lithography. As one of such methods, a pattern forming technique based on a sidewall leaving process is known (for example, see Patent Document 1). FIG. 1 to FIG. As shown in FIG. 8, a resist pattern is formed on the first film, which will later become a dummy pattern, by a lithography process. The first film is etched using the resist pattern as a mask to form a dummy pattern, and then the resist is peeled off. Next, a second film that is a material to be a sidewall is deposited on the dummy pattern. Thereafter, when the second film is etched by RIE, a sidewall pattern is formed on the sidewall of the dummy pattern. After the dummy pattern is removed, the film to be processed is etched using the sidewall pattern as a mask. At this time, a hard mask is selected as a film to be processed, and a finer pattern can be formed by slimming the hard mask (narrowing the line width). Finally, the side wall pattern is peeled off to complete pattern formation by the side wall leaving process. When a hard mask is used, the hard mask is peeled off after etching the base film.

The following points can be cited as features of the sidewall leaving process.
1) A pattern formed by lithography has a pitch twice the design pitch, that is, a pattern can be formed by an exposure apparatus two to three generations before.

2) The design pattern and the lithography target pattern (dummy pattern) are different.

3) The same pattern size is formed on the entire surface.

4) Closed loop pattern.

5) The dimensional accuracy is determined only by the film thickness of the side wall pattern and has high dimensional controllability.

6) Line edge roughness is small.

  The integrated circuit pattern is formed from patterns having various line widths as well as the minimum line width. Therefore, the above 3) is disadvantageous in forming a complicated integrated circuit pattern. Various proposals have been made as a process of forming a pattern size having a minimum line width by a sidewall leaving process and forming a pattern other than the minimum line width (see, for example, Patent Document 2).

However, in each of these proposals, the minimum line width pattern and the other pattern are divided and lithography is performed with another mask (double exposure process). For this reason, misalignment occurs between the minimum line width pattern and the other patterns. In order to prevent this misalignment from affecting the device, it is necessary to design with a sufficient distance (a misalignment margin) between both patterns. This misalignment margin directly affects the chip size of the device, resulting in an unnecessarily large chip and a high cost process.
US Pat. No. 6,063,688 US Pat. No. 6,475,891

  As described above, while the side wall remaining pattern forming method has various advantages, since the entire surface is formed with the same pattern size, when patterns of various sizes are mixed, it is necessary to expose for each size, Considering the misalignment at that time, it is necessary to take a margin in the pattern design, which is a cause of increasing the chip size. In addition, when misalignment occurs in a pattern in which the same transistor is repeatedly formed, a characteristic imbalance occurs between the formed transistors, causing a decrease in yield due to a characteristic defect.

  The present invention has been made in view of the above circumstances, and provides an integrated circuit pattern forming method capable of suppressing characteristic imbalance due to misalignment and waste generation on a chip area and simplifying the process. With the goal.

In order to solve the above problems, a first method of forming an integrated circuit pattern according to the present invention includes a step of forming a resist pattern on a laminated film formed on a processing substrate by a lithography process,
Using the resist pattern as a mask, the first film of the uppermost layer of the laminated film is processed to form a pattern made of the first film, and the pattern made of the first film is partially formed by forming a resist pattern by a lithography process A step of selectively exposing, a step of selectively narrowing the pattern of the exposed first film by an etching process, and a second under the first film using the first film as a mask Processing the film to form a laminated pattern composed of the first and second films; partially exposing the laminated pattern of the first and second films by forming a resist pattern by a lithography process; Removing the exposed first film by etching and exposing the second film; a laminated pattern of the first and second films; and a sidewall portion of the pattern of the second film Forming a sidewall pattern made of a third film; removing the exposed second film portion after forming the sidewall pattern; and removing the exposed second film portion. A step of processing a fourth film below the first, second, and third films using the patterns of the first, second, and third films as a mask; and And a step of removing the third film.

  A second method of forming an integrated circuit pattern according to the present invention includes a step of forming a resist pattern on a laminated film formed on a processing substrate by a lithography process, and a step of forming the uppermost layer of the laminated film using the resist pattern as a mask. Processing the first film, forming a pattern made of the first film, thinning the exposed pattern made of the first film by an etching process, and using the first film as a mask Processing a second film under the first film to form a stacked pattern of the first and second films; and forming a stacked pattern of the first and second films by a lithography process. A step of partially exposing the film, a step of removing the exposed first film by etching to expose the second film, a laminated pattern of the first and second films, Forming a sidewall pattern made of a third film on a sidewall portion of the second film pattern; removing the exposed second film portion after forming the sidewall pattern; and exposing the exposed portion. After the second film portion is removed, the fourth film under the first, second, and third films is processed using the pattern of the first, second, and third films as a mask. And a step of removing the first, second, and third films.

  Further, a third method of forming an integrated circuit pattern according to the present invention includes a step of forming a resist pattern by a lithography process on a laminated film formed on a processing substrate, a step of thinning the resist pattern by an etching process, Processing the first film of the uppermost layer of the laminated film using the thinned resist pattern as a mask to form a pattern made of the first film; and forming the pattern of the first film using the first film as a mask. Processing the second film below to form a laminated pattern comprising the first and second films, and sidewalls comprising a third film on the side walls of the laminated pattern of the first and second films A step of forming a pattern, a step of partially exposing the pattern made of the first, second, and third films by forming a resist pattern by a lithography process after forming the sidewall pattern; and And forming the exposed first and second films by etching, and using the patterns of the first, second, and third films as a mask. A step of processing a fourth film below the third film, and a step of removing the first, second, and third films.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the formation method of the integrated circuit pattern which can suppress the characteristic imbalance based on misalignment and the waste generation on a chip area, and can simplify a process.

  Before describing the embodiment of the present invention, the problem of the method for forming a sidewall pattern in the double exposure process will be described in more detail using a NAND flash memory as an example. FIG. 1 is an equivalent circuit diagram of one string of a NAND flash memory. A plurality of memory cells MC connected in series are provided between the select transistors ST1 and ST2. Selection gate lines SG1 and SG2 are connected to the gates of the selection transistors ST1 and ST2, respectively, and word lines (control gate lines) WL1 to WLn are connected to the control gate of the memory cell MC. One of the source and the drain of the selection transistor ST1 is connected to the bit line BL, and one of the source and the drain of the selection transistor ST2 is connected to the source line SL.

  In an actual memory IC, a plurality of NAND strings are arranged in a matrix in the memory cell portion, and a memory cell control circuit and the like are arranged in a peripheral circuit portion adjacent to the memory cell portion. FIG. 2 shows a part thereof in a sectional view, in which two NAND strings (only the opposite ends are shown) are arranged so as to oppose the selection transistors ST at the ends, On the right side of the part, the gate electrode of one transistor of the peripheral circuit part is drawn. The gate structures of these transistors have the same layer configuration as is well known. That is, on the semiconductor substrate 1, a first gate insulating film 2, a first polysilicon gate electrode film (floating gate) 3, a second gate insulating film (inter-gate electrode insulating film) 4, a second polysilicon A stack of gate electrode films (control gates) 5 is processed by photolithography and separated.

  As described above, when the stacked gate is formed with the side wall remaining, only the same pattern size can be formed. For this reason, the formation of the memory cells MC constituting the word line portion (WL portion) and the formation of the selection transistor ST and the peripheral transistor must be formed separately in the lithography process. That is, since the exposure process is performed twice, it is necessary to look at a margin for misalignment in photolithography. As shown in FIG. 2, the misalignment occurs between the WL portion and the selection gate portion (SG portion), and between the WL portion and the peripheral portion.

  As described above, when the sidewall-remaining process is applied to a device in which a pattern having different line widths such as a WL portion and an SG portion exists in the memory cell array, such as a gate layer of a NAND flash memory, the above-described problem is very difficult. Become serious. It is necessary to ensure a misalignment margin even in a memory cell array portion (usually 60 to 80% area occupancy) having a high area occupancy in the chip, and an increase in the memory cell area remains as it is. This is because the size increases.

  Here, it is assumed that a misalignment margin is not secured in the memory cell. As shown in FIG. 3, there are adjacent select gates STa and STb (they are made of the same mask, so there is no mutual misalignment), and the memory cell MCa adjacent to the select gate STa is closer than a specified interval. Suppose that the memory cell MCb adjacent to the select gate STb is wider than the specified interval and misalignment occurs. Using the stacked gates ST, MC as a mask, source / drain diffusion layers d1, d2, d3, etc. are formed by ion implantation. Since the ion implantation becomes deeper as the distance between the masks is wider, the depth of the diffusion layer is d1 <d2 and d3. Since the depth of the diffusion layer and the diffusion length under the stacked gate are proportional, comparing the effective channel length Leff of the memory cell MCa in the WL portion with the effective channel length Leff of the memory cell MCb, MCa> MCb. On the other hand, the effective channel length Leff of the selection transistors MTa and MTb is STa> STb.

The above is a case where only the effective channel length is considered, but the following matters can be cited as problems of the double exposure process.
1) The characteristics (Vth, Ion, Ioff) of the left and right select transistors (STa, STb) are asymmetric.
2) The transistor characteristics (Vth, Ion, Ioff) of the left and right first memory cells (MCa, MCb) are asymmetric.
3) In order to avoid the above, the area in the cell increases (the SG-WL distance needs to be increased).
4) In order to match the transistor characteristics of MCa with other MCs, it is necessary to tune the ion implantation process (the process becomes complicated such as double ion implantation).
5) Regarding the misalignment between the WL portion and the peripheral portion, if it is attempted to avoid this, the area increases.

  Among these, in 1) and 2), the MCb threshold voltage decreases due to the small effective channel length Leff of MCb, resulting in overwritten cells. This raises the threshold voltage at the time of reading, and the NAND string does not turn on, and reading cannot be performed. In order to avoid this, a complicated process such as 4) is required, which results in an expensive process. The present invention provides a solution to such problems.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
4 to 17 show process flows of the semiconductor integrated circuit device according to the first embodiment of the present invention. In the present embodiment, a process flow of the NAND flash memory will be described as an example. First, a tunnel oxide film 2 as a first film, a first polysilicon film 3 serving as a floating gate, a high dielectric film (inter-gate insulating film) 4 and a control gate are formed on a silicon substrate 1 which is a substrate to be processed. A second polysilicon film 5 is stacked, and a silicon oxide film (second film) 6 and a hard mask material (third film) 7 which are sacrificial films are deposited (FIG. 4).

Here, Al ₂ O ₃ is used as the high dielectric film 4 and a glass (BSG) film containing boron is used as the silicon oxide film 6. As the hard mask 7, a film having an etching selectivity with respect to the BSG film, for example, a silicon nitride film (SiN film) can be considered. In the drawing, EI is a space for establishing electrical continuity between the floating gate 3 and the control gate 5 at a location that will later become a selection gate (SG) portion, and is formed in advance by a lithography process and an etching process.

  First, a resist pattern (first mask pattern) is formed in a WL (word line) portion, an SG portion, and a peripheral circuit portion in a first lithography process (FIG. 5). The pattern pitch P1 and the resist dimension L1 of the resist pattern in the WL portion are both about twice the pitch P2 and the transistor gate length L2 of the MC transistor pattern that will be the final WL (see FIG. 17 described later). That is, when a 55 nm gate length transistor is required in the WL portion, the resist width of the WL portion is about 110 nm and the resist pattern pitch is about 220 nm. The resist pattern in the SG portion is about 1.5 to 4 times the WL transistor size. The resist pattern in the peripheral circuit portion has a random pattern size according to the circuit pattern. The resist film thickness is about 200 to 400 nm.

Using this resist pattern 8 as a mask, the underlying hard mask material is etched to form a hard mask 7 pattern (second mask pattern) (FIG. 6). As an etching process, anisotropic etching (RIE) is generally used. The figure shows a state in which the resist 8 is peeled after the hard mask 7 is etched. As the resist stripping process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used.

  Next, in the second lithography step, the hard mask pattern of the SG portion and the peripheral circuit portion is covered with the resist 9, and only the hard mask pattern of the WL portion is exposed (FIG. 7). At this time, the film thickness of the resist 9 is larger than the film thickness of the resist 8 in the first lithography process. Next, the exposed hard mask pattern 7 is slimmed by an etching process (FIG. 8).

  The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method, and the process is determined by the hard mask material, controllability of the slimming amount, and the like. For example, when a SiN film is selected as the hard mask, wet etching with hot phosphoric acid can be used. The amount to be thinned by slimming is about ½ (around one side) of the final gate length in the WL portion. That is, when a 55 nm WL transistor size is required, the slimming amount is about 27.5 nm per side.

After the slimming process of the hard mask in the WL portion is completed, the resist pattern 9 in the SG portion and the peripheral circuit portion is removed (FIG. 9). As the resist stripping process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used.

  Next, the underlying BSG mask is etched using the hard mask pattern 7 as a mask (FIG. 10). As an etching process, anisotropic etching (RIE) is generally used. At this time, the SG portion and the peripheral circuit portion have the BSG pattern 6 having substantially the same size as the resist pattern 8 formed in the first lithography process, and the WL portion has about 1 / of the resist pattern 8 formed in the first lithography step. A BSG pattern 6 'having a size of 2 is formed. When the BSG film 6 is etched, the etching is performed under conditions where the hard mask 7 remains on the BSG film 6 (an etching condition in which the etching selectivity of the BSG film 6 with respect to the hard mask 7 is high).

  Next, in the third lithography step, the hard mask 7 / BSG film 6 laminated pattern in the SG portion and the peripheral circuit portion is covered with a resist (third mask pattern) 10, and the hard mask 7 / BSG film 6 in the WL portion is covered. 'Only the laminated pattern is exposed (FIG. 11). At this time, the film thickness of the resist 10 is larger than the film thickness of the resist 8 in the first lithography process. Further, the same exposure mask as the second mask pattern can be used as the third mask pattern.

  Next, only the hard mask 7 on the exposed hard mask 7 / BSG film 6 ′ laminated pattern is removed by an etching process (FIG. 12). The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method, and the process is determined by a hard mask material or the like. For example, when a SiN film is selected as the hard mask 7, wet etching with hot phosphoric acid can be used.

After removing the hard mask in the WL portion, the resist pattern 10 is peeled off (FIG. 13). As the resist 10 peeling process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used. Through the steps so far, the BSG pattern 6 'is formed in the WL portion at a pitch of about twice the final transistor pattern pitch. Further, a stacked pattern of the hard mask 7 / BSG film 6 is formed in the SG portion and the peripheral circuit portion.

  Next, sidewall patterns (fourth film) 11 are formed on the sidewalls of these patterns (FIG. 14). Although details of the side wall pattern forming method are omitted, there is a method in which an insulating film such as a silicon oxide film or a silicon nitride film as a side wall material is deposited on the pattern using a CVD method or the like, and the pattern is left only on the side wall by etching by RIE. It is common.

  The dimension of the sidewall pattern 11 is set so as to substantially match the deposited film thickness of the sidewall material and to be the same value as the WL dimension of the NAND flash memory of that generation. For example, when a WL transistor size of 55 nm is required, the deposited film thickness is 55 nm. Since the dimension of the sidewall pattern 11 substantially matches the deposited film of the sidewall film, the dimension controllability is extremely high. Next, the BSG film 6 'exposed on the surface is removed by etching. For this etching, a VPC method or the like is generally known. At this time, only the WL part is removed from the BSG film, and the BSG film 6 in the SG part and the peripheral circuit part is covered with the hard mask 7, so the BSG film 6 is not removed (FIG. 15).

Next, the gate structure of the NAND flash memory (tunnel oxide film 2 / first polysilicon layer 3 / Al ₂ O _{3 layer} 4 / second polysilicon layer 5) as a base is used, and the WL portion uses the sidewall pattern 11 as a mask. The SG portion and the peripheral circuit portion are etched using the sidewall pattern 11, the hard mask pattern 7, and the BSG film 6 as a mask (FIG. 16).

  Finally, the sidewall pattern 11, the hard mask pattern 7, and the BSG film 6 that serve as a mask are removed by etching (FIG. 17). A pattern having no misalignment between the SG portion and the WL portion, and the peripheral circuit portion and the WL portion is completed. By adopting the above steps, it is possible to manufacture a NAND flash memory with uniform characteristics of individual memory cells without having to look at a misalignment margin between the WL portion and the SG portion or the peripheral portion.

(Second Embodiment)
In the second embodiment, another process flow will be described using a NAND flash memory as an example. First, the same processing as in FIGS. 4 and 5 of the first embodiment is performed on the silicon substrate (substrate to be processed) 1. That is, the pattern pitch and the resist dimension of the resist pattern (first mask pattern) 8 in the WL portion are both about twice the pitch of the transistor pattern and the transistor (gate length) dimension that will be the final WL. That is, when a 55 nm WL transistor size is required, the resist size of the WL portion is about 110 nm and the resist pattern pitch is about 220 nm. The resist pattern 8 in the SG portion is about 1.5 to 4 times the WL transistor size. The resist pattern 8 in the peripheral circuit portion has a random pattern size according to the circuit pattern. The resist film thickness is about 200 to 400 nm.

Next, as shown in FIG. 18, the underlying hard mask material (third film) is etched using the resist pattern 8 as a mask to form a hard mask 7 pattern. As an etching process, anisotropic etching (RIE) is generally used. In the figure, the resist is peeled after the hard mask is etched. As the resist stripping process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used.

  Next, the exposed hard mask pattern 7 is slimmed by an etching process (FIG. 19). The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method, and the process is determined by the hard mask material, controllability of the slimming amount, and the like. For example, when a SiN film is selected as the hard mask, wet etching with hot phosphoric acid can be considered. The amount to be thinned by slimming is about ½ (around one side) of the transistor size that will be the final WL. That is, when a 55 nm WL transistor size is required, the slimming amount is about 27.5 nm per side.

  Next, the underlying BSG film (second film) 6 is etched using the hard mask pattern 7 as a mask (FIG. 20). As an etching process, anisotropic etching (RIE) is generally used. At this time, the BSG pattern 6 corresponding to about ½ of the size of the resist pattern 8 formed in the first lithography process is formed in the WL portion. When the BSG film 6 is etched, the etching is performed under conditions where the hard mask 7 remains on the BSG film 6 (an etching condition in which the etching selectivity of the BSG film 6 with respect to the hard mask 7 is high).

  Next, in the second lithography step, the laminated pattern of the hard mask 7 / BSG film 6 in the SG portion and the peripheral circuit portion is covered with a resist (second mask pattern) 9, and the hard mask 7 / BSG film in the WL portion is covered. Only the 6 ′ laminate pattern is exposed (FIG. 21). At this time, the film thickness of the resist 9 is larger than the film thickness of the resist 8 in the first lithography process.

Next, only the hard mask 7 on the exposed hard mask 7 / BSG film 6 'laminated pattern is removed by an etching process (FIG. 22). The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method, and the process is determined by a hard mask material or the like. For example, when a SiN film is selected as the hard mask 7, wet etching with hot phosphoric acid can be considered. After removing the hard mask in the WL portion, the resist pattern is peeled off (FIG. 23). As the resist stripping process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used. Through the steps so far, the BSG pattern is formed in the WL portion at a pitch about twice the final transistor pattern pitch. Further, a stacked pattern of the hard mask 7 / BSG film 6 is formed in the SG portion and the peripheral circuit portion.

  Next, sidewall patterns (fourth film) 11 are formed on the sidewalls of these patterns (FIG. 24). The method for forming the sidewall pattern 11 is the same as that in the first embodiment. Next, the BSG film 6 'exposed on the surface is removed by etching. For this etching, a VPC method or the like is generally known. At this time, only the WL part is removed from the BSG film, and the BSG film 6 in the SG part and the peripheral circuit part is covered with the hard mask 7, so the BSG film 6 is not removed (FIG. 25).

Next, the gate structure of the NAND flash memory (tunnel oxide film 2 / first polysilicon electrode 3 / Al ₂ O ₃ film 4 / second polysilicon electrode 5) as a base is used, and the WL portion uses the sidewall pattern 11 as a mask. The SG portion and the peripheral circuit portion are processed using the sidewall pattern 11, the hard mask pattern 7, and the BSG film 6 as a mask (FIG. 26). Finally, the sidewall pattern 11, the hard mask pattern 7, and the BSG film 6 that became the mask are removed by etching (FIG. 27). A pattern having no misalignment between the SG portion and the WL portion, and the peripheral circuit portion and the WL portion is completed.

  According to the second embodiment, an equivalent effect can be achieved with a simpler process than in the first embodiment.

  Here, in the above-described embodiment, the relationship between the size of the resist pattern formed first and the final pattern size will be described in plan view. FIG. 28A is a schematic plan view of the resist 8 in FIG. 5, which is formed with a width L1 and a pitch P1. FIG. 28B shows a planar shape of the hard mask 7 after slimming in the WL portion of FIG. 8, and has a width L1 / 2 and a pitch P1. FIG. 28C is a plan view in which the side wall 11 is formed in FIG. 14, and the side wall 11, the width of the BSG film 6, and the interval between the adjacent side walls 11 are all processed to be L1 / 2. FIG. 28D is a plan view showing a state in which the stacked gate structure of the WL portion in FIG. 17 is formed, and the width (gate length) of the sidewall gate is L2 = L1 / 2 and the pitch P2 = P1 / 2.

  In general, the ratio between the gate length and the gate interval is often 1: 1 as a design. However, in the actual product level, it is preferable to control in the range of P2 / P1 = 0.4 to 0.6.

(Third embodiment)
In the third embodiment, a NAND flash is taken as an example, and still another process flow is described. First, the same processing as in FIGS. 4 and 5 of the first embodiment is performed on the silicon substrate 1.

  Next, as shown in FIG. 29, the resist pattern 8 is slimmed by an etching process. The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method. Etching of an antireflection film material (formed directly under the resist for the purpose of suppressing reflection from the base, not shown). It is also possible by RIE over-etching used in the above. The process is determined by the antireflection film material, the slimming amount controllability, and the like. The amount of thinning by slimming is about ½ (per one side) of the transistor size that will be the final WL. That is, when a 55 nm WL transistor size is required, the slimming amount is about 27.5 nm per side.

Next, as shown in FIG. 30, the underlying hard mask material 7 is etched using the slimmed resist pattern 8 as a mask to form a hard mask pattern. As an etching process, anisotropic etching (RIE) is generally used. FIG. 30 shows a state where the resist is peeled after etching the hard mask. As the resist stripping process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used.

  Next, as shown in FIG. 31, the underlying BSG layer 6 is etched using the hard mask 7 as a mask. As an etching process, anisotropic etching (RIE) is generally used. At this time, the SG portion and the peripheral circuit portion have a BSG pattern 6 having a dimension obtained by subtracting a thin portion from the resist pattern 8 formed in the first lithography step, and the WL portion is a resist pattern formed in the first lithography step. Thus, the BSG pattern 6 having a size of about 1/2 of 8 is formed. When the BSG pattern 6 is etched, the etching is performed under a condition that a hard mask remains on the BSG film (an etching condition with high etching selectivity of the BSG film with respect to the hard mask).

  Next, as shown in FIG. 32, sidewall spacers 11 are formed on the sidewalls of these patterns. Although details of the method for forming the sidewall spacers are omitted, an insulating film such as an oxide film or a nitride film serving as a sidewall material is deposited so as to cover the BSG pattern 6 using a CVD method or the like, and the BSG pattern 6 is etched by RIE. A method of leaving an insulating film only on the side wall is common. The film thickness in the horizontal direction of the side wall spacer is set so as to substantially match the deposited film thickness of the side wall material and to be the same value as the WL dimension of the NAND flash memory of that generation. Since the film thickness in the horizontal direction of the sidewall spacer substantially matches the deposited film of the sidewall film, the dimensional controllability is extremely high.

  Next, as shown in FIG. 33, in the second lithography process, the region including the hard mask pattern 7 in the SG portion and the peripheral circuit portion is covered with a resist 9, and only the region including the hard mask pattern 7 in the WL portion is covered. Expose. The film thickness of the resist 9 at this time is generally larger than the film thickness of the resist 8 in the first lithography process.

Next, as shown in FIG. 34, only the laminated pattern of the hard mask 7 / BSG film 6 'in the exposed region is removed by an etching process. The etching process at this time is generally an isotropic etching process such as a CDE method or a wet method, and the process is determined by a hard mask material or the like. For example, when a SiN film is selected as the hard mask 7, wet etching with hot phosphoric acid is considered. After removing the hard mask 7 in the WL portion, the resist pattern 9 is peeled off. As a resist 9 peeling process, an ashing process (O ₂ asher) in an oxygen atmosphere is generally used. Through the steps so far, the sidewall pattern 11 is formed in the WL portion at a pitch of about twice the final transistor pattern pitch. Further, a stack of hard mask 7 / BSG film 6 + sidewall spacer 11 is formed in the SG portion and the peripheral circuit portion.

Next, as shown in FIG. 35, the gate structure of the NAND flash memory as a base (tunnel oxide film 2 / first polysilicon film 3 / high dielectric film (Al ₂ O ₃ ) 4 / second polysilicon film 5) The WL portion is processed using the sidewall pattern 11 as a mask, and the SG portion and the peripheral circuit portion are processed using the sidewall pattern 11, the hard mask pattern 7, and the BSG film 6 as a mask. Finally, as shown in FIG. 36, the sidewall spacer 11, the hard mask pattern 7, and the BSG film 6 that become the mask are removed by etching.

  As described above, according to the third embodiment, similarly to the second embodiment, a pattern without misalignment between the SG portion and the WL portion and the peripheral circuit portion and the WL portion is completed.

(Fourth embodiment)
FIG. 37 shows an integrated circuit pattern forming method according to the fourth embodiment of the present invention. Since the pattern formed by the sidewall leaving process is a closed loop pattern, the line termination pattern must be cut to obtain an integrated circuit pattern.

  There are two types of cutting methods. One is a method of exposing both the WL end portion of the sidewall and the other end portions (SG portion and peripheral circuit portion) by forming a resist pattern 12 by a lithography process as shown in FIG. . The timing for introducing this lithography process is desirably after the BSG film mask 6 'in the WL portion is removed in the process flow described in the first and second embodiments. The exposed portion of the sidewall pattern 11 is removed by etching.

  As shown in FIG. 38, the other one is the formation of a resist pattern 13 by a lithography process, where only the WL side wall terminal end is exposed, and the other (SG part, peripheral circuit part) line end parts are resist patterns. It is a method of covering with. Since the hard mask 7 other than the WL portion remains and no closed loop pattern is formed, the line termination portion other than the WL portion may be covered with the resist pattern 13. After such termination processing is performed, the wiring pattern 14 is filled with the interlayer insulating film 15, and then the termination pattern is formed through a process of connecting the contact 16 to the wiring pattern 14 (FIG. 39).

  In FIG. 40, the NAND string lengths of the double exposure method (Type A) and the method of the first embodiment (Type B) and the second or third embodiment (Type C) are compared. The horizontal axis represents the generation expressed in half pitch (HP).

  As miniaturization accelerates, the difference in NAND string length between Type A, Type B, and Type C increases. The reason is considered as follows. The gate pattern of the NAND flash memory has a feature that the dimensional miniaturization accelerates, but the vertical (height) miniaturization does not advance, and the aspect ratio becomes higher with the miniaturization. For this reason, the asymmetry of the device characteristics due to ion implantation increases, but shrinking of the distance between WL1 and SG to eliminate this influence is not performed even if the generation progresses.

  From FIG. 40, it can be seen that in the 12 nm generation, the string length of about 25% becomes shorter in the method (Type B, Type C) of this embodiment than in the double exposure method (Type A). This difference is the difference in memory cell area as it is, and if it is multiplied by the memory cell occupation ratio (usually 60 to 80%), it becomes a difference in chip size. By using this technique, it is possible to realize a semiconductor integrated device with a small chip size, desired device characteristics, and a low cost process.

  Although the present invention has been described above through the embodiments, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

1 is an equivalent circuit diagram of a general NAND flash memory. FIG. 3 is a schematic cross-sectional view of a NAND flash memory for explaining misalignment in a double exposure process. FIG. 3 is a schematic cross-sectional view of a NAND flash memory for explaining characteristic variation caused by the misalignment. Sectional drawing for demonstrating the NAND type flash memory manufacturing process concerning 1st Embodiment. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a cross-sectional view of the process following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 6A is a cross-sectional view for explaining a manufacturing process of the NAND flash memory according to the second embodiment and is a cross-sectional view of the process following FIG. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. FIG. 21 is a cross-sectional view of the process following FIG. 20. FIG. 22 is a sectional view of a step following FIG. 21. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23. FIG. 25 is a sectional view of a step following FIG. 24. FIG. 26 is a sectional view of a step following FIG. 25. FIG. 27 is a sectional view of a step following FIG. 26; The top view for demonstrating the relationship between the mask pattern in the embodiment of this invention, and the gate pattern at the time of completion. FIG. 6A is a cross-sectional view illustrating a manufacturing process of the NAND flash memory according to the third embodiment and is a cross-sectional view illustrating a process following FIG. FIG. 30 is a sectional view of a step following FIG. 29; FIG. 31 is a sectional view of a step following FIG. 30. FIG. 32 is a cross-sectional view of the process following FIG. 31. FIG. 33 is a sectional view of a step following FIG. 32. FIG. 34 is a sectional view of a step following FIG. 33. FIG. 35 is a sectional view of a step following FIG. 34. FIG. 36 is a cross-sectional view of the process following FIG. FIG. 10 is a plan view for explaining a manufacturing process of the NAND flash memory according to the fourth embodiment. FIG. 14 is a plan view for explaining another manufacturing process of the NAND flash memory according to the fourth embodiment. The top view of the process following FIG. The figure for demonstrating the effect of this invention.

Explanation of symbols

ST ... selection transistor MC ... memory cell SG ... selection gate WL ... word line 1 ... silicon substrate (substrate to be processed)
2 ... Gate insulating film (tunnel oxide film) (part of the first film)
3 ... polysilicon film (floating gate) (part of the first film)
4 ... Inter-gate insulating film (part of the first film)
5 ... Polysilicon film (control gate) (part of the first film)
6 ... Silicon oxide film (BSG film) (second film)
7. Hard mask (third film)
8, 8, 10, 12, 13... Resist film (mask pattern)
11: Side wall insulating film (fourth film)
14 ... Electrode 15 ... Interlayer insulating film

Claims (5)

Forming a resist pattern by a lithography process on a laminated film formed on the processing substrate;
Processing the first film of the uppermost layer of the laminated film using the resist pattern as a mask to form a pattern made of the first film;
Partially exposing the pattern of the first film by forming a resist pattern by a lithography process;
Selectively thinning the exposed pattern of the first film by an etching process;
Processing the second film below the first film using the first film as a mask to form a laminated pattern composed of the first and second films;
Partially exposing the laminated pattern of the first and second films by forming a resist pattern by a lithography process;
Removing the exposed first film by etching and exposing the second film;
Forming a side wall pattern composed of a third film on the side wall portion of the laminated pattern of the first and second films and the pattern of the second film;
Removing the exposed portion of the second film after forming the sidewall pattern;
After removing the exposed portion of the second film, the fourth film under the first, second, and third films is formed using the pattern of the first, second, and third films as a mask. Processing the membrane;
Removing the first, second and third films;
An integrated circuit pattern forming method comprising:   A step of partially exposing a pattern made of the first film by forming a resist pattern by a lithography process; and a step of partially exposing a laminated pattern of the first and second films by forming a resist pattern by a lithography process; 2. The integrated circuit pattern forming method according to claim 1, wherein the exposure mask used in the step is the same exposure mask. Forming a resist pattern by a lithography process on a laminated film formed on the processing substrate;
Processing the first film of the uppermost layer of the laminated film using the resist pattern as a mask, and forming a pattern comprising the first film;
Narrowing the pattern of the exposed first film by an etching process;
Processing the second film below the first film using the first film as a mask to form a laminated pattern of the first and second films;
Partially exposing the laminated pattern of the first and second films by forming a resist pattern by a lithography process;
Removing the exposed first film by etching and exposing the second film;
Forming a side wall pattern composed of a third film on the side wall portion of the laminated pattern of the first and second films and the pattern of the second film;
Removing the exposed portion of the second film after forming the sidewall pattern;
After removing the exposed portion of the second film, the fourth film under the first, second, and third films is formed using the pattern of the first, second, and third films as a mask. Processing the membrane;
Removing the first, second and third films;
An integrated circuit pattern forming method comprising: Forming a resist pattern by a lithography process on a laminated film formed on a processing substrate;
Thinning the resist pattern by an etching process;
Processing the first film of the uppermost layer of the laminated film using the thinned resist pattern as a mask, and forming a pattern comprising the first film;
Processing the second film below the first film using the first film as a mask to form a laminated pattern composed of the first and second films;
Forming a sidewall pattern made of a third film on a sidewall portion of the laminated pattern of the first and second films;
A step of partially exposing a pattern formed of the first, second, and third films by forming a resist pattern by a lithography process after the sidewall pattern is formed;
Removing the exposed first and second films by etching after forming the resist pattern;
Processing the fourth film below the first, second, and third films using the patterns of the first, second, and third films as a mask;
Removing the first, second and third films;
An integrated circuit pattern forming method comprising: After the sidewall pattern formation, a step of partially exposing the end portion of the sidewall pattern by resist pattern formation by a lithography process;
Removing the exposed sidewall pattern;
5. The integrated circuit pattern forming method according to claim 1, comprising:

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