JP2013021013A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can form a fine line pattern below the lithography resolution limit by improving a selection flexibility of the number of lines according to an embodiment.SOLUTION: According to an embodiment, a semiconductor device manufacturing method comprises the steps of: forming a plurality of line patterns 23a; forming side wall films 26a on side walls of each line pattern 23a to form pattern rows 50 including a plurality of line patterns 23a and a plurality of side wall films 26a; forming spacer films 27a, 27b between neighboring side wall films 26a and in regions 60 beside the side wall films 26a at the ends of the pattern rows 50; and processing each spacer film 27b formed in each region 60 to a line-and-space pattern and removing the side wall films 26a to leave the spacer films 27a, 27b1, 27b2.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  With the progress of miniaturization of semiconductor devices, formation of fine wiring patterns below the resolution limit of lithography is required. As a method for realizing this, a so-called sidewall process is known in which a sidewall film is formed on a sidewall of a sacrificial film or a core material formed by lithography, and then the sacrifice film is removed to leave the sidewall film. According to this method, it becomes possible to form a line and space having a pitch that is 1/2 times the pitch that is limited by the resolution limit of lithography. There has also been proposed a method of forming a line and space having a pitch 1/4 times a pitch subject to the limitation of the resolution limit of lithography by repeating the side wall process.

JP 2009-152613 A

  According to the embodiment, there is provided a method for manufacturing a semiconductor device capable of forming a fine line pattern having a resolution below the resolution limit of lithography with an increased degree of freedom in selection.

  According to the embodiment, a method of manufacturing a semiconductor device includes a step of forming a plurality of line patterns, a sidewall film is formed on a sidewall of each of the line patterns, and the plurality of line patterns and the plurality of sidewall films are included. Forming a pattern row; forming a spacer film between the adjacent sidewall films; and a region next to the sidewall film at the end of the pattern row; and forming the pattern row in the region next to the sidewall film at the end. And processing the spacer film into a line and space pattern including a line pattern having a width different from that of the spacer film formed between the side wall films, and removing the side wall film.

1 is a schematic plan view of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A ′ in FIG. 1. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a schematic plan view showing the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic plan view showing another method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic plan view showing another method for manufacturing the semiconductor device of the embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing.

FIG. 1 is a schematic plan view showing a planar layout of main elements in the semiconductor device of the embodiment.
FIG. 2 is a schematic cross-sectional view corresponding to the cross section AA ′ in FIG. 1.

  In the present embodiment, as a semiconductor device, for example, a nonvolatile semiconductor memory device having a floating gate structure will be described as an example.

  FIG. 2 shows a cross section near the surface of the semiconductor substrate 8. An active region 10 is formed on the surface of the semiconductor substrate 8. The active region 10 has a first conductivity type channel region, and a second conductivity type source region and drain region.

  The active region 10 extends in the first direction X. Further, as shown in FIG. 1, a plurality of active regions 10 are formed side by side in a second direction Y that is orthogonal to the first direction X. The active regions 10 adjacent in the second direction Y are isolated from each other by an insulating film embedded in the semiconductor substrate 8.

  As shown in FIG. 2, a first insulating film 11 is provided on the active region 10. The first insulating film 11 extends in the first direction X and is divided into a plurality of parts in the second direction Y.

  A plurality of floating gates FG are provided on the first insulating film 11. The plurality of floating gates FG are divided in the first direction X. Further, the plurality of floating gates FG are also divided in the second direction Y.

  A second insulating film 13 is provided on the floating gate FG. The second insulating film 13 is divided into a plurality in the first direction X. The second insulating film 13 extends in the second direction Y and is not divided in the second direction Y.

  A control gate CG is provided on the second insulating film 13. The control gate CG is divided into a plurality in the first direction X. The control gate CG extends in the second direction Y and is not divided in the second direction Y.

  An insulating layer 17 is provided between the floating gates FG adjacent in the first direction X. The floating gates FG adjacent in the second direction Y are insulated and separated by an insulating film (not shown) embedded in the semiconductor substrate 8.

  The floating gate FG is located at the intersection of the control gate CG and the active region 10 in plan view. That is, a plurality of memory cells MC are laid out in a matrix on the semiconductor substrate 8. One memory cell MC includes one floating gate FG that is insulated around the memory cell MC.

  That is, the floating gate FG is not electrically connected anywhere. Therefore, even if the power is turned off, the electrons accumulated in the floating gate FG do not leak from the floating gate FG and do not enter again. That is, the semiconductor device of this embodiment is a nonvolatile semiconductor memory device that can hold data without supplying power.

  The plurality of memory cells MC are connected in series in the first direction X to form a cell column. Further, selection transistors are connected to both ends of the cell column in the first direction X. The cell column and the select transistor are connected in series between the source line SL and the bit line BL shown in FIG. 2, and constitute a memory string. A source region and a drain region (not shown) are formed on the surface of the semiconductor substrate 8 between the adjacent memory cells MC and between the select transistors adjacent to the memory cells MC at both ends.

  The source line SL is connected to the active region 10 via the source line contact CSL and the contact region 19a. The contact region 19a is formed on the surface of the active region 10 in a portion extending in the first direction X from one end of the cell row. The source line contact CSL is provided on the contact region 19a and is electrically connected to the contact region 19a.

  A source side select transistor is provided between the cell column and the contact region 19a. The source side select transistor has a source side select gate SGS. The source side select gate SGS is provided on the active region 10 via the first insulating film 11 outside the cell row in the first direction X.

  The source side select gate SGS is separated from the floating gate FG and the control gate CG at the extreme end of the cell column, and an insulating layer 17 is provided between the cell column and the source side select gate SGS. The distance between the memory cell MC at the end of the cell column and the source side select gate SGS is larger than the distance between the memory cells MC.

  A pair of source side select gates SGS is provided across the contact region 19a in the first direction X, and each of the source side select gates SGS can connect a different cell column to the source line SL. That is, the source line SL is shared among a plurality of memory strings.

  The bit line BL is connected to the active region 10 via the bit line contact CBL and the contact region 19b. The contact region 19b is formed on the surface of the active region 10 in a portion extending in the first direction X from the other end of the cell row. The bit line contact CBL is provided on the contact region 19b and is electrically connected to the contact region 19b.

  A drain side select transistor is provided between the cell row and the contact region 19b. The drain side select transistor has a drain side select gate SGD. The drain side select gate SGD is provided on the active region 10 via the first insulating film 11 outside the cell row in the first direction X.

  The drain side select gate SGD is separated from the farthest floating gate FG and control gate CG of the cell column, and an insulating layer 17 is provided between the cell column and the drain side select gate SGD. The distance between the memory cell MC at the extreme end of the cell column and the drain side select gate SGD is larger than the distance between the memory cells MC.

  A pair of drain side select gates SGD is provided across the contact region 19b in the first direction X, and each drain side select gate SGD can connect a different cell column to the bit line BL. That is, the bit line BL is shared among a plurality of memory strings.

  As shown in FIG. 1, the source side select gate SGS, the drain side select gate SGD, and the source line contact CSL extend in the second direction Y. The source lines SL (not shown in FIG. 1) are laid out across a plurality of active regions 10 arranged in the second direction Y, and the plurality of active regions 10 can be connected to a common source line SL. The bit line BL extends in the first direction X as shown in FIG. A plurality of bit lines BL are provided corresponding to the number of the plurality of active regions 10 arranged in the second direction Y.

  As shown in FIG. 2, an interlayer insulating film 15 is provided on the control gate CG, the source-side selection gate SGS, and the drain-side selection gate SGD, and the bit line BL is provided on the interlayer insulating film 15. Yes. The source line SL is covered with the interlayer insulating film 15 and insulated from the bit line BL and the source side select gate SGS.

  Next, a method for manufacturing the semiconductor device of the embodiment will be described.

  FIG. 3A to FIG. 9B are schematic plan views showing a method for manufacturing a semiconductor device of the embodiment. FIG. 10A to FIG. 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device of the embodiment.

  The line and space patterns shown in FIGS. 9B and 13C are formed by the process shown in FIGS. 3A to 13C. The cross section in FIG. 13C corresponds to the B-B ′ cross section in FIG.

  Line patterns 22a to 22c shown in FIGS. 9B and 13C correspond to, for example, a gate structure (stacked gate structure) including the floating gate FG, the second insulating film 13, and the control gate CG in FIG. To do. Alternatively, the gate structure is processed using the line patterns 22a to 22c as a mask.

  Also, the line pattern 22d shown in FIGS. 9B and 13C corresponds to, for example, the drain side selection gate SGD or the source side selection gate SGS in FIG. Alternatively, the drain side selection gate SGD or the source side selection gate SGS is processed using the line pattern 22d as a mask.

  FIG. 10A shows a cross section of a laminated body to which the process of this embodiment is applied, and FIG. 3A shows an upper surface of the laminated body. The stacked body includes a substrate 21, a processed film 22 formed on the substrate 21, a hard mask 23 formed on the processed film 22, and a resist 24 formed on the hard mask 23. The film to be processed 22 has a single layer structure or a multi-layer structure.

  The resist 24 is selectively exposed using a mask (reticle) (not shown). The resist 24 is sensitive to the exposure light, and the exposed or unexposed part of the resist 24 is soluble in the developer.

  By developing the resist 24 after the exposure, a plurality of sacrificial films 24a that are line patterns are formed on the hard mask 23, as shown in FIGS. 10B and 3B.

  The sacrificial film 24a is not limited to a resist pattern formed by lithography, but may be a hard mask pattern such as a silicon oxide film further processed using the resist pattern as a mask.

  Next, isotropic etching is performed on the sacrificial film 24a, and as shown in FIGS. 10C and 4A, the width of the sacrificial film 24a is reduced (slimmed). The width of the sacrificial film 24a is reduced to about ½ compared with that before slimming shown in FIGS. 10B and 3B, and the interval between the sacrificial films 24a is expanded about 3/2 times.

  Next, as shown in FIG. 10D, a first sidewall film 25 is formed on the hard mask 23. The first sidewall film 25 covers the sidewall and upper surface of the sacrificial film 24a. The first sidewall film 25 is conformally formed along the sidewall and the upper surface of the sacrificial film 24a. The thickness of the portion of the first sidewall film 25 that covers the sidewall of the sacrificial film 24a is controlled to be the same as or close to the width of the sacrificial film 24a.

  The first sidewall film 25 is made of a material different from that of the sacrificial film 24a. For example, the first sidewall film 25 is a silicon nitride film with respect to the sacrificial film 24a which is a resist or a silicon oxide film.

  Next, anisotropic etching (for example, RIE (Reactive Ion Etching)) is performed on the first sidewall film 25. Thereby, the first sidewall film 25 on the upper surface of the sacrificial film 24a is removed, and the first sidewall film 25a is left on the sidewall of the sacrificial film 24a as shown in FIG. The upper surface of the sacrificial film 24a is exposed.

  In addition, a space having the same width as or close to the width of the sacrificial film 24a is formed between the adjacent first sidewall films 25a. The upper surface of the hard mask 23 is exposed in the space. That is, as shown in FIG. 4B, the first sidewall film 25a as a line pattern is formed on the sidewalls on both sides in the width direction of each of the plurality of sacrificial films 24a.

  Next, as shown in FIGS. 11B and 5A, the sacrificial film 24a is removed by anisotropic etching or isotropic etching. This etching is performed under conditions where the sacrificial film 24a is selectively etched with respect to the first sidewall film 25a. Therefore, a plurality of first sidewall films 25a that are line patterns are left on the hard mask 23. The width of the first sidewall film 25a is substantially the same as the width of the space between the first sidewall films 25a.

  Next, the hard mask 23 is processed by anisotropic etching using the first sidewall film 25a as a mask. Thereafter, the first sidewall film 25a is removed. As shown in FIGS. 11C and 5B, the hard mask 23 is processed into a plurality of line patterns 23a. The line pattern 23a is a portion left under the first side wall film 25a in the hard mask 23, and is arranged with substantially the same width and pitch as the first side wall film 25a.

  The hard mask 23, that is, the line pattern 23a is made of a material different from that of the first sidewall film 25a. For example, with respect to the first sidewall film 25a which is a silicon nitride film, the hard mask 23 and the line pattern 23a are TEOS (tetraethoxysilane) films mainly containing silicon oxide.

  Next, isotropic etching is performed on the line pattern 23a, and the width of the line pattern 23a is reduced (slimmed) as shown in FIGS. 11 (d) and 6 (a). The width of the line pattern 23a is reduced to about ½ compared with that before slimming shown in FIGS. 11C and 5B, and the interval between the line patterns 23a is increased about 3/2 times.

  Further, the width of the line pattern 23a after slimming is about 1/4 of the width of the sacrificial film 24a shown in FIGS. 10B and 3B formed by lithography, and the number of the line patterns 23a is sacrificed. This is twice the number of films 24a.

  Next, as shown in FIG. 12A, a second sidewall film 26 is formed on the film 22 to be processed. The second sidewall film 26 covers the sidewall and the upper surface of the line pattern 23a. The second sidewall film 26 is formed conformally along the sidewall and upper surface of the line pattern 23a. The film thickness of the portion covering the side wall of the line pattern 23a in the second side wall film 26 is controlled to be the same as or close to the width of the line pattern 23a.

  The second sidewall film 26 is made of a material different from that of the line pattern 23a. For example, the second sidewall film 26 is a silicon nitride film with respect to the line pattern 23a which is a TEOS film.

  Next, anisotropic etching (for example, RIE) is performed on the second sidewall film 26. Thereby, the second sidewall film 26 on the upper surface of the line pattern 23a is removed, and the second sidewall film 26a is left on the sidewall of the line pattern 23a as shown in FIG. The upper surface of the line pattern 23a is exposed.

  In addition, a space having the same width as or close to the width of the line pattern 23a is formed between the adjacent second sidewall films 26a. The upper surface of the film 22 to be processed is exposed in the space. That is, as shown in FIG. 6B, the second sidewall film 26a, which is a line pattern, is formed on the sidewalls on both sides in the width direction of each of the plurality of line patterns 23a. A pattern row 50 including the second sidewall film 26a is formed.

  Next, as shown in FIGS. 12C and 7A, a spacer film 27 a is formed between the adjacent second sidewall films 26 a in the pattern row 50. The spacer film 27a is embedded in the space between the adjacent second sidewall films 26a. Further, the spacer film 27 b is also formed in the region 60 next to the second sidewall film 26 a at the end of the pattern row 50.

  The spacer films 27a and 27b are made of the same material and are formed simultaneously. The spacer films 27a and 27b are made of a material different from that of the second sidewall film 26a. For example, the spacer films 27a and 27b are silicon oxide films with respect to the second sidewall film 26a which is a silicon nitride film. For example, TEOS films formed by a chemical vapor deposition (CVD) method can be used as the spacer films 27a and 27b.

  Alternatively, silicon oxide films (SiO) may be formed as the spacer films 27a and 27b by a coating method. In this case, the embedding property in the space between the second sidewall films 26a is excellent.

  Next, as shown in FIG. 7B, a mask 40 is selectively formed on the pattern film 50 and on the spacer film 27b formed in the region 60 on the side thereof. In FIG. 7B, the mask 40 is represented by a thick line.

  The mask 40 is made of a material different from that of the spacer film 27b. For example, the mask 40 is an organic film (resist film) with respect to the spacer film 27b which is a silicon oxide film. The mask 40 is patterned by lithography.

  The mask 40 covers the entire pattern row 50. The spacer film 27 a buried between the adjacent second sidewall films 26 a in the pattern row 50 is also covered with the mask 40. The mask 40 covers a part of the spacer film 27 b formed in the lateral region 60 of the pattern row 50. Another part of the spacer film 27 b formed in the region 60 is exposed without being covered with the mask 40.

  If the space between the second sidewall films 26a in the pattern row 50 is narrow or the aspect ratio is high, a step is formed due to poor filling of the mask 40 into the space, and there is a concern that lithography for patterning the mask 40 may be difficult. is there. However, in the present embodiment, the spacer film 27a is embedded between the second sidewall films 26a in the pattern row 50, and the upper surface of the pattern row 50 is substantially flat. Therefore, the mask 40 can be patterned with high accuracy.

  Then, using the mask 40, the spacer film 27b is selectively etched by, eg, RIE. Thereby, as shown in FIGS. 13A and 8A, the spacer film 27b exposed from the mask 40 in the lateral region 60 of the pattern row 50 is selectively removed. In FIG. 13A, the mask 40 is represented by a two-dot chain line.

  Here, in the line pattern 23a and the second sidewall film 26a, loop-shaped portions (not shown) formed on both sides in the longitudinal direction are exposed from the mask 40, and these loop-shaped portions are etched by using the mask 40. May be cut.

  Thereafter, the mask 40 is removed (FIG. 8B). By the etching using the mask 40, the spacer film 27b formed in the lateral region 60 of the pattern row 50 is processed into a line and space pattern including the first line pattern 27b1 and the second line pattern 27b2. The

  The first line pattern 27b1 is formed on the side wall of the second side wall film 26a at the end of the pattern row 50. The second line pattern 27b2 is separated from the first line pattern 27b1 with a space. The second line pattern 27b2 has a width larger than the width of the first line pattern 27b1, the width of the line pattern 23a, the width of the second sidewall film 26a, and the width of the spacer film 27a between the second sidewall films 26a. Have

  Next, as shown in FIGS. 13B and 9A, the second sidewall film 26a is removed by anisotropic etching or isotropic etching. In this etching, the second sidewall film 26a is selectively etched with respect to the line pattern 23a, the spacer film 27a, and the first line pattern 27b1 and the second line pattern 27b2, which are the same material as the spacer film 27a. Done on condition. The line pattern 23a, the spacer film 27a, the first line pattern 27b1, and the second line pattern 27b2 are made of a silicon oxide material, and the second sidewall film 26a is made of a silicon nitride material. Accordingly, conditions for etching the silicon nitride material with selectivity to the silicon oxide material are set.

  By selectively removing the second sidewall film 26a, the line pattern 23a, the spacer film 27a, the first line pattern 27b1, and the second line pattern 27b2 are left on the film 22 to be processed. These are formed as line patterns parallel to each other.

  Then, the film to be processed 22 is processed by anisotropic etching using the line pattern 23a, the spacer film 27a, the first line pattern 27b1, and the second line pattern 27b2 as a mask. As shown in FIGS. 13C and 9B, the film to be processed 22 is processed into a line and space pattern including line patterns 22a to 22d.

  The line pattern 22a is a part left under the spacer film 27a, the line pattern 22b is a part left under the line pattern 23a, and the line pattern 22c is under the first line pattern 27b1 of the spacer film 27b. The line pattern 22d is a portion left under the second line pattern 27b2 of the spacer film 27b.

  The line patterns 22a and 22b are arranged with substantially the same width and pitch. The space between the line pattern 22a and the line pattern 22b and the space between the line pattern 22c and the line pattern 22b are both spaces formed by removing the second sidewall film 26a. Therefore, the width of the space between the line pattern 22a and the line pattern 22b is substantially the same as the width of the space between the line pattern 22c and the line pattern 22b.

  The line pattern 22b has the same pitch as the first sidewall film 25a formed by the first sidewall process. That is, the line pattern 22b has a pitch that is ½ times the pitch that is limited by the resolution limit of lithography.

  The line pattern 22a is formed at an intermediate position in the width direction between adjacent line patterns 22b. Therefore, the line pattern 22b and the line pattern 22a are arranged at a pitch that is 1/4 times the pitch that is limited by the resolution limit of lithography.

  On the other hand, the width of the line pattern 22c and the width of the line pattern 22d can be arbitrarily adjusted by the design of the mask 40 shown in FIG. 7B, and do not depend on the sidewall process.

  The line pattern 22d is, for example, a pattern corresponding to the drain side selection gate SGD or the source side selection gate SGS (hereinafter collectively referred to as a selection gate) shown in FIG. 2, and corresponds to the gate structure of the memory cell MC. The line patterns 22a and 22b are formed with a width larger than the width of the line patterns 22a and 22b.

  The line pattern 22c is formed at the end in the cell row. In general, a cell formed at the end of a cell column may not be used as a memory cell MC in consideration of an electrical influence from a selection gate, particularly a drain side selection gate SGD. Therefore, the line pattern 22c corresponds to the pattern of the gate structure of the dummy cell that is not used as the memory cell MC, and the width may or may not be the same as the width of the gate structure of the memory cell MC. As described above, the width of the line pattern 22c formed through the patterning of the spacer film 27b using the mask 40 can be arbitrarily set without depending on the width of the line patterns 22a and 22b formed through the sidewall process. .

  Further, the space between the line pattern 22c and the line pattern 22d does not include the space formed by the sidewall process. That is, using the mask 40, the first line pattern 27b1 corresponding to the dummy cell at the end of the cell row, the second line pattern 27b2 corresponding to the selection gate, and the space between them are formed. Therefore, the variation in the space dimension caused by the repetition of the sidewall process is not included in the space dimension between the gate structure of the dummy cell and the selection gate.

  Here, a case is considered in which a sidewall structure is used to add a dummy cell gate structure to the end of a cell row including 64 gate structures used as memory cells MC, for example.

  When the side wall process is performed only once, 33 line patterns are formed as sacrificial films by lithography, side wall films are formed on both side walls in the width direction of the respective sacrificial films, and the sacrificial films are removed. 66 sidewall films can be obtained as a line pattern. In this case, there are 66 gate structures used as the memory cells MC at a pitch that is 1/2 times the pitch that is limited by the resolution limit of lithography, and 66 gate structures corresponding to the gate structures of two dummy cells formed at both ends thereof. A line pattern of books can be obtained.

  Next, consider a case where the side wall process is repeated twice to obtain a line pattern arranged at a pitch that is 1/4 times the pitch that is limited by the resolution limit of lithography.

  First, 16 line patterns are formed as sacrificial films by lithography, side wall films are formed on both side walls in the width direction of the respective sacrificial films, and the sacrificial films are removed to obtain 32 side wall films as line patterns. be able to. Further, the 32 side wall films or 32 line patterns processed using the side wall films as masks are used as second sacrificial films, and the second side walls are formed on the side walls on both sides in the width direction of the respective second sacrificial films. When the film is formed and the second sacrificial film is removed, 64 second sidewall films can be obtained as a line pattern. However, when 64 gate structures used as the memory cells MC are formed, a line pattern corresponding to the dummy cell gate structure cannot be obtained.

  On the other hand, first, 17 line patterns are formed as sacrificial films by lithography, side wall films are formed on both side walls in the width direction of the respective sacrificial films, and when the sacrificial films are removed, 34 side wall films are formed into line patterns. Can be obtained as Further, the 34 sidewall films or 34 patterns processed using the sidewall films as masks are used as second sacrificial films, and the second sidewall films are formed on the sidewalls on both sides in the width direction of the respective second sacrificial films. When the second sacrificial film is removed, 68 second sidewall films can be obtained as a line pattern. However, when it is desired to obtain 64 gate structures used as the memory cells MC, the number of line patterns corresponding to the gate structures of the dummy cells becomes redundant.

In contrast, in the present embodiment, the spacer film 27b is formed in the lateral region 60 of the pattern row 50 obtained by performing the sidewall process of forming the sidewall film on the sidewall of the sacrificial film (or the core material) twice, The spacer film 27 b is processed into a line and space pattern using the mask 40. Therefore, an arbitrary number of line patterns can be added to the pattern row 50 formed by the sidewall process without being limited by the number of sidewall processes. Typically, when the sidewall process is repeated ⁿ times, a gate structure and a line pattern corresponding to the gate structure used as the memory cells MC arranged at a pitch that is 1/2 ⁿ times the pitch that is limited by the resolution limit of lithography, At least one line pattern corresponding to the gate structure of the dummy cell formed using the spacer film 27b at the end can be obtained. That is, according to the present embodiment, it is possible to form a fine line pattern below the resolution limit of lithography with an increased degree of freedom in selecting the number.

  Note that the step of processing the spacer film 27b formed in the lateral region 60 of the pattern row 50 into a line-and-space pattern may be performed after removing the second sidewall film 26a.

  That is, after the spacer films 27a and 27b shown in FIG. 7A are formed, the second sidewall film 26a is removed as shown in FIG. 14A.

  Thereafter, as shown in FIG. 14B, a mask 40 is formed, and the spacer film 27b is selectively removed by etching using the mask 40 as shown in FIG. In addition, loop portions (not shown) formed on both sides in the longitudinal direction of the line pattern 23 a can also be cut by etching using the mask 40.

  Then, by removing the mask 40, a line pattern 23a, a spacer film 27a, a first line pattern 27b1, and a second line pattern 27b2 are obtained as shown in FIG. 15B.

  The number of sidewall processes is not limited to the embodiment described above. The line pattern 23a shown in FIG. 6A is obtained by one side wall process, and is arranged at a pitch 1/2 times that of the sacrificial film 24a shown in FIG. 3B formed by lithography. May be a line pattern obtained by two sidewall processes and arranged at a pitch that is 1/4 times the line pattern formed by lithography. Alternatively, the line pattern 23a may be a line pattern obtained by three or more sidewall processes.

  Further, the processes after FIG. 6B may be performed not on the line pattern 23a but on the sacrificial film 24a shown in FIG. 4A formed by lithography and slimming.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 21 ... Substrate, 22 ... Processed film, 23 ... Hard mask, 23a ... Line pattern, 24 ... Resist, 24a ... Sacrificial film, 25, 25a ... First side wall film, 26, 26a ... Second side wall film, 27a 27b ... Spacer film, 27b1 ... First line pattern of spacer film, 27b2 ... Second line pattern of spacer film, 40 ... Mask, 50 ... Pattern row

Claims (5)

After the first sidewall film is formed on the sidewall of the sacrificial film, the sacrificial film is removed, and etching is performed using the remaining first sidewall film as a mask so as to be provided under the first sidewall film. Patterning the film, forming a plurality of line patterns by reducing the pattern width of the patterned film; and
Forming a second sidewall film on a sidewall of each line pattern, and forming a pattern row including the plurality of line patterns and the plurality of second sidewall films;
Forming a spacer film between the adjacent second side wall films and in a region next to the second side wall film at the end of the pattern row;
The spacer film formed in the region beside the second sidewall film at the end is changed into a first line pattern formed on the sidewall of the second sidewall film at the end, and the first line pattern. Forming a line-and-space pattern having a second line pattern having a width greater than the width of the plurality of line patterns, and removing the second sidewall film;
A method for manufacturing a semiconductor device, comprising: Forming a plurality of line patterns;
Forming a sidewall film on a sidewall of each of the line patterns, and forming a pattern row including the plurality of line patterns and the plurality of sidewall films;
Forming a spacer film in a region between the side wall films adjacent to each other and a side wall film at an end of the pattern row;
The spacer film formed in the region beside the sidewall film at the end is processed into a line and space pattern including a line pattern having a width different from that of the spacer film formed between the sidewalls, and the sidewall film Removing the
A method for manufacturing a semiconductor device, comprising: The step of forming the line pattern includes:
Forming a first sidewall film on the sidewall of the sacrificial film;
Removing the sacrificial film and leaving the first sidewall film;
The method of manufacturing a semiconductor device according to claim 2, further comprising: The step of forming the line pattern includes:
Patterning a film provided under the first sidewall film by etching using the first sidewall film left after removing the sacrificial film as a mask;
Reducing the pattern width of the patterned film,
The method of manufacturing a semiconductor device according to claim 3, further comprising:   The sidewall film is removed after processing the spacer film formed in the region beside the sidewall film at the end into the line-and-space pattern. The manufacturing method of the semiconductor device of description.

Images