CN208142177U - Active array and random access memory - Google Patents

Abstract

The utility model provides a kind of active array and random access memory, and active array includes the spacing unit that semiconductor substrate and active area unit and external series gap are constituted, wherein the minimum dimension of photoresist exposure development is the odd-multiple of spacing unit；Random access memory includes active array, device cell and shallow groove isolation structure, and device cell is formed on active area unit, fills external series gap to form shallow groove isolation structure.The active array of the utility model is by improving photolithography limitation precision, to obtain smaller size of spacing unit, to meet specific small spacing unit demand in random access memory.

Description

Active array and random access memory

Technical field

The utility model relates to semiconductor integrated circuit field more particularly to a kind of active array and random access memory.

Background technique

In random access memory, active array (Active array) universal at present is as shown in Figure 1, individual devices unit 1 (Cell is formed in active array by active area unit line) and its adjacent (STI, active of shallow groove isolation structure 2 Formed in array by external series gap space) between spacing be known as a spacing unit 3 (Pitch).

Pitch doubling technique is used in the prior art, it is two Pitch that an original Pitch, which is divided to, thus The size of Pitch is reduced, but since the exposure active area unit tolerance makes, the spacing unit size being lithographically derived in prior art With active area unit is wide is not able to satisfy certain smaller spacing unit size demands.

Utility model content

The utility model provides a kind of active array and random access memory, with solve it is above it is in the prior art at least one Technical problem.

In order to achieve the above objectives, a kind of active array of the utility model, including：

Semiconductor substrate；And

The active area unit being formed on the semiconductor substrate and the isolation between the adjacent active area unit The spacer units that gap is constituted；

Wherein, the minimum feature size of the exposure development size of photoresist is the odd number of the characteristic size of the spacing unit Times.

In a kind of embodiment, the characteristic size of the spacing unit includes 30nm

In order to achieve the above objectives, the utility model provides a kind of random access memory, including

Such as above-mentioned active array as described in the examples；

Multiple device cells are formed on the active area unit；And

Shallow groove isolation structure is formed in the semiconductor substrate by the way that isolated material is filled in the external series gap.

The utility model improves photolithography limitation precision in active array, to obtain smaller size of spacing unit, so as to have Source array and random access memory obtain smaller size of spacing unit, to meet specific small spacing unit demand.

Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one Aspect, embodiment and the feature of step, which will be, to be readily apparent that.

Detailed description of the invention

In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.

Fig. 1 is the structure chart of active array in the prior art.

Fig. 2 is the flow chart of active array manufacture in the utility model embodiment.

Fig. 3 is the structure chart that active array step S10 is manufactured in the utility model embodiment.

Fig. 4 is the structure chart that active array step S20 is manufactured in the utility model embodiment.

Fig. 5 is the structure chart that active array step S30 is manufactured in the utility model embodiment.

Fig. 6 is the structure chart that active array step S40 is manufactured in the utility model embodiment.

Fig. 7 is the structure chart that active array step S50 is manufactured in the utility model embodiment.

Fig. 8 is the structure chart that active array step S60 is manufactured in the utility model embodiment.

Fig. 9 is the structure chart that active array step S70 is manufactured in the utility model embodiment.

Figure 10 is the structure chart of active array in semiconductor devices in the utility model embodiment.

Appended drawing reference in Fig. 1：

1：Device cell, 2：Shallow groove isolation structure, 3：Spacing unit.

Fig. 3 appended drawing reference into Figure 10：

110 semiconductor substrates,

120 photoresists,

121 first sides,

122 second sides,

130 first barrier layers,

131 exposure mask portions,

132 protection portion,

140 sacrificial layers,

141 grooves,

150 second barrier layers,

151 occlusion parts,

160 spacing units,

160A external series gap,

160B active area unit.

Specific embodiment

Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.

Embodiment one

A kind of manufacturing method of active array of the present embodiment, referring to shown in Fig. 2, including：

Step S10：Referring to shown in Fig. 3, semi-conductive substrate 110 is provided, forms interval setting on semiconductor substrate 110 Photoresist 120.

Step S20：Referring to shown in Fig. 4, the first barrier layer 130 is formed in the semiconductor substrate 110 and the photoresist On 120.

Step S30：Referring to Figure 5, sacrificial layer 140 is formed on first barrier layer 130, wherein two neighboring The sacrificial layer 140 between the photoresist 120 forms groove 141.The material of first barrier layer 130 and sacrificial layer 140 is not Together, so as to not had an impact mutually when individually being etched.

Step S40：Referring to shown in Fig. 6, the second barrier layer 150 is formed on the sacrificial layer 140, to fill the groove 141.Second barrier layer 150 is different with the material of sacrificial layer 140, so as to not have an impact mutually when individually being etched.

Step S50：Referring to shown in Fig. 7, second barrier layer is removed downwards along 150 upper surface of the second barrier layer 150, to expose the upper surface of the sacrificial layer 140, wherein second barrier layer 150 in the groove 141, which is formed, blocks Portion 151.

Step S60：Referring to shown in Fig. 8, using the occlusion part 151 as exposure mask from the upper surface of the sacrificial layer 140 to It is lower to etch the sacrificial layer 140 and the first barrier layer 130, until appearing the upper surface of the photoresist 120.Described first stops Layer 130 has the exposure mask portion 131 for the side for being attached at the photoresist 120 and described leads positioned at the sacrificial layer 140 and partly Protection portion 132 between body substrate 110, the longitudinal thickness in the exposure mask portion 131 are greater than the longitudinal thickness of the protection portion 132. The upper surface that etching appears all photoresists 120 stops etching, removes photoetching all in semiconductor substrate 110 to facilitate Glue 120.

Step S70：Referring to shown in Fig. 9, the photoresist 120 is removed, and appear part downwards along the sacrificial layer 140 The sacrificial layer is etched, until appearing the protection portion 132 on first barrier layer 130, and continues the institute that etching appears The protection portion 132 on the first barrier layer 130 is stated, until appearing the semiconductor substrate 110, in the semiconductor substrate It is formed on 110 by the exposure mask portion 131 on first barrier layer 130 and the screening including second barrier layer 150 Multiple barrier structures that stopper 151 is constituted.The barrier structure further includes the sacrificial layer below the occlusion part 151 140 and first barrier layer 130, to form exposure mask stack layer.Wherein, 140 etching process of sacrificial layer due to thickness it is big And it is recessed to two sides, and depressed section does not influence the etched portions on first barrier layer 130.

Step S80：Referring to Fig.1 shown in 0, the spacing unit 160 for constructing active array is formed, including with the blocking Structure is as semiconductor substrate 110 described in mask etching, to form external series gap 160A；Remove the barrier structure formed it is active Area unit 160B；And an active area unit 160B and its adjacent one external series gap 160A are constituted between one Away from unit 160.The spacing of one active area unit 160B and its adjacent one external series gap 160A constitute one Cell spacing.

The present embodiment is in the case where that can not reduce 120 size of photoresist, by changing material on semiconductor substrate 110 Depositional mode and etching mode, form multiple active area unit 160B and external series gap 160A, improve photolithography limitation precision, with Smaller size of spacing unit 160 is constituted, so that active array obtains smaller size of spacing unit 160, to meet specific Small 160 demand of spacing unit.

In a kind of embodiment, the minimum dimension of the exposure development between the adjacent photoresist 120 is the spacing unit The odd-multiple of 160 sizes.

In a kind of embodiment, referring to shown in Fig. 3 and Figure 10, the photoresist 120 includes first side 121 and relative to institute The second side 122 of first side 121 is stated, and the distance between first side 121 of two neighboring photoresist 121 is that exposure is aobvious The minimum dimension of shadow, (minimum dimension of exposure development is A, and has been marked in Fig. 3 and Figure 10), wherein the semiconductor lining It include three spacing units 160, (spacing unit 160 on the corresponding position of the minimum dimension of bottom 110 and the exposure development Spacing be B, and marked in Figure 10) to reducing the size of each spacing unit 160, to obtain smaller spacing list First 160 sizes.The minimum dimension of the exposure development of usual photoresist is 80~90nm, the then size of the spacing unit 160 obtained In 30nm or so.A and B represents distance in Fig. 3 and Figure 10, and A is the spacing distance of exposure development, and B is unit interval.

In a kind of embodiment, the size of spacing unit 160 includes 30nm, and the spacing unit 160 of the present embodiment manufacture is most Small size can reach 30nm, to meet 160 size of spacing unit of 30nm demand.

In a kind of embodiment, the 1/2 of the thickness of the sacrificial layer 140 is more than or equal to the thickness on first barrier layer 130, Transverse gage and first barrier layer 130 of the sacrificial layer 140 at the first side are at the first side The sum of transverse gage is less than 1/2 of spacing between the adjacent photoresist 120, to form the groove 141.

In a kind of embodiment, the size and first barrier layer 130 and the sacrifice of the photoresist 120 are adjusted Layer 140 is in the first side of the photoresist 120 and the thickness of the second side, to adjust the active area unit The size of the width of 160B and the external series gap 160A.

Specifically, the size of photoresist 120 is directly proportional to external series gap 160A size, the thickness on the first barrier layer 130 with The active area unit width of active area unit 160B is directly proportional, and the thickness of sacrificial layer 140 is directly proportional to external series gap 160A size.

Change the size of photoresist 120 and the thickness of sedimentary in the present embodiment, to the spacing unit 160 eventually formed Size have an impact, specific size needs the requirement of more manufacture to be adjusted, and the present embodiment is only to spacing unit 160 Size makees qualitative analysis, without doing quantitative analysis.

In a kind of embodiment, first barrier layer 130 includes silicon nitride, and the sacrificial layer 140 includes silica, and Second barrier layer 150 includes silicon nitride.

In a kind of embodiment, etching includes dry etching, and removal includes chemical mechanical grinding, and the present embodiment passes through dry method quarter Erosion and chemical mechanical grinding can control the location and range of etching, and size conforms to during guaranteeing active array manufacture It asks.

Embodiment two

Based on embodiment 1, referring to Fig.1 shown in 0, a kind of active array of the present embodiment, including：

Semiconductor substrate；And

The multiple active area units being formed according to manufacturing method described in embodiment one on the semiconductor substrate The 160B and external series gap 160A between the adjacent active area unit 160B.One active area unit 160B and its The external series gap 160A of adjacent one constitutes a spacing unit 160.

Wherein, the minimum feature size of the exposure development size of photoresist is the characteristic size of the spacing unit 160 Odd-multiple.

In a kind of embodiment, the characteristic size of the spacing unit 160 includes 30nm

The present embodiment active array includes that semiconductor substrate and active area unit 160B and external series gap 160A are formed Spacing unit 160, and the characteristic size of spacing unit 160 includes 30nm, improves photoetching minimum precision, makes random storage device It can satisfy certain specific 160 sizes of spacing unit.

Embodiment three

In order to achieve the above objectives, a kind of random access memory of the utility model, including it is such as above-mentioned as described in the examples active Array and multiple device cells and shallow groove isolation structure.

Multiple device cells are formed on active area unit 160B.

Shallow groove isolation structure is formed in the semiconductor substrate by the way that isolated material is filled in the external series gap 160A In 110.

Wherein, when the characteristic size of the spacing unit 160 includes 30nm, the unit and the shallow groove isolation structure Between spacing also include 30nm.

In the present embodiment random access memory positioned at random access memory device semiconductor substrate 110 on unit and shallow slot every It can be 30nm from the distance between structure, while including active area unit in the semiconductor substrate 110 of random access memory device The storage array of the spacing unit 160 of 160B and external series gap 160A composition, meets the certain smaller spacing lists of random access memory First 160 sizes requirement, improves the performance of random access memory.

More than, only specific embodiment of the present utility model, but protection scope of the utility model is not limited thereto, Anyone skilled in the art within the technical scope disclosed by the utility model, can readily occur in its various change Or replacement, these should be covered within the scope of the utility model.Therefore, protection scope of the utility model Ying Yiquan Subject to the protection scope that benefit requires.

In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", The orientation or positional relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " is based on the figure Orientation or positional relationship is merely for convenience of describing the present invention and simplifying the description, rather than the dress of indication or suggestion meaning It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to the utility model Limitation.

In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include one or more of the features.The meaning of " plurality " is two or two in the description of the present invention, More than, unless otherwise specifically defined.

In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu It is fixed " etc. terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be Mechanical connection, is also possible to be electrically connected, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through Even, the connection inside two elements or the interaction relationship of two elements be can be.For those of ordinary skill in the art For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.

In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it "lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to Cross the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above " One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special Sign includes fisrt feature right above second feature and oblique upper under the second feature " below ", " below " and " below ", or only Indicate that first feature horizontal height is less than second feature.

Above disclosure provides many different embodiments or example is used to realize the different structure of the utility model. In order to simplify the disclosure of the utility model, above the component of specific examples and setting are described.Certainly, they are only Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.

Claims (3)

1. a kind of active array, which is characterized in that including：

Semiconductor substrate；And

The active area unit and the external series gap between the adjacent active area unit being formed in the semiconductor substrate The spacing unit of composition；

Wherein, the minimum feature size of the exposure development size of photoresist is the odd-multiple of the characteristic size of the spacing unit.

2. active array as described in claim 1, which is characterized in that the characteristic size of the spacing unit includes 30nm.

3. a kind of random access memory, which is characterized in that including：

Active array as described in claim 1；

Multiple device cells are formed on the active area unit；And

Shallow groove isolation structure by the way that isolated material is filled in the external series gap, and is formed in semiconductor substrate.