CN112909079A - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

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CN112909079A
CN112909079A CN202110258183.7A CN202110258183A CN112909079A CN 112909079 A CN112909079 A CN 112909079A CN 202110258183 A CN202110258183 A CN 202110258183A CN 112909079 A CN112909079 A CN 112909079A
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forming
shallow trench
semiconductor substrate
semiconductor device
barrier layer
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CN112909079B (en
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孙访策
黄冲
曹子贵
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

In a semiconductor device and a method of forming the same provided by the present invention, a method of forming a semiconductor device includes the steps of: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure; flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the DSTI CMP process has better planarization effect, and the CMP disturbing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI dent is smaller, the problem of early opening of the MOSFET device caused by concentration of the tip electric field of the STI dent area is solved, and the leakage current of the MOSFET device is reduced.

Description

Semiconductor device and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are required to achieve faster operation speed. Larger data storage capacity and more functions, semiconductor devices are developed toward higher element density and high integration, and the requirements for their physical structure and manufacturing process are also increasing. The MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device has a leakage problem. Among them, STI (shallow trench isolation) recess (divot) is one of the causes of leakage of the MOSFET device. In general, the deeper the depth of the STI recess, the more significant the leakage of the MOSFET device.
As shown in fig. 1, the gate structure 11 of the MOSFET device includes a gate oxide layer and a gate polysilicon formed in sequence. One of the reasons that the STI recess causes the electric leakage is that the gate oxide layer at the boundary between the active region (ACT) and the STI (i.e., the region a) is thin, specifically, the gate oxide layer is generated in a thermal oxidation manner, the stress at the boundary between the active region and the STI is large, so that oxygen atoms are difficult to enter the active region and form silicon dioxide with the silicon substrate of the active region, and finally the gate oxide layer at the boundary between the active region and the STI is thin, so that the device in the region is easy to open, and the electric leakage in the region is increased; the second reason why the STI recess causes the leakage is that in the region a, in the subsequent process of forming the gate structure 11, since the electric field at the region a is concentrated, the device in the region is easier to turn on, and the leakage in the region increases accordingly.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can reduce the problem of STI recess so as to reduce the leakage current of a MOSFET device.
In order to achieve the above object, the present invention provides a method of forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a barrier layer on the semiconductor substrate;
forming a shallow trench structure in the semiconductor substrate;
flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and
and removing the barrier layer.
Optionally, the thickness of the barrier layer is
Figure BDA0002968422600000021
Optionally, before forming the barrier layer on the semiconductor substrate, a first pad oxide layer is further formed on the semiconductor substrate.
Further, the forming of the shallow trench structure in the semiconductor substrate includes:
etching the barrier layer, the first pad oxide layer and the semiconductor substrate in sequence, and stopping etching in the semiconductor substrate to form a shallow trench;
thermally treating the semiconductor substrate to form a second pad oxide layer in the shallow trench; and
and forming a filling layer in the shallow trench to form a shallow trench structure.
Furthermore, the filling layer is formed in the shallow trench by a high-density plasma oxidation layer deposition process, and the filling layer is also formed on the barrier layer at the same time.
Further, the material of the filling layer comprises silicon dioxide, and the material of the barrier layer comprises silicon nitride.
Further, when the shallow trench structure is subjected to planarization processing through a DSTI CMP process, the polishing liquid with the high selection ratio of the filling layer and the barrier layer is selected.
Further, after the DSTI CMP process, the filling layer with a part of thickness in the STI is etched and removed through an etching process.
Further, a gate structure, a source region and a drain region are sequentially formed on the semiconductor substrate, so as to form a semiconductor device, wherein the source region and the drain region are located between the adjacent shallow trench structures, and the gate structure is located between the source region and the drain region and separates the source region from the drain region.
In another aspect, the invention also provides a semiconductor device prepared by the method.
Compared with the prior art, the invention has the following beneficial effects:
in a semiconductor device and a method of forming the same provided by the present invention, a method of forming a semiconductor device includes the steps of: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure in the semiconductor substrate; flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the DSTI CMP process has better planarization effect, and the CMP disturbing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI dent is smaller, the problem of early opening of the MOSFET device caused by concentration of the tip electric field of the STI dent area is solved, and the leakage current of the MOSFET device is reduced.
Further, the thickness of the barrier layer is
Figure BDA0002968422600000031
The thickness of the barrier layer is larger than that of the silicon nitride layer in the prior art
Figure BDA0002968422600000032
In other words, the thickness is reduced, the stress at the boundary of the active region and the STI is reduced, the risk of STI recess generation in the subsequent mechanical grinding process and wet etching process is reduced, and cracks on the surface of the barrier layer and the surface of the semiconductor substrate below the barrier layer in the mechanical grinding process are avoided.
Drawings
FIG. 1 is a top view of a semiconductor device with STI recesses;
FIG. 2 is a schematic cross-sectional view of a prior art semiconductor device;
fig. 3 is a flow chart illustrating a method of forming a semiconductor device according to an embodiment of the invention;
fig. 4a to 4e are schematic cross-sectional views of a part of steps in a flow chart of a method for forming a semiconductor device according to an embodiment of the invention.
Description of reference numerals:
in FIGS. 1-2:
11-a gate structure; 12-a pad bottom oxide layer; 13-underlying silicon nitride layer; 14-HDP layer;
in FIGS. 4a-4 e:
100-a semiconductor substrate; 111-first pad bottom oxide layer; 112-a second pad oxide layer; 120-barrier layer, 130-fill layer.
Detailed Description
As described in the background, the stress at the boundary of the active region and the STI is large, which eventually results in a thin gate oxide layer at the boundary of the active region and the STI. As shown in fig. 2, stress at the boundary of the active region and the STI is formed for two reasons: one of the reasons is that when the STI linear (i.e. the pad oxide layer 12 in the shallow trench is formed, the material of the pad oxide layer 12 is silicon dioxide), since the process is a thermal diffusion process, oxygen atoms need to enter into a silicon lattice, but since the silicon lattice in the inner corner region of the bottom of the STI groove is difficult to unload the stress caused by oxygen diffusion through deformation, oxygen diffusion is difficult to perform, and therefore, the thickness of the silicon dioxide in the inner corner region at the bottom of the STI groove is thin, and the thickness of the silicon dioxide in the outer corner region at the opening of the STI groove is opposite, so that the thickness of the silicon dioxide in the outer corner region is thick; the second reason is that, during the STI HDP (high density plasma oxide layer, which is specifically made of silicon dioxide) deposition process, the receiving angle of the outer corner region is larger, so that the thickness of the HDP layer 14 in the HDP process of the outer corner region is thicker, while the thickness of the HDP layer 14 in the HDP process of the inner corner region is thinner, so that the thickness of the silicon dioxide of the outer corner region is further thicker. Since the thermal expansion coefficient of silicon dioxide is lower than that of silicon, a concentrated compressive stress of silicon dioxide to the silicon substrate at the STI trench opening is formed in the outer corner region, and the compressive stress results in a higher activation energy at the boundary between the active region and the STI during subsequent processes (e.g., an STI CMP (Chemical Mechanical Polishing) process and a wet etching (wet etching) process), which results in a higher Polishing rate of the STI CMP process to silicon dioxide, and a higher etching rate of the wet etching process to silicon dioxide, thereby causing STI dishing.
From the above analysis, the thickness of the substrate nitride layer 13 will affect the magnitude of the stress in the STI outer corner region. The substrate nitride layer 13 with a smaller thickness will have better STI recess performance (i.e. the depth of the STI recess is shallower), but the thickness of the substrate nitride layer 13 cannot be too thin, when the thickness of the substrate nitride layer 13 is too thin, cracks will appear on the surface of the substrate nitride layer 13 during the subsequent STI CMP process, and there is a possibility that the silicon substrate located below the substrate nitride layer 13 will crack under the mechanical polishing force.
Based on the research, the invention provides a semiconductor device and a forming method thereof, wherein the forming method of the semiconductor device has better planarization effect through a DSTI CMP process compared with the STI CMP process in the prior art, and the CMP disturbing phenomenon on a grinding surface does not occur in the DSTI CMP process, so that the depth of an STI dent is smaller, the problem of early opening of an MOSFET device caused by concentration of a tip electric field in the STI dent area is solved, and the leakage current of the MOSFET device is reduced.
The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
The embodiment provides a method for forming a semiconductor device. Fig. 3 is a flowchart illustrating a method of forming a semiconductor device according to this embodiment. As shown in fig. 3, the method comprises the steps of:
step S10: providing a semiconductor substrate;
step S20: forming a barrier layer on the semiconductor substrate;
step S30: forming a shallow trench structure in the semiconductor substrate;
step S40: flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and
step S50: and removing the barrier layer.
A method for forming a semiconductor device provided in this embodiment will be described in detail below with reference to fig. 3 to 4.
Fig. 4a is a schematic cross-sectional view of a semiconductor substrate provided in this embodiment. As shown in fig. 4a, step S10 is first performed to provide a semiconductor substrate 100.
The semiconductor substrate 100 may provide an operation platform for subsequent processes, and may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a bare die, or a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, but is not limited to, a silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, and the like. In the present embodiment, a first pad bottom oxide layer 111 is formed on the semiconductor substrate 100.
Fig. 4b is a schematic cross-sectional view of the barrier layer formed in the present embodiment. As shown in fig. 4b, next, step S20 is performed to form a barrier layer 120 on the semiconductor substrate. The material of the barrier layer 120 is, for example, silicon nitride. The barrier layer 120 has a thickness of
Figure BDA0002968422600000061
The specific thickness is, for example
Figure BDA0002968422600000062
Figure BDA0002968422600000063
Etc. which has a thickness greater than that of the silicon nitride layer of the prior art
Figure BDA0002968422600000064
In other words, the thickness is reduced, the stress at the boundary between the active region and the STI is reduced, the risk of STI dishing during the subsequent mechanical polishing process and wet etching process is reduced, and cracks on the surface of the barrier layer 120 and the surface of the semiconductor substrate 100 below the barrier layer 120 during the mechanical polishing process are also avoided.
Fig. 4c is a schematic cross-sectional view of the barrier layer formed in the present embodiment. As shown in fig. 4c, next, step S30 is performed to form a shallow trench structure in the semiconductor substrate.
The method specifically comprises the following steps:
first, the barrier layer 120, the first pad oxide layer 111, and the semiconductor substrate 100 are sequentially etched, and the etching is stopped in the semiconductor substrate 100 to form a shallow trench. In this embodiment, in this step, the barrier layer 120, the first pad oxide layer 111, and the semiconductor substrate 100 may be sequentially etched by a dry etching process, and the etching is stopped in the semiconductor substrate 100 to form a shallow trench, where the semiconductor substrate between adjacent trenches is used to form an active region.
Next, the semiconductor substrate 100 is heat-treated to form the second bottom oxide layer 112 in the shallow trench, which is, for example, an STI linear process, in which a thin silicon dioxide layer is formed in an inner corner region of the bottom of the shallow trench and a thicker silicon dioxide film layer is formed in an outer corner region of the opening of the shallow trench, that is, the heat treatment process forms the second bottom oxide layer 112 in the inner corner region of the shallow trench to be thinner and forms the second bottom oxide layer 112 in the outer corner region to be thicker. The thinning of the barrier layer 120 of the present embodiment reduces the influence of the thicker thickness of the second underlying oxide layer 112 formed in the outer corner region in this step on the subsequent processes.
Then, a filling layer 130 is formed in the shallow trench to form a shallow trench structure. The filling layer is formed in the shallow trench by, for example, a HDP (high density plasma oxidation) deposition process, and is also formed on the barrier layer 120, and the specific material of the filling layer 130 is, for example, silicon dioxide. In the step, thicker silicon dioxide is formed in the outer corner area of the shallow trench, which is not beneficial to the subsequent mechanical grinding process and wet etching process.
FIG. 4d is a schematic cross-sectional view of the DSTI CMP process of the present embodiment. As shown in fig. 4d, step S40 is performed to planarize the shallow trench structure by a DSTI CMP process.
In this step, first, a high-selectivity polishing slurry for the filler layer 130 and the barrier layer 120 is selected, and in this embodiment, CeO is used2Abrasive, typically CeO2The abrasive has a smaller particle diameter and a uniform size than a conventional abrasive. And due to CeO2The silicon nitride has the capability of adsorbing negative ions, and the silicon nitride also has the capability of adsorbing negative ions, and negative ion polymers are added into the grinding fluid and are respectively wrapped in CeO like a protective film2The surface of the particle and the barrier layer has greatly reduced contact chance due to the repulsive effect of the anionic polymer, and the filling layer 130 has no strong adsorption capacity, and CeO2The particles can act on the surface of the filling layer 130 to cause corresponding physical and chemical reactions, so that a high selectivity ratio of silicon dioxide/silicon nitride can be realized. CeO (CeO)2The abrasive material makes the grinding rate of the filling layer low, so that the grinding amount of the filling layer 130 is small. Next, the semiconductor substrate 100 is polished.
As can be seen from the above, the DSTI CMP process of this step can reduce the polishing thickness of the barrier layer 120 due to the high selectivity ratio, thereby reducing the stress at the boundary between the active region and the STI, and the planarization effect of the DSTI CMP process is better than that of the general STI CMP (i.e., the planarization effect of the DSTI CMP process is higher than that of the general STI CMP), and the CMP lifting phenomenon (i.e., the phenomenon of dishing occurs above the shallow trench, so that the surface is wavy) does not occur on the polishing surface in the DSTI CMP process, so that the depth of the STI dishing is also smaller, thereby solving the problem of early turn-on of the MOSFET device due to the concentration of the tip electric field in the STI dishing region, i.e., reducing the leakage current of the MOSFET device.
Optionally, after the DSTI CMP process, the filling layer 130 with a partial thickness in the STI is removed by etching through an etching process to reduce the surface height of the STI relative to the surface height of the semiconductor substrate. The etching process may be a dry etching process and/or a wet etching process. In this embodiment, for example, a wet etching process is used to etch the oxide layer in the STI, and an etching solution of the wet etching process is HF.
Next, step S50 is executed to remove the barrier layer 120. In this embodiment, the barrier layer 120 is removed by a wet etching process. In this step, since the stress at the boundary between the active region and the STI is small, the STI dishing effect is reduced, and the leakage current of the semiconductor device is reduced.
As shown in fig. 1, a gate structure, a source region and a drain region are sequentially formed on the semiconductor substrate 100, thereby forming a semiconductor device. The gate structure, for example, sequentially includes a gate oxide layer and a gate polysilicon formed on the semiconductor substrate, and an active region (i.e., a source region and a drain region) is formed in the semiconductor substrate between adjacent shallow trench structures. The gate structure is located between the source region and the drain region and separates the source region and the drain region. The gate structure, the source region and the drain region are arranged in parallel, the extending direction of the gate structure is the width direction of the active region, and the direction perpendicular to the extending direction of the gate structure is the length direction of the active region. The leakage current of the MOSFET device formed by the above process is reduced more remarkably as the width of the active region is smaller (the width of the active region is less than 1 μm).
As shown in fig. 4e, taking the low voltage Nmos transistor as an example, when the active region of the low voltage Nmos transistor has a width of 0.14 μm and a length of 0.12 μm, the abscissa is the gate-source voltage Vgs, the ordinate is the leakage current Id, the drain-source voltage Vds is 1.65V, and the source-source voltage Vbs is 0V, -0.375V, -0.75V, -1.125V, -1.5V, respectively, the solid line in fig. 4e is the Vgs/Id curve of the Nmos transistor prepared by the conventional process, and the dotted line is the Vgs/Id curve of the Nmos transistor prepared by the present process. It can be seen in the region b that when the value of the gate-source voltage Vgs is between 0.5V and-0.5V, the value of the leakage current Id of the Nmos transistor prepared by the process of the present invention is significantly smaller than that of the leakage current Id of the Nmos transistor prepared by the existing process, that is, the Nmos transistor prepared by the process of the present invention has smaller leakage, and exhibits better device characteristics.
The embodiment also provides a semiconductor device prepared by the method.
In summary, in the semiconductor device and the forming method thereof provided by the present invention, the forming method of the semiconductor device includes the following steps: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure; flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the DSTI CMP process has better planarization effect, and the CMP disturbing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI dent is smaller, the problem of early opening of the MOSFET device caused by concentration of the tip electric field of the STI dent area is solved, and the leakage current of the MOSFET device is reduced.
Further, the thickness of the barrier layer is
Figure BDA0002968422600000081
The thickness of the barrier layer is larger than that of the silicon nitride layer in the prior art
Figure BDA0002968422600000082
In other words, the thickness is reduced, the stress at the boundary of the active region and the STI is reduced, the risk of STI recess generation in the subsequent mechanical grinding process and wet etching process is reduced, and meanwhile, the mechanical grinding process and the wet etching process are also avoidedDuring the grinding process, cracks appear on the surface of the barrier layer and on the surface of the semiconductor substrate below the barrier layer.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A method for forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a barrier layer on the semiconductor substrate;
forming a shallow trench structure in the semiconductor substrate;
flattening the shallow trench structure by a DSTI (double patterning of shallow trench isolation) CMP (chemical mechanical polishing) process; and
and removing the barrier layer.
2. The method of forming a semiconductor device according to claim 1, wherein the barrier layer has a thickness of
Figure FDA0002968422590000011
3. The method for forming a semiconductor device according to claim 1, wherein a first pad oxide layer is further formed over the semiconductor substrate before the barrier layer is formed over the semiconductor substrate.
4. The method of forming a semiconductor device according to claim 3, wherein forming a shallow trench structure in the semiconductor substrate comprises:
etching the barrier layer, the first pad oxide layer and the semiconductor substrate in sequence, and stopping etching in the semiconductor substrate to form a shallow trench;
thermally treating the semiconductor substrate to form a second pad oxide layer in the shallow trench; and
and forming a filling layer in the shallow trench to form a shallow trench structure.
5. The method of forming a semiconductor device according to claim 4, wherein the filling layer is formed in the shallow trench by a high density plasma oxide deposition process, and the filling layer is also formed on the barrier layer at the same time.
6. The method for forming a semiconductor device according to claim 5, wherein a material of the filling layer comprises silicon dioxide, and a material of the barrier layer comprises silicon nitride.
7. The method of claim 6, wherein the high selectivity slurry for the fill layer and the barrier layer is selected when the shallow trench structure is planarized by a DSTI CMP process.
8. The method of claim 7, wherein after the DSTI CMP process, a portion of the thickness of the fill layer in the STI is etched away by an etching process.
9. The method of forming a semiconductor device according to claim 8, wherein a gate structure, a source region, and a drain region are sequentially formed on the semiconductor substrate, thereby forming a semiconductor device, wherein the source region and the drain region are located between adjacent shallow trench structures, and the gate structure is located between the source region and the drain region and separates the source region and the drain region.
10. A semiconductor device produced by the method for forming a semiconductor device according to any one of claims 1 to 9.
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