CN108581639A - A kind of control method and its control system of CMP process - Google Patents
A kind of control method and its control system of CMP process Download PDFInfo
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- CN108581639A CN108581639A CN201810247675.4A CN201810247675A CN108581639A CN 108581639 A CN108581639 A CN 108581639A CN 201810247675 A CN201810247675 A CN 201810247675A CN 108581639 A CN108581639 A CN 108581639A
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- 238000000034 method Methods 0.000 title claims abstract description 146
- 230000008569 process Effects 0.000 title claims abstract description 82
- 238000000227 grinding Methods 0.000 claims abstract description 157
- 230000004888 barrier function Effects 0.000 claims abstract description 65
- 238000012937 correction Methods 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 235000012431 wafers Nutrition 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000003082 abrasive agent Substances 0.000 claims description 6
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 150000001450 anions Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010539 anionic addition polymerization reaction Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a kind of control method of CMP process and its control systems,The CMP process includes the process of lapping on the grinding barrier layer to wafer dielectric layer and below the dielectric layer,The control method is by introducing amount of grinding correction value △ d=(D0 D2 D1) * k,Wherein,D0 is the original depth on the grinding barrier layer,D2 is the final thickness on the grinding barrier layer after grinding,D1 is the removal desired value on the grinding barrier layer,K is the selection ratio on the grinding barrier layer,Allow the control method according to the removal desired value D1 on the grinding barrier layer as benchmark,Obtain amount of grinding correction value △ d,To constantly update and align hone amount d2,So that the control system forms the closed-loop system of a correction value,It may be implemented to accurately control amount of grinding d2,Improve the homogeneity of grinding thickness in manufacture of semiconductor,To improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of CMP (Chemical Mechanical
Planarization, chemical-mechanical planarization) technique control method and its control system.
Background technology
CMP process is the important process in semiconductor devices manufacture, it is made using chemical attack and the collaboration of mechanical grinding
With can effectively take into account semiconductor devices part and global flatness.
Currently, the control method of CMP process mainly has the grinding method and terminal for directly using the set time (By time)
The grinding method of (endpoint) is monitored, optical ISRM (In Situ Rate Monitor, in situ detection) terminal is such as used
Detecting system, or carry out endpoint monitoring using TCM (Table Current Monitor, table current monitoring) detecting system
Grinding method.But when directly using the grinding method of set time, since grinding rate is with the variation of consumptive material service life
Larger, then the grinding method of set time is poor for the removal controlling of amount of grinding in processing procedure；Whole using optical ISRM
In the grinding method of point monitoring, because optical end point method for detecting is sometimes difficult to accurately differentiate endpoint signal, therefore lead to its mistake
Efficiency is very high, influences the performance of semiconductor devices；In addition, being transformed into board by the way that frictional force is changed into current signal
The grinding method of TCM detecting systems not only needs additional improvement expenses, while crash rate is also higher, leads to semiconductor devices
Poor performance.
Therefore, it is necessary to provide a kind of control method and its control system of new CMP process.
Invention content
Technical problem to be solved by the invention is to provide a kind of control method of CMP process and its control systems, to carry
Amount of grinding accurately controls in high CMP process, to improving the performance of semiconductor devices.
In order to solve the above technical problems, the control method of CMP process provided by the invention, the CMP process includes to crystalline substance
The process of lapping of circle dielectric layer and the grinding barrier layer below the dielectric layer, the control method include：
Step 1：It sets amount of grinding theoretical value d1, the amount of grinding theoretical value d1 and is equal to 0 He of thickness d of the dielectric layer
The sum of the removal desired value D1 on the grinding barrier layer, process is ground to wherein a piece of or in which a batch of wafer；
Step 2：Measure the final thickness D2 on the grinding barrier layer after grinding；
Step 3：Calculate amount of grinding correction value △ d, amount of grinding correction value △ d=(D0-D2-D1) the * k, wherein
D0 is the original depth on the grinding barrier layer, and k is the selection ratio on the grinding barrier layer；
Step 4：Obtain amount of grinding d2, the amount of grinding d2 and the amount of grinding theoretical value d1 and amount of grinding correction value △ d
The sum of correlation；
Step 1 is iteratively repeated to step 4, until completing this time process of lapping of all wafers, wherein repeating every time
During step 1, the amount of grinding theoretical value d1 is replaced with the amount of grinding d2 that last step 4 obtains.
Further, further include setting grinding proportion a, then amount of grinding d2=(the d1+ △ d) * in the step 1
a。
Optionally, in the control method of the CMP process, the numberical range of a is 1%~100%.
Optionally, in the control method of the CMP process, the dielectric layer includes oxide skin(coating).
Further, in the control method of the CMP process, the oxide skin(coating) includes silicon dioxide layer, highly dense
Spend plasma oxidation layer or the combination layer of high-density plasma oxide layer and teos layer.
Optionally, in the control method of the CMP process, the grinding barrier layer includes silicon nitride layer.
Further, the production method of the wafer includes：One substrate is provided；Form a barrier layer, the barrier layer position
In in the substrate；A groove is formed, the groove is through the barrier layer and in the substrate, the remaining blocking
Layer is grinding barrier layer；A dielectric layer is covered, the dielectric layer filling is completely described to be open and cover the grinding barrier layer.
Optionally, the CMP process is DSTI CMP.
Further, further include the step of the determining dielectric layer and the selection ratio on grinding barrier layer before the step 1
Suddenly.
Correspondingly, another side according to the present invention, the present invention also provides a kind of control system of CMP process, the controls
System includes CMP machine platform, and the CMP machine platform executes process of lapping using above-mentioned control method.
Further, in the control system of the CMP process, the control system is APC system.
Further, in the control system of the CMP process, the CMP machine platform uses grinding comprising CeO2 abrasive materials
Grinding fluid.
Compared with prior art, the invention has the advantages that：
The present invention proposes that a kind of control method and control system of CMP process, the CMP process include to medium in wafer
The process of lapping of layer and the grinding barrier layer below the dielectric layer, the control method are repaiied by introducing an amount of grinding
Positive value △ d=(D0-D2-D1) * k, wherein D0 is the original depth on the grinding barrier layer, and D2 is the grinding after grinding
The final thickness on barrier layer, D1 are the removal desired value on the grinding barrier layer, and k is the selection ratio on the grinding barrier layer, is made
Amount of grinding correction value △ can be obtained according to the removal desired value D1 on the grinding barrier layer as benchmark by obtaining the control method
D, to constantly update and align hone amount d2 so that the control system forms the closed-loop system of a correction value, can be with
Realization accurately controls amount of grinding d2, the homogeneity of grinding thickness in manufacture of semiconductor is improved, to improve semiconductor devices
Performance.
Description of the drawings
Fig. 1 is a kind of flow chart of the control method of CMP process described in the embodiment of the present invention；
Fig. 2 is the crystal circle structure schematic diagram before CMP process in the embodiment of the present invention；
Fig. 3 is the crystal circle structure schematic diagram after CMP process in the embodiment of the present invention.
Specific implementation mode
In recent years, APC (Advanced Process Control, advanced process control) system common application in
The final thickness that product is controlled in CMP process, compared to the grinding side for the grinding method or endpoint monitoring for using the set time
Method can more accurately control amount of grinding.In traditional STI (Shallow Trench Isolation, shallow trench isolation)
In CMP process, desired value is set as to the final thickness value of product using APC system, is ground the time on this basis
Feedback.However, in DSTI (Direct Shallow Trench Isolation, direct shallow trench isolation) CMP process,
The silicon dioxide layer on active area is anti-carved because not needing additional etch step, can directly be ground, then compared to traditional
STI CMP process needs the lapping liquid using high selectivity；In addition, the lapping liquid of high selectivity causes to be located at the titanium dioxide
The grinding rate of silicon nitride layer below silicon layer is very low (about).Therefore, traditional STI CMP process cannot be satisfied DSTI
The requirement of CMP process.
Then, inventor passes through a series of researchs, it is proposed that a kind of control method of CMP process can meet DSTI CMP
Technological requirement, as shown in Figure 1, the control method includes：
Step 1：It sets amount of grinding theoretical value d1, the amount of grinding theoretical value d1 and is equal to 0 He of thickness d of the dielectric layer
The sum of the removal desired value D1 on the grinding barrier layer, process is ground to wherein a piece of or in which a batch of wafer；
Step 2：Measure the final thickness D2 on the grinding barrier layer after grinding；
Step 3：Calculate amount of grinding correction value △ d, amount of grinding correction value △ d=(D0-D2-D1) the * k, wherein
D0 is the original depth on the grinding barrier layer, and k is the selection ratio on the grinding barrier layer；
Step 4：Obtain amount of grinding d2, the amount of grinding d2 and the amount of grinding theoretical value d1 and amount of grinding correction value △ d
The sum of correlation；
Step 1 is iteratively repeated to step 4, until completing the process of lapping of all wafers, wherein repeating step every time
During one, the amount of grinding theoretical value d1 is replaced with the amount of grinding d2 that last step 4 obtains.
Correspondingly, another side according to the present invention, the present invention also provides a kind of control system of CMP process, the controls
System includes CMP machine platform, and the CMP machine platform executes process of lapping using above-mentioned control method.
The present invention proposes that a kind of control method and control system of CMP process, the CMP process include to medium in wafer
The process of lapping of layer and the grinding barrier layer below the dielectric layer, the control method are repaiied by introducing an amount of grinding
Positive value △ d=(D0-D2-D1) * k, wherein D0 is the original depth on the grinding barrier layer, and D2 is the grinding after grinding
The final thickness on barrier layer, D1 are the removal desired value on the grinding barrier layer, and k is the selection ratio on the grinding barrier layer, is made
Amount of grinding correction value △ can be obtained according to the removal desired value D1 on the grinding barrier layer as benchmark by obtaining the control method
D, to constantly update and align hone amount d2 so that the control system forms the closed-loop system of a correction value, can be with
Realization accurately controls amount of grinding d2, the homogeneity of grinding thickness in manufacture of semiconductor is improved, to improve semiconductor devices
Performance.
The control method and its control system of a kind of CMP process of the present invention are carried out below in conjunction with schematic diagram more detailed
Description, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change described here
The present invention, and still realize the advantageous effects of the present invention.Therefore, following description should be understood as those skilled in the art
It is widely known, and be not intended as limitation of the present invention.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
It is exemplified below the control method of DSTI CMP process and its embodiment of control system, clearly to illustrate the present invention's
Content, it is understood that, present disclosure is not restricted to following embodiment, other to pass through those of ordinary skill in the art
Conventional technical means improvement also the present invention thought range within.
The DSTI CMP process includes the grinding barrier layer to wafer dielectric layer and below the dielectric layer
Process of lapping.Specifically, in the present embodiment, the manufacturing process of the wafer includes：There is provided a substrate 10, the substrate 10 can be with
But be not limited to silicon base, silicon germanium semiconductor substrate, silicon carbide substrate etc.；A barrier layer is formed in the substrate 10, certainly,
Further include first growing one layer of thin oxide layer on 10 surface of the substrate before forming the barrier layer in actual technique
(schematic diagram omits in figure)；Then, a groove is formed using conventional lithography and etching technique, the groove runs through the blocking
Layer is simultaneously located in the substrate 10, then the remaining barrier layer is grinding barrier layer, preferably, the grinding barrier layer can be with
But it is not limited to include silicon nitride layer, it is preferred that in the present embodiment, the grinding barrier layer is silicon nitride layer 11；Jie is covered again
Matter layer, the dielectric layer filling completely groove simultaneously cover the silicon nitride layer 11, and the dielectric layer is oxide skin(coating), the oxygen
Compound layer can be, but not limited to as silicon dioxide layer, high-density plasma oxide layer (HDP) or be high-density plasma oxidation
The combination layer of layer (HDP) and teos layer (TEOS), it is preferred that the dielectric layer is silicon dioxide layer 12, then described recessed
The corresponding structure of slot is the fleet plough groove isolation structure 100 subsequently needed to form.Because in the present embodiment, the manufacturing process of the wafer
Be it is known to a person skilled in the art, not described in detail herein.
Next, CMP process is directly carried out in said structure, firstly, it is necessary to determine using the silicon dioxide layer 12
With the lapping liquid of the high selectivity of silicon nitride layer 11, in the present embodiment, can no longer meet using original silicon abrasive material, Ke Yixuan
Select CeO2Abrasive material, in general, CeO2Abrasive material wants small compared to the particle diameter of common abrasive material, and size is uniform.Moreover, because of CeO2From
Body has the ability of absorption anion, and silicon nitride also has the ability of absorption anion, and it is poly- that anion is added in lapping liquid
Zoarium, these anionic polymerization bodies are rolled in CeO respectively just as layer protecting film2The surface of particle and silicon nitride, due to anion
Polymeric repulsive interaction makes the chance that both the above substance contacts greatly reduce, and since there is no very strong for silicon oxide film
Adsorption capacity, CeO2Particle can act on the surface with silica, generate corresponding physical and chemical reaction, to realize pair
The high selectivity of silicon dioxide layer/silicon nitride layer.
Then, process of lapping is executed by CMP machine platform, the CMP machine platform can be the Mirra boards of AMAT, the CMP
Board uses APC system, referring to Fig. 1, the control method in the APC system includes：
Step 1：It sets amount of grinding theoretical value d1, the amount of grinding theoretical value d1 and is equal to 0 He of thickness d of the dielectric layer
The sum of the removal desired value D1 on the grinding barrier layer, process is ground to wherein a piece of or in which a batch of wafer；
Specifically, in order to improve the accurate of amount of grinding, a piece of wherein or in which a collection of secondary wafer (such as first or
A batch of wafer, the wafer of the first batch can be, but not limited to include 12 wafers) when being ground, only in accordance with grinding
Theoretical value d1 is ground, the thickness d 0 and the grinding barrier layer 11 that the grinding theoretical value d1 need to be in conjunction with the dielectric layer 12
Removal desired value D1 depending on, the grinding theoretical value d1 is the thickness d 0 and the silicon nitride layer 11 of the silicon dioxide layer 12
The sum of removal desired value D1.After setting amount of grinding theoretical value d1, the APC system run in CMP machine platform realizes process of lapping.
In addition, in this step, grinding proportion a can also be set, the grinding proportion a can be between 1%~100%.In addition, this
Field technology personnel know, include the technique etching information of the wafer, the wafer level inside the APC system
Other related process parameters such as Layer information and grinding rate, this will not be repeated here.
After above-mentioned process of lapping, structure as shown in Figure 3 is obtained, the DSTI CMP process can completely avoid biography
" the butterfly effect " occurred in system STI CMP process, the effect structure that DSTI CMP process is formed are very good.In order to ensure wafer
The consistency of amount of grinding between wafer, next, the control method executes step 2：Measure the grinding resistance after grinding
The final thickness D2 of barrier measures the thickness D2 of the silicon nitride layer 11 ' after grinding.
Then, a step of most critical in the control method, i.e. step 3 are executed, amount of grinding correction value △ d, institute are calculated
State amount of grinding correction value △ d=(D0-D2-D1) * k, wherein D0 is the original depth on the grinding barrier layer, and k is the grinding
The selection ratio on barrier layer.Specifically, the control method (is theoretically removed with the removal desired value D1 of the silicon nitride layer 11
The thickness value of the silicon nitride layer 11) on the basis of, obtain the removal thickness and theoretical value of silicon nitride layer 11 described in actual process
Deviation obtain amount of grinding correction value △ d to again according to the selection ratio of the silicon nitride layer.
Next, timely feedbacking the amount of grinding correction value △ d that the control method obtains to APC system, APC system is allowed
Execute step 4：Obtain the sum of amount of grinding d2, the amount of grinding d2 and the amount of grinding theoretical value d1 and amount of grinding correction value △ d
Correlation, preferably, the amount of grinding d2=(d1+ △ d) * a, a may be set between 1%~100%, such as in the present embodiment
In, a is set as 100%, i.e., the described amount of grinding d2=d1+ △ d.
Finally, step 1 is repeated to step 4, wherein during repeating step 1, is obtained with above-mentioned step 4
The amount of grinding d2 replaces the amount of grinding theoretical value d1.Specifically, after the completion of the process of lapping of above-mentioned wafer, when APC systems
When system obtains amount of grinding d2 by above-mentioned control method, APC system will be using the amount of grinding d2 as back wafer (such as second
The wafer of piece or second lot) amount of grinding.
In this way, step 1 is iteratively repeated to step 4, until completing the process of lapping of all wafers.Like this, CMP machine platform
APC system process of lapping, the control of the APC system are executed to the wafer of a piece of another or one batch another batch
Method processed passes through with the removal desired value D1 (thickness value for theoretically removing the silicon nitride layer 11) of the silicon nitride layer 11
On the basis of, constantly remove the amount of grinding for updating and correcting back wafer so that APC system forms a closed loop body for having correction value
System, may be implemented to accurately control silicon nitride layer removal amount, you can to ensure the consistency of the amount of grinding of all wafers, to
Improve the performance of semiconductor devices.
To sum up, the present invention proposes a kind of control method and control system of CMP process, and the CMP process includes to wafer
The process of lapping of dielectric layer and the grinding barrier layer below the dielectric layer, the control method are ground by introducing one
Mill amount correction value △ d=(D0-D2-D1) * k, wherein D0 is the original depth on the grinding barrier layer, and D2 is the institute after grinding
The final thickness on grinding barrier layer is stated, D1 is the removal desired value on the grinding barrier layer, and k is the selection on the grinding barrier layer
Than so that the control method can obtain amount of grinding and repair according to the removal desired value D1 on the grinding barrier layer as benchmark
Positive value △ d, to constantly update and align hone amount d2 so that the control system forms the closed loop body of a correction value
System, may be implemented to accurately control amount of grinding d2, improve the homogeneity of grinding thickness in manufacture of semiconductor, partly be led to improve
The performance of body device.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (12)
1. a kind of control method of CMP process, the CMP process includes to wafer dielectric layer and below the dielectric layer
Grinding barrier layer process of lapping, which is characterized in that the control method includes：
Step 1：Set amount of grinding theoretical value d1, the amount of grinding theoretical value d1 is equal to the thickness d 0 of the dielectric layer and described
The sum of the removal desired value D1 for grinding barrier layer, process is ground to wherein a piece of or in which a batch of wafer；
Step 2：Measure the final thickness D2 on the grinding barrier layer after grinding；
Step 3：Calculate amount of grinding correction value △ d, amount of grinding correction value △ d=(D0-D2-D1) the * k, wherein D0 is
The original depth on the grinding barrier layer, k are the selection ratio on the grinding barrier layer；
Step 4：Obtain the sum of amount of grinding d2, the amount of grinding d2 and the amount of grinding theoretical value d1 and amount of grinding correction value △ d
It is related；
Step 1 is iteratively repeated to step 4, until completing this time process of lapping of all wafers, wherein repeating step every time
During one, the amount of grinding theoretical value d1 is replaced with the amount of grinding d2 that last step 4 obtains.
2. the control method of CMP process as described in claim 1, which is characterized in that further include setting in the step 1
Proportion a is ground, then amount of grinding d2=(d1+ △ d) the * a.
3. the control method of CMP process as claimed in claim 2, which is characterized in that the numberical range of a is 1%~100%.
4. the control method of CMP process as described in claim 1, which is characterized in that the dielectric layer includes oxide skin(coating).
5. the control method of CMP process as claimed in claim 4, which is characterized in that the oxide skin(coating) includes silica
The combination layer of layer, high-density plasma oxide layer or high-density plasma oxide layer and teos layer.
6. the control method of CMP process as described in claim 1, which is characterized in that the grinding barrier layer includes silicon nitride
Layer.
7. the control method of CMP process as described in claim 1, which is characterized in that the production method of the wafer includes：
One substrate is provided；
A barrier layer is formed, the barrier layer is located in the substrate；
A groove is formed, for the groove through the barrier layer and in the substrate, the remaining barrier layer is grinding
Barrier layer；
A dielectric layer is covered, the dielectric layer filling is completely described to be open and cover the grinding barrier layer.
8. the control method of CMP process as claimed in claim 8, which is characterized in that the CMP process is DSTI CMP.
9. the control method of CMP process as described in claim 1, which is characterized in that before the step 1 further include true
The step of fixed dielectric layer and the selection for grinding barrier layer are compared.
10. a kind of control system of CMP process, which is characterized in that the control system includes CMP machine platform, and the CMP machine platform is adopted
Process of lapping is executed with the control method as described in claim 1 to 9 any one.
11. the control system of CMP process as claimed in claim 10, which is characterized in that the control system is APC system.
12. the control system of CMP process as claimed in claim 10, which is characterized in that the CMP machine platform use includes CeO2
The lapping liquid of abrasive material.
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| CN201810247675.4A CN108581639A (en) | 2018-03-23 | 2018-03-23 | A kind of control method and its control system of CMP process |
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| CN201810247675.4A CN108581639A (en) | 2018-03-23 | 2018-03-23 | A kind of control method and its control system of CMP process |
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| CN201810247675.4A Pending CN108581639A (en) | 2018-03-23 | 2018-03-23 | A kind of control method and its control system of CMP process |
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| TWI775622B (en) * | 2020-12-16 | 2022-08-21 | 日商Ｓｕｍｃｏ股份有限公司 | Method of polishing silicon wafer and method of manufacturing silicon wafer |
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