CN102136426A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN102136426A CN102136426A CN2010101023534A CN201010102353A CN102136426A CN 102136426 A CN102136426 A CN 102136426A CN 2010101023534 A CN2010101023534 A CN 2010101023534A CN 201010102353 A CN201010102353 A CN 201010102353A CN 102136426 A CN102136426 A CN 102136426A
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- clearance wall
- gate oxide
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Abstract
The invention discloses a preparation method for a semiconductor device, which provides a base; a gate oxide is formed on the base; a gate electrode is formed on the gate oxide; a clearance wall insulation layer is formed on the side walls of the gate electrode and the gate oxide; a clearance wall layer is formed on the side wall of the clearance wall insulation layer; ion implantation technology is implemented to form a source/drain electrode; then the clearance wall layer is removed; a high stress layer is formed on the surfaces of the base, the gate electrode and the clearance wall insulation layer; then annealing technique is implemented to form a cover layer on the surface of the high stress layer; and chemical mechanical polishing technique is adopted on the cover layer to expose the high stress layer above the gate electrode.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly semiconductor device and preparation method thereof.
Background technology
The technology of semiconductor integrated circuit chip is made and is utilized the batch process technology, forms a large amount of various types of complex devices on same silicon substrate, and it is connected to each other the electric function of finishing to have.Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, the size of components and parts is more and more littler, because of the high density of device, the influence that the various effects of small size initiation are made the result to semiconductor technology become increasingly conspicuous, this has just proposed more, higher requirement to semiconductor technology.With the film growth is example, and along with device size is more and more littler, service speed is more and more faster, and is also more and more higher to the requirement of device drive current in the circuit.The conductance of channel region is the principal element of decision metal-oxide semiconductor (MOS) (MOS) performance of transistors.Therefore, the channel resistance rate that reduces channel length and reduce to be associated with channel length becomes the important design criteria that is used for improving integrated circuit operation speed.Yet, thereby reducing channel length, lasting reduction transistor size can bring problems, for example the controllability of raceway groove reduces (this is also referred to as short-channel effect).These problems must be overcome, and progressively reduce the resulting advantage of MOS transistor channel length in order to avoid exceedingly balance out.In addition, continuing to reduce critical size (for example, transistorized grid length) also needs the technology that adapts or the more complicated technology of exploitation to be used for compensate for short channel effects, therefore can be more and more difficult from technological angle.
Especially after entering the 65nm process node, the method for traditional raising device drive current has been subjected to many restrictions, and the film that need have stress usually improves the drive current of device.Now confirm, in the device forming process, give birth to the thin layer that just can introduce stress, can reach the purpose of improving device performance: can improve the mobility in hole along the compression of channel direction, can effectively improve the performance of PMOS device at device surface; And can improve the mobility of electronics along the tensile stress of channel direction, can improve the performance of nmos device.This has just proposed extra requirement to thin film growth process.
For the carrier mobility in the raceway groove is had tangible improvement, the thin layer of introducing stress should be formed at the surface near raceway groove.In the existing method; behind the process node that enters below the 65nm; in order to strengthen the carrier mobility of this device; improve device performance; usually the cover layer that is connected with device can be grown to stressor layers with certain stress; the overall performance of semiconductor device can be optimized, the effect of isolation can be played again.
Traditional making has the method for tectal semiconductor device shown in Figure 1A to 1E.
Shown in Figure 1A, substrate 100 is provided, comprise shallow channel isolation area (STI) 101, a plurality of field oxide region (not shown) and be pre-formed in wherein N trap or P trap (not shown).Substrate 101 surfaces have one deck gate oxide 102, are formed with one deck polysilicon layer 103 on the gate oxide 102.Carry out light dope technology, form LDD district 104A and 104B.
Shown in Figure 1B, deposition and etching form clearance wall insulating barrier 105A and 105B on the sidewall of gate oxide 102 and polysilicon layer 103, then difference etching formation gap parietal layer 106A and 106B on the sidewall of clearance wall insulating barrier 105A and 105B.
Shown in Fig. 1 C, carry out ion implantation technology, formation source/ drain electrode 107A and 107B, and carry out annealing process subsequently, with the ion among activation of source/drain electrode 107A and the 107B.
Shown in Fig. 1 D, on the total surface, i.e. substrate 100, polysilicon layer 103 and clearance wall insulating barrier 105A and 105B surface be with CVD method deposition one deck high stress layer 108, can select to have the SiN of tensile stress or compression etc.Then carry out annealing process, stress is retained in source/drain electrode 107A and the 107B zone.
Shown in Fig. 1 E, on high stress layer 108, deposit layer of oxide layer as cover layer 109 with the CVD method, material can be chosen as the SiN with certain stress.
But this traditional tectal method of making has certain limitation.That is,, can not produce enough big saturation current (I even formed cover layer with certain stress
Dsat)Traditional method is to adopt the mode that increases tectal stress to increase saturation current, but in the test that increases cover layer stress, find to cause easily gate-induced drain leakage (GIDL) effect, drain electrode can produce very big leakage current, cause device power consumption to rise, and influence the working life of semiconductor device.
Therefore, need a kind of new method, can effectively solve the big inadequately problem of saturation current, can not cause gate-induced drain leakage effect again,, improve the yields of semiconductor device so that improve the performance of device integral body.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order effectively to solve the big inadequately problem of saturation current, the present invention proposes a kind of manufacture method of semiconductor device, comprises, a substrate is provided; In described substrate, form gate oxide; On described gate oxide, form grid; On the sidewall of described grid and described gate oxide, form the clearance wall insulating barrier; On the sidewall of described clearance wall insulating barrier, form the gap parietal layer; Carry out ion implantation technology and form source/drain electrode; Remove described gap parietal layer; Form one deck high stress layer at described semiconductor device surface; Implement annealing process; Form one deck cover layer on described high stress layer surface; Described cover layer is adopted CMP (Chemical Mechanical Polishing) process, expose the described high stress layer of described grid top.
Preferably, described annealing process is spike annealing or laser annealing.
Preferably, the material of described high stress layer is SiN, SiGe or SiC.
Preferably, described tectal material is SiN, SiGe or SiC.
Preferably, described tectal thickness is 5000～7000 dusts.
Preferably, the material of described clearance wall insulating barrier is silicon nitride or low temperature oxide.
The present invention also provides a kind of semiconductor device, comprises substrate; The gate oxide that forms in the described substrate; The grid that forms on the described gate oxide; The clearance wall insulating barrier that forms on the sidewall of described grid and described gate oxide; Source/drain electrode that ion implantation technology forms; One deck high stress layer in described substrate, described grid and the formation of described clearance wall surface of insulating layer; At one deck cover layer that described high stress layer surface forms, described cover layer does not cover the described high stress layer of described grid top.
Preferably, the material of described high stress layer is SiN, SiGe or SiC.
Preferably, described tectal material is SiN, SiGe or SiC.
Preferably, described tectal thickness is 5000～7000 dusts.
Preferably, the material of described clearance wall insulating barrier is silicon nitride or low temperature oxide.
According to the present invention, can effectively solve the big inadequately problem of saturation current, can not cause gate-induced drain leakage effect again.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 E is the cross-sectional view that traditional making has tectal semiconductor device;
Fig. 2 A to 2G is that making according to the present invention has the cross-sectional view of tectal semiconductor device;
Fig. 3 makes according to the tectal semiconductor device technology flow chart of having of the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention adopts new technology to solve the big inadequately problem of saturation current.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
With reference to Fig. 2 A to Fig. 2 G, the cutaway view according to each step of the embodiment of one aspect of the invention is shown.
Shown in Fig. 2 A, substrate 200 is provided, comprise shallow channel isolation area (STI) 201, a plurality of field oxide region (not shown) and be pre-formed in wherein N trap or P trap (not shown).Have one deck gate oxide 202 in the substrate 200, can be chosen as and utilize oxidation technology temperature in the oxygen steam ambient to form gate oxide 202 down about 800～1000 degrees centigrade.Be formed with grid 203 on the gate oxide 202, material can be but be not limited to polysilicon.The mode that forms grid 203 can adopt the chemical vapor deposition (CVD) method.Carry out light dope technology then, form LDD district 204A and 204B.
Then, shown in Fig. 2 B, deposition and etching form clearance wall insulating barrier 205A and 205B on the sidewall of gate oxide 202 and grid 203, and material can be but be not limited to silicon nitride or low temperature oxide (LTO).The difference etching forms gap parietal layer 206A and 206B on the sidewall of clearance wall insulating barrier 205A and 205B then, and material can be but be not limited to silicon nitride.
Next, shown in Fig. 2 C, carry out ion implantation technology, inject n type foreign ion or p type foreign ion, formation source/ drain electrode 207A and 207B.
Then, shown in Fig. 2 D, coating one deck photoresist layer (not shown) in grid 203 and substrate 200, the photoresist layer (not shown) that has pattern by the formation of technologies such as exposure imaging is in order to remove gap parietal layer 206A and 206B.Removing method can be the wet etching method that adopts phosphoric acid solution.Adopt ashing method to remove photoresist layer.
Next, shown in Fig. 2 E, on the surface of total, promptly at substrate 200, grid 203 and clearance wall insulating barrier 205A and 205B surface deposition one deck high stress layer 208, material can be but be not limited to SiN, SiGe or SiC etc.The stress types that can be had according to the different choice high stress layer 208 of type of device, to nmos device, high stress layer 208 should have tensile stress; For the PMOS device, high stress layer 208 should have compression.Can obtain to have the high stress layer 208 of required stress types according to the adjustment of technological parameter.Then, implement annealing process.Annealing process can adopt spike annealing, carries out under 1000～1100 degrees centigrade, perhaps adopts the method for laser annealing.
Next, shown in Fig. 2 F, on the total surface, promptly deposit one deck cover layer 209 on the surface of high stress layer 208 with the CVD method, its thickness is 5000～7000 dusts, and material can be but be not limited to SiN, SiGe or SiC etc.The stress that can have according to the cover layer 209 that the polarity of device is selected to be deposited need have the cover layer 209 of tensile stress as nmos device, can adopt SiH
4, NH
3And N
2As source gas, form the SiN layer with tensile stress, wherein SiH down at 350～550 degrees centigrade
4Flow is 320～340sccm, NH
3Flow is 3000～3400sccm, N
2Flow is 3800～4200sccm; The PMOS device need have the cover layer 209 of compression, can adopt SiH
4, NH
3And N
2As source gas, form the SiN layer with compression, wherein SiH down at 380～420 degrees centigrade
4Flow be 30～40sccm, NH
3Flow is 70～90sccm, N
2Flow is 8000～9000sccm.Here, sccm is under the standard state, just the flow of 1 atmospheric pressure, 25 degrees centigrade of following per minutes 1 cubic centimetre (1ml/min).
Shown in Fig. 2 G, cover layer 209 is adopted CMP (chemico-mechanical polishing) technology, make its top concordant with the top of high stress layer 208, promptly expose the high stress layer 208 of grid 203 tops.
According to the present invention, the annealing process of source/ drain electrode 207A and 207B is put into forms after the high stress layer 208, original twice annealing technology is become only needs annealing process of enforcement to get final product, simplified production technology, reduce production cost, and avoided when high stress layer 208 is carried out annealing process the potential injury that may cause other structure of semiconductor device.Gap parietal layer 206A and 206B are removed, make that the high stress layer stress effect that 208 pairs of sources/ drain electrode 207A and 207B are applied is more remarkable, improved carrier mobility greatly, increased saturation current.And cover layer 209 adopts materials such as the thicker SiN with stress, SiGe or SiC, increased stress especially to the source/ drain electrode 207A and 207B are applied, further improve the mobility of charge carrier rate, promoted the overall performance of semiconductor device, thereby increased yields.The saturation current of detection manufactured samples according to the present invention is found at V
Tline(linear zone voltage) and V
TsatUnder (saturation region voltage) constant situation, its saturation current has risen to 493 μ m/ μ A from 460 μ m/ μ A, and saturation current has increased greatly, and purpose according to the invention had not only increased saturation current but also do not caused that gate-induced drain reveals effect.
The flow chart of Fig. 3 shows making and makes the semiconductor device technology flow chart according to the employing improvement technology of the embodiment of the invention.In step 301, substrate is provided, comprise shallow channel isolation area, a plurality of field oxide region and be pre-formed in wherein N trap or P trap.Have one deck gate oxide in the substrate, be formed with grid on the gate oxide.In step 302, carry out light dope technology, form the LDD district.In step 303, deposition and etching form the clearance wall insulating barrier on the sidewall of gate oxide and grid, and etching forms the gap parietal layer respectively on the sidewall of clearance wall insulating barrier.In step 304, carry out ion implantation technology, formation source/drain electrode.In step 305, remove the gap parietal layer.In step 306, at surface deposition one deck high stress layer of substrate, grid and clearance wall insulating barrier.In step 307, implement annealing process.In step 308, at surface deposition one deck cover layer of high stress layer.In step 309, cover layer is adopted CMP technology, make its top concordant with the top of high stress layer, promptly expose the high stress layer of grid top.
Can be applicable in the multiple integrated circuit (IC) according to the tectal semiconductor device of having of aforesaid embodiment manufacturing.According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. the manufacture method of a semiconductor device comprises,
One substrate is provided;
In described substrate, form gate oxide;
On described gate oxide, form grid;
On the sidewall of described grid and described gate oxide, form the clearance wall insulating barrier;
On the sidewall of described clearance wall insulating barrier, form the gap parietal layer;
Carry out ion implantation technology and form source/drain electrode;
Remove described gap parietal layer;
Form one deck high stress layer at described semiconductor device surface;
Implement annealing process;
Form one deck cover layer on described high stress layer surface;
Described cover layer is adopted CMP (Chemical Mechanical Polishing) process, expose the described high stress layer of described grid top.
2. the method for claim 1 is characterized in that, described annealing process is spike annealing or laser annealing.
3. the method for claim 1 is characterized in that, the material of described high stress layer is SiN, SiGe or SiC.
4. the method for claim 1 is characterized in that, described tectal material is SiN, SiGe or SiC.
5. as claim 1 or 4 described methods, it is characterized in that described tectal thickness is 5000～7000 dusts.
6. the method for claim 1 is characterized in that, the material of described clearance wall insulating barrier is silicon nitride or low temperature oxide.
7. a semiconductor device comprises,
Substrate;
The gate oxide that forms in the described substrate;
The grid that forms on the described gate oxide;
The clearance wall insulating barrier that forms on the sidewall of described grid and described gate oxide;
Source/drain electrode that ion implantation technology forms;
One deck high stress layer in described substrate, described grid and the formation of described clearance wall surface of insulating layer;
At one deck cover layer that described high stress layer surface forms, described cover layer does not cover the described high stress layer of described grid top.
8. device as claimed in claim 7 is characterized in that, the material of described high stress layer is SiN, SiGe or SiC.
9. device as claimed in claim 7 is characterized in that, described tectal material is SiN, SiGe or SiC.
10. device as claimed in claim 7 is characterized in that, described tectal thickness is 5000～7000 dusts.
11. device as claimed in claim 7 is characterized in that, the material of described clearance wall insulating barrier is silicon nitride or low temperature oxide.
12. an integrated circuit that comprises the semiconductor device of making by the method for claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
13. an electronic equipment that comprises the semiconductor device of making by the method for claim 1, wherein said electronic equipment personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103021849A (en) * | 2011-09-20 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | N-channel metal oxide semiconductor (NMOS) component manufacturing method using stress memorization technology |
| CN103794559A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| CN108581639A (en) * | 2018-03-23 | 2018-09-28 | 上海华虹宏力半导体制造有限公司 | A kind of control method and its control system of CMP process |
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| CN1979786A (en) * | 2005-11-29 | 2007-06-13 | 联华电子股份有限公司 | Method for making strain silicon transistor |
| CN101165862A (en) * | 2006-10-16 | 2008-04-23 | 联华电子股份有限公司 | High pressure stress film and stress silicon metal oxide semiconductor transistor and its manufacture method |
| US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1979786A (en) * | 2005-11-29 | 2007-06-13 | 联华电子股份有限公司 | Method for making strain silicon transistor |
| US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
| CN101165862A (en) * | 2006-10-16 | 2008-04-23 | 联华电子股份有限公司 | High pressure stress film and stress silicon metal oxide semiconductor transistor and its manufacture method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021849A (en) * | 2011-09-20 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | N-channel metal oxide semiconductor (NMOS) component manufacturing method using stress memorization technology |
| CN103021849B (en) * | 2011-09-20 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of nmos device manufacture method adopting stress memory technique |
| CN103794559A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| CN108581639A (en) * | 2018-03-23 | 2018-09-28 | 上海华虹宏力半导体制造有限公司 | A kind of control method and its control system of CMP process |
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