CN103794559A - Semiconductor device and method for preparing same - Google Patents
Semiconductor device and method for preparing same Download PDFInfo
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- CN103794559A CN103794559A CN201210422173.3A CN201210422173A CN103794559A CN 103794559 A CN103794559 A CN 103794559A CN 201210422173 A CN201210422173 A CN 201210422173A CN 103794559 A CN103794559 A CN 103794559A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
The present invention relates to a semiconductor device and a method for preparing the same. The method comprises the steps of providing a semiconductor substrate at least containing a grid structure; forming grooves at the two sides of a grid, carrying out ion implantation at the two sides of the grid before or after forming the grooves, and doping B having a concentration gradient in the substrate at the bottom of each groove; growing a SiGe layer in each groove epitaxially while doping B in situ to form a source-drain area. According to the method of the present invention, source-drain implantation is carried out before the SiGe layer is grown epitaxially, so that the B possessing a certain concentration gradient is formed at the bottom of each groove, and accordingly a contact electric leakage caused by the source-drain communication is avoided. And then, the B is doped in situ while the SiGe layer is grown epitaxially to form the source and the drain, thereby avoiding the source-drain implantation, keeping the pressure stress on a PMOS better, eliminating the stress relaxation, and further improving the performance of the device. Moreover, the whole preparation technology is simpler.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
Along with the sustainable development of integrated circuit technique, on chip, by integrated more devices, chip also will adopt speed faster.Under the propelling of these requirements, the physical dimension of device will constantly be dwindled, and constantly adopt new material, new technology and new manufacturing process in the manufacturing process of chip.The preparation of semiconductor device at present has developed into Nano grade, and the preparation technology of conventional device is ripe gradually simultaneously.
At present semiconductor device in the process of preparation CMOS in order to obtain better performance, conventionally carry out extension e-SiGe at the source-drain area of CMOS and apply compression with the raceway groove place to substrate, PMOS performance is improved, in prior art, generally leak and form depression in PMOS source, then epitaxial growth e-SiGe, but in formation e-SiGe process, there are a lot of challenges at present, for example integrating (integration), defect control, selectivity etc., wherein a maximum problem is in the time forming described depression epitaxial growth, along with the increase of Ge content in the increase of epitaxy layer thickness and epitaxial loayer causes the deformation relaxation (stress relaxation) on source-drain area, particularly when PMOS device size is down to after 32nm rank, deformation relaxation (stress relaxation) will directly cause the reduction of device performance.
In addition; after extension SiGe, conventionally can carry out Implantation; adulterate to obtain higher doping content; in this process, conventionally select the B(Boron of high-energy, low dosage) its source is being leaked and adulterated; to form doping hangover (doping tail) profile; reduce the electric leakage of intersection, but leak after carrying out Implantation and conventionally can cause device after annealing, to produce deformation relaxation in the source of the SiGe of PMOS, cause the reduction of device performance.In prior art, also can its source leaked and carried out B(Boron by carrying out in epitaxial growth SiGe) doping, and by adjusting gas flow and other parameters, to reach enough doping contents, but during by in-situ doped B, in SiGe layer, can realize doping, but described SiGe layer and described substrate intersection can not form the B doping with concentration gradient, and therefore SiGe layer and described substrate intersection cause very large leakage current, also can reduce the performance of device.
Therefore, in the time that leak in prior art intermediate ion method for implanting formation source, relaxation is leaked in the source of causing can not eliminate Implantation time, if adopt the in-situ doped larger leakage current that can cause, all there is problem separately in the method that forms at present epitaxy Si Ge layer, affect the performance of device, need to improve to eliminate described impact to prior art.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to address the above problem, the invention provides a kind of preparation method of semiconductor device, comprising:
Semiconductor substrate is provided, at least comprises grid structure;
At described grid both sides connected in star, before or after forming described groove, carry out Implantation in described grid both sides, there is the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Epitaxial growth SiGe layer in described groove, in-situ doped B when epitaxial growth SiGe layer, to form source-drain area.
As preferably, described Semiconductor substrate comprises the NMOS grid structure that is positioned at nmos area and the PMOS grid structure that is positioned at PMOS district;
On described substrate, form the masking material bed of material;
On described nmos area, form mask layer, form groove in described PMOS grid both sides, before or after forming described groove, carry out Implantation in described PMOS grid both sides, there is the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Epitaxial growth SiGe layer in described groove, in-situ doped B when epitaxial growth SiGe layer, to form PMOS source-drain area;
In described PMOS district, form mask layer, the masking material bed of material of described nmos area is carried out to etching, to form skew sidewall on the sidewall at described NMOS grid structure;
Source is carried out in described nmos area and leak injection, to form NMOS source-drain area.
As preferably, on described nmos area, form after mask layer, described PMOS district is carried out to Implantation, then described PMOS district is carried out to etching, to form groove.
As preferably, the ion of described Implantation is B or BF
2.
As preferably, when described injection ion is B, the energy of described Implantation is 5 ~ 15kev.
As preferably, when described injection ion is BF2, the energy of described Implantation is 15 ~ 60kev.
As preferably, the concentration of described Implantation is 1E13-1E14 atom/cm
3.
As preferably, on described nmos area, form after mask layer, described PMOS district is carried out to etching, to form groove, then in described groove, carry out Implantation.
As preferably, the ion of described Implantation is B or BF
2.
As preferably, when described injection ion is B, the energy of described Implantation is 200 ~ 5kev.
As preferably, when described injection ion is BF2, the energy of described Implantation is 500ev ~ 15kev.
As preferably, the concentration of described Implantation is 5E11 ~ 1E13 atom/cm
3.
As preferably, in described groove, before epitaxial growth SiGe layer, carry out an annealing steps.
As preferably, described in be annealed into spike annealing or Millisecond annealing.
As preferably, the peak temperature of described spike annealing is 900 ~ 1100 ℃.
As preferably, the peak position residence time of described spike annealing is 0.8 ~ 1.5 second.
As preferably, described Millisecond annealing temperature is 1100 ~ 1300 ℃.
As preferably, the time of staying of described Millisecond annealing is 0.2 ~ 1 millisecond.
As preferably, described SiGe layer is one or more layers composite laminate.
As preferably, in described SiGe layer, the content of Ge is 10 ~ 50%.
As preferably, the concentration of the B adulterating in described SiGe layer is 1E18 ~ 1E21 atom/cm
3.
As preferably, described groove is Σ connected in star.
As preferably, the described masking material bed of material is silica and/or silicon nitride.
As preferably, described method is further comprising the steps of:
Described nmos area is carried out source leak inject before, on the sidewall of described NMOS grid structure and PMOS grid structure, form clearance wall.
As preferably, on described substrate, form the masking material bed of material, then on NMOS, form patterning photoresist, the masking material bed of material forms skew sidewall on the sidewall of described PMOS grid structure described in etching.
The present invention also provides a kind of semiconductor device, and described device comprises:
Grid structure, is positioned in Semiconductor substrate;
The in-situ doped SiGe layer of B, is positioned at the both sides of described grid structure, to form source-drain area;
Ion implanted region, is arranged in the substrate below described SiGe layer, has the B of concentration gradient.
As preferably, in described SiGe layer, the content of Ge is 10 ~ 50%.
As preferably, the concentration of the B adulterating in described SiGe layer is 1E18 ~ 1E21 atom/cm
3.
As preferably, described SiGe layer is one or more layers composite laminate.
As preferably, the ion of described ion implanted region is B or BF2.
As preferably, the concentration of described ion implanted region intermediate ion is 5E11 ~ 1E14 atom/cm
3.
The invention provides a kind of preparation method of semiconductor device, in the present invention in order to reduce PMOS relaxation effect (the stress relaxation) and contact electric leakage, in the time forming source-drain area, no longer the step of injecting is leaked in execution source, leak injection but carried out source before epitaxial growth SiGe layer, form the B with finite concentration gradient with the bottom at described groove, be communicated with thereby avoided source to leak the contact electric leakage causing, then in-situ doped B in extension, leak with formation source, having avoided source to leak injects, better keep the compression on PMOS, eliminate relaxation effect (the stress relaxation), further improve the performance of device, and whole preparation technology is simpler.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1-7 are for preparing the process generalized section of described semiconductor device in the present invention;
Fig. 8 is the process chart of preparing described semiconductor device in the present invention;
Fig. 9 is the doping ion distribution schematic diagram of the semiconductor device for preparing in the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that semiconductor device of the present invention and preparation method thereof to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
As shown in Figure 1, first Semiconductor substrate 201 is provided, and described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferred silicon-on-insulator (SOI) in the present invention, described silicon-on-insulator (SOI) is followed successively by support substrates, oxide insulating layer and semiconductor material layer from the bottom up, but is not limited to above-mentioned example.
In described Semiconductor substrate, form isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure 204 or selective oxidation silicon (LOCOS) isolation structure.In described Semiconductor substrate, be also formed with the channel layer of various traps (well) structure and substrate surface.
Described substrate is divided into territory, nmos area and PMOS region by described isolation structure in the present invention, then on described substrate, forms grid structure.
Particularly, on described substrate, form PMOS grid structure 202 and NMOS grid structure 302, described formation method for grid structure for to form gate dielectric on described substrate, and described gate dielectric can be silica (SiO2) or silicon oxynitride (SiON).Can adopt those skilled in the art's oxidation technology known such as furnace oxidation, rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) etc. to form the gate dielectric layer of silica material.Then deposition of gate material layer and oxide skin(coating), the sandwich construction that wherein said gate material layers comprises semi-conducting material, for example silicon, germanium, metal or its combination.Described gate dielectric layer, gate material layers and oxide skin(coating) are carried out to etching and form grid structure.
Then on described substrate, deposit the masking material bed of material 203, to cover described NMOS grid and PMOS grid, the wherein said masking material bed of material 203 is hard mask layer, preferential oxidation silicon and/or silicon nitride, optimize execution mode as one of the present invention, the described masking material bed of material is that silica, silicon nitride form jointly, and concrete technology is: in Semiconductor substrate, form the first silicon oxide layer, the first silicon nitride layer.
Then form light dope source electrode/drain electrode (LDD) in the substrate of grid structure either side.The method of described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will form, and the device forming is nmos device, and the foreign ion mixing in LDD injection technology is a kind of or combination in phosphorus, arsenic, antimony, bismuth; If the device forming is PMOS device, the foreign ion injecting is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
With reference to Fig. 4, on described nmos area, form mask layer, form groove in described PMOS grid both sides, before or after forming described groove, carry out the step of Implantation, there is the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Respectively two kinds of situations are described in conjunction with Fig. 2-4 respectively below:
With reference to Fig. 2, first form groove and then Implantation, particularly, first on NMOS, form patterning photoresist, the then masking material bed of material described in etching forms skew sidewall on the sidewall of described PMOS grid structure;
Then form groove in the both sides of described PMOS grid forming after described PMOS grid skew sidewall, be preferably formed in the present invention " ∑ " shape depression, in this step, can select PMOS source-drain area described in dry etching, in described dry etching, can select CF
4, CHF
3, add in addition N
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
In this step, the ion of described Implantation is B or BF
2, as preferably, in the time that described injection ion is B, the energy of described Implantation is 200 ~ 5kev, when described injection ion is BF
2time, the energy of described Implantation is 500ev ~ 15kev, is 5E11 ~ 1E13 atom/cm in the concentration of Implantation described in this step
3.Formed doping and had the region 20 of the B of concentration gradient by the described bottom that is infused in groove.Be positioned at the described source that will the form face that leaks down in this region, therefore avoided the connection of source between leaking, can eliminate pick-up current, improve device performance.
With reference to Fig. 3, first Implantation forms groove again, particularly, on described nmos area, form after mask layer, carry out Implantation in described PMOS district, then described PMOS district is carried out to etching, to form groove, be B or BF2 at the ion of Implantation described in this step, in the time that described injection ion is B, the energy of described Implantation is 5 ~ 15kev, when described injection ion is BF
2time, the energy of described Implantation is 15 ~ 60kev, is 1E13-1E14 atom/cm in the concentration of Implantation described in this step
3.Then described in etching, PMOS district carries out etching, and to form groove, engraving method particularly can be with reference to first method.
Continue with reference to Fig. 4, according to first or the second way carry out an annealing steps after forming the substrate of doping B, eliminate to eliminate infringement on silicon chip, minority carrier lifetime and mobility can obtain recovery in various degree, impurity also can obtain a certain proportion of activation, improves device efficiency.
Be annealed into spike annealing or Millisecond annealing described in this step, wherein, the peak temperature of described spike annealing is 900 ~ 1100 ℃, is preferably 950 ~ 1050 ℃, and the peak position residence time of described spike annealing is 0.8 ~ 1.5 second, is preferably 1.0 ~ 1.2 seconds; In the time selecting Millisecond annealing, described Millisecond annealing temperature is 1100 ~ 1300 ℃, is preferably 1150 ~ 1250 ℃, and the time of staying of described Millisecond annealing is 0.2 ~ 1 millisecond, is preferably 0.5 ~ 0.8 millisecond.
With reference to Fig. 5, epitaxial growth SiGe layer in described groove, in-situ doped B when epitaxial growth SiGe layer, to form PMOS source-drain area;
Particularly, epitaxial growth e-SiGe layer in the depression forming in described PMOS region, the compression of leaking to increase PMOS source, in-situ doped B when epitaxial growth SiGe layer, in the described SiGe layer forming in this step, the content of Ge is 10 ~ 50%, is preferably 20 ~ 30%; The concentration of the B adulterating in described SiGe layer is 1E18 ~ 1E21 atom/cm3.Described extension can be selected the one in reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, molecular beam epitaxy in the present invention.
As preferably, the lamination that described e-SiGe layer is one or more layers formation, the lamination that more preferably multilayer forms in the present invention, its can be included as with groove in multi-layer bottom material layer, and be positioned at the top layer of material in described bottom material layer, described top layer of material can be SiGe, Si or containing one or more in the Si layer of B, the thickness of its top layer of material is more preferably greater than the degree of depth of described raceway groove.
Forming after described SiGe layer, can also further on described SiGe layer, form block layer, described block layer is SiGe or Si, the deposition process of described block layer can be chemical vapour deposition technique (CVD), as the one in low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), this material layer of patterning after the described material layer of deposition formation, to form described block layer.Then remove the mask layer on described nmos area.
With reference to Fig. 6, in described PMOS district, form mask layer, the masking material bed of material of described nmos area is etched with and on the sidewall of described NMOS grid structure, forms skew sidewall, then on NMOS and PMOS grid, form clearance wall, and source leakage is carried out in described nmos area and inject, to form NMOS source-drain area;
First; in described PMOS grid and the leakage of source, both sides, form mask layer; for example photoresist layer; to protect the source-drain area of described PMOS; described in etching, the masking material bed of material forms skew sidewall on described NMOS grid structure; then remove described mask layer; on described NMOS grid and described PMOS grid, form clearance wall; then in described PMOS district, again form mask layer and separately described NMOS is carried out to source and leak injection; the ionic type of injection is leaked in wherein said source and the concentration of doping all can be selected this area usual range, does not repeat them here.
With reference to Fig. 7, remove described mask layer, carry out thermal anneal step.
Particularly, carry out after described thermal anneal step, the infringement on silicon chip can be eliminated, minority carrier lifetime and mobility can obtain recovery in various degree, and impurity also can obtain a certain proportion of activation, therefore can improve device efficiency.
Described annealing steps is generally that described substrate is placed under the protection of high vacuum or high-purity gas; being heated to certain temperature heat-treats; be preferably nitrogen or inert gas at high-purity gas of the present invention; the temperature of described thermal anneal step is 800-1200 ℃, and the described thermal anneal step time is 1-200s.
As further preferred, can select in the present invention rapid thermal annealing, particularly, can select the one in following several mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent wideband light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.Those skilled in the art can select as required, are also not limited to examples cited.
In addition, the present invention also provides a kind of semiconductor device, it is characterized in that, described device comprises:
Grid structure, is positioned in Semiconductor substrate;
The in-situ doped SiGe layer of B, is positioned at the both sides of described grid structure, to form source-drain area;
Ion implanted region, is arranged in the substrate below described SiGe layer, has the B of concentration gradient.
Wherein, in described SiGe layer, the content of Ge is 10 ~ 50%.
Particularly, described in device of the present invention, device as shown in Figure 7, in described source-drain area, comprise the SiGe layer of B in-situ doped, avoid source to leak the step of injecting, therefore can better guarantee the compression that leak in source, as shown in Figure 9, at more shallow depth, in SiGe layer doped with B, and at described SiGe layer and described substrate intersection, in the substrate under intersection, also there is certain density B, and the concentration of described B just there is certain gradient, as shown in dotted line right side, therefore avoid source to leak and be communicated with the contact electric leakage causing.
The invention provides a kind of semiconductor device and preparation method thereof, in the present invention in order to reduce PMOS relaxation effect (the stress relaxation) and contact electric leakage, in the time forming source-drain area, no longer the step of injecting is leaked in execution source, leak injection but carried out source before epitaxial growth SiGe layer, form the B with finite concentration gradient with the bottom at described groove, be communicated with thereby avoided source to leak the contact electric leakage causing, then in-situ doped B in extension, leak with formation source, having avoided source to leak injects, better keep the compression on PMOS, eliminate relaxation effect (the stress relaxation), further improve the performance of device, and whole preparation technology is simpler.
With reference to Fig. 8, wherein show the method flow diagram that the present invention prepares two epitaxial loayers, for schematically illustrating the flow process of whole manufacturing process.
Described in step 201, Semiconductor substrate comprises the NMOS grid structure that is positioned at nmos area and the PMOS grid structure that is positioned at PMOS district;
Step 202 forms the masking material bed of material on described substrate;
Step 203 forms mask layer on described nmos area, forms groove in described PMOS grid both sides, before or after forming described groove, carries out Implantation in described PMOS grid both sides, has the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Step 204 is epitaxial growth SiGe layer in described groove, and in-situ doped B when epitaxial growth SiGe layer, to form PMOS source-drain area;
Step 205 forms mask layer in described PMOS district, and the masking material bed of material of described nmos area is carried out to etching, to form skew sidewall on the sidewall at described NMOS grid structure;
Step 206 is carried out source to described nmos area and is leaked injection, to form NMOS source-drain area.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (31)
1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided, at least comprises grid structure;
At described grid both sides connected in star, before or after forming described groove, carry out Implantation in described grid both sides, there is the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Epitaxial growth SiGe layer in described groove, in-situ doped B when epitaxial growth SiGe layer, to form source-drain area.
2. method according to claim 1, is characterized in that, described Semiconductor substrate comprises the NMOS grid structure that is positioned at nmos area and the PMOS grid structure that is positioned at PMOS district;
On described substrate, form the masking material bed of material;
On described nmos area, form mask layer, form groove in described PMOS grid both sides, before or after forming described groove, carry out Implantation in described PMOS grid both sides, there is the B of concentration gradient with doping in the substrate of described bottom portion of groove;
Epitaxial growth SiGe layer in described groove, in-situ doped B when epitaxial growth SiGe layer, to form PMOS source-drain area;
In described PMOS district, form mask layer, the masking material bed of material of described nmos area is carried out to etching, to form skew sidewall on the sidewall at described NMOS grid structure;
Source is carried out in described nmos area and leak injection, to form NMOS source-drain area.
3. method according to claim 2, is characterized in that, on described nmos area, forms after mask layer, and described PMOS district is carried out to Implantation, then described PMOS district is carried out to etching, to form groove.
4. method according to claim 3, is characterized in that, the ion of described Implantation is B or BF
2.
5. method according to claim 4, is characterized in that, when described injection ion is B, the energy of described Implantation is 5 ~ 15kev.
6. method according to claim 4, is characterized in that, described injection ion is BF
2time, the energy of described Implantation is 15 ~ 60kev.
7. according to the method described in claim 3 or 4, it is characterized in that, the concentration of described Implantation is 1E13-1E14 atom/cm
3.
8. method according to claim 2, is characterized in that, on described nmos area, forms after mask layer, and described PMOS district is carried out to etching, to form groove, then in described groove, carries out Implantation.
9. method according to claim 8, is characterized in that, the ion of described Implantation is B or BF
2.
10. method according to claim 9, is characterized in that, when described injection ion is B, the energy of described Implantation is 200 ~ 5kev.
11. methods according to claim 9, is characterized in that, described injection ion is BF
2time, the energy of described Implantation is 500ev ~ 15kev.
12. methods according to claim 8 or claim 9, is characterized in that, the concentration of described Implantation is 5E11 ~ 1E13 atom/cm
3.
13. methods according to claim 1 and 2, is characterized in that, in described groove, before epitaxial growth SiGe layer, carry out an annealing steps.
14. methods according to claim 13, is characterized in that, described in be annealed into spike annealing or Millisecond annealing.
15. methods according to claim 14, is characterized in that, the peak temperature of described spike annealing is 900 ~ 1100 ℃.
16. methods according to claim 14, is characterized in that, the peak position residence time of described spike annealing is 0.8 ~ 1.5 second.
17. methods according to claim 14, is characterized in that, described Millisecond annealing temperature is 1100 ~ 1300 ℃.
18. methods according to claim 14, is characterized in that, the time of staying of described Millisecond annealing is 0.2 ~ 1 millisecond.
19. methods according to claim 1 and 2, is characterized in that, described SiGe layer is one or more layers composite laminate.
20. methods according to claim 1 and 2, is characterized in that, in described SiGe layer, the content of Ge is 10 ~ 50%.
21. methods according to claim 1 and 2, is characterized in that, the concentration of the B adulterating in described SiGe layer is 1E18 ~ 1E21 atom/cm
3.
22. methods according to claim 1 and 2, is characterized in that, described groove is Σ connected in star.
23. methods according to claim 2, is characterized in that, the described masking material bed of material is silica and/or silicon nitride.
24. methods according to claim 2, is characterized in that, described method is further comprising the steps of:
Described nmos area is carried out source leak inject before, on the sidewall of described NMOS grid structure and PMOS grid structure, form clearance wall.
25. methods according to claim 2, is characterized in that, form the masking material bed of material on described substrate, then on NMOS, form patterning photoresist, and the masking material bed of material forms skew sidewall on the sidewall of described PMOS grid structure described in etching.
26. 1 kinds of semiconductor device, is characterized in that, described device comprises:
Grid structure, is positioned in Semiconductor substrate;
The in-situ doped SiGe layer of B, is positioned at the both sides of described grid structure, to form source-drain area;
Ion implanted region, is arranged in the substrate below described SiGe layer, has the B of concentration gradient.
27. devices according to claim 26, is characterized in that, in described SiGe layer, the content of Ge is 10 ~ 50%.
28. devices according to claim 26, is characterized in that, the concentration of the B adulterating in described SiGe layer is 1E18 ~ 1E21 atom/cm
3.
29. devices according to claim 26, is characterized in that, described SiGe layer is one or more layers composite laminate.
30. devices according to claim 26, is characterized in that, the ion of described ion implanted region is B or BF
2.
31. devices according to claim 26, is characterized in that, the concentration of described ion implanted region intermediate ion is 5E11 ~ 1E14 atom/cm
3.
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