CN101081488A - Online control method of mixed type chemical mechanical buffing technics - Google Patents
Online control method of mixed type chemical mechanical buffing technics Download PDFInfo
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- CN101081488A CN101081488A CN 200610092381 CN200610092381A CN101081488A CN 101081488 A CN101081488 A CN 101081488A CN 200610092381 CN200610092381 CN 200610092381 CN 200610092381 A CN200610092381 A CN 200610092381A CN 101081488 A CN101081488 A CN 101081488A
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Abstract
The on-line control method for mixed chemical and mechanical polishing process includes the following steps: providing one mixed chemical and mechanical polishing system including one first polishing platform and one second polishing platform with grinding and polishing pads of different types; providing one batch of chips to be polished, with the chips possessing patterns, one first dielectric layer deposited on the pattern treat and one second dielectric layer; polishing at least 3 sample chips in the first polishing platform, on-line measuring the residual dielectric layer thickness of the polished samples, establishing one linear polishing rate table; and polishing the rest chips in the first polishing platform based on the polishing rate table to polish the first dielectric layer to the target thickness.
Description
Technical field
The present invention relates to chemically mechanical polishing (chemical mechanical polishing, CMP) technology, particularly relate to control method on the line of a kind of hybrid (hybrid) CMP process, two kinds of dissimilar grinding and polishing pad have wherein been used, especially can be applicable to channel insulation (shallow trench isolation, STI) in the technology, dielectric layer on the wafer is polished to desired target thickness exactly, to avoid excessive polishing (over-polish), dish polishing (dishing) phenomenon, the consume of fast grinding belt (fast-band) phenomenon or silicon nitride bed course (pad nitride), improve the reliability of STI technology by this, increase the equipment output capacity simultaneously and reduce production costs.
Background technology
In semiconductor technology, chemically mechanical polishing (chemical mechanical polishing, CMP) technology is one of most important technology of comprehensive planarization that provides at present by super large-scale integration, be widely used in many different field of semiconductor technology, for example, the channel insulation of integrated circuit technology leading portion (shallow trench isolation, STI) technology, and the metal interconnecting technology of integrated circuit technology back segment.
In making the process of integrated circuit, inevitably need be on a wafer stacked structure of precipitation number layer different materials.Chemical Mechanical Polishing Technique can be used to remove equably the aimed thin film layer (target thin film) of irregular surface on the wafer (topographical), make wafer after handling, can have the surface of smooth and regular (regular and planar) through CMP process, with guarantee in follow-up gold-tinted technology the depth of focus (depth of focus, DOF).And the thickness of the aimed thin film layer that removes in order to control, the CMP process terminal point must be detected and promptly be determined accurately, to stop CMP process immediately.
In brief, chemical Mechanical Polishing Technique is that a polished wafer face is pressed on the grinding and polishing pad (polishing pad) down, and this polished wafer is fixed by a discoid mechanism that is called rubbing head (carrier head).In the polishing stage, rubbing head drives polished wafer and rotates with a fixed rotating shaft, and grinding and polishing pad is then with another rotating shaft rotation, is able to the dielectric layer that wafer surface is to be removed by chemistry or mechanical system then or metal level polishes.
Generally speaking, for fear of excessive polishing, the control of the aimed thin film layer thickness of CMP process mainly is dependent on a polishing stop layer (stop layer) that is arranged at aimed thin film layer below and is judged whether to stop CMP process.The polishing speed of polishing stop layer (removal rate) needs little aimed thin film layer thereon usually, and in other words, the polished speed of target polished layer needs the polishing stop layer greater than target polished layer below.Yet, sometimes in practical application, the aimed thin film layer that part is carried out CMP process does not have polishing stop layer, therefore, can't determine the CMP process terminal point by polishing stop layer, under this situation,, then must deposit (re-deposition) technology again and again if produce the situation of excessive polishing, with on the aimed thin film layer after the chemically mechanical polishing again sedimentary facies with thin layer, mat makes the thickness of aimed thin film layer reach pre-provisioning request.
As previously mentioned, in the STI technology that chemical Mechanical Polishing Technique can be applied at leading portion.Because sti structure is used for electrical isolation and is produced on transistor unit and transistor drain or source region etc. on the wafer, so its importance is well imagined.So-called STI technology normally forms silica bed course and silicon nitride bed course earlier on wafer surface, in silicon nitride bed course and wafer, etch groove with photoetching and etch process then, deposit a silica dielectric layer then in groove and on the wafer surface comprehensively, then again with CMP process polish outside groove, silica dielectric layer above the silicon nitride bed course, so promptly form sti structure.Wherein, the silicon nitride bed course is except can be used as the etch hard mask when the etched trench, simultaneously also subsequently in CMP process, play the part of the role of polishing stop layer.In CMP process,, all can require to make the consume of silicon nitride bed course few more good more on the technology for avoiding undermining the material layer or the element of below.
Hence one can see that, and chemical Mechanical Polishing Technique has low cost, high production ability and advantages such as high uniformity and efficient.Yet chemical Mechanical Polishing Technique also has its shortcoming, and for example, in when polishing, silica layer is to the selectivity deficiency of silicon nitride layer, thereby causes the directional polish or the excessive polishing phenomenon of silica layer.Past can utilize extra step to compensate it in order to address these problems, and for example, utilizes so-called anti-phase photomask or contrary mask (reverse mask).
The existing recently a kind of direct polishing method that develops out at STI technology, adopt so-called mixed type chemical mechanical polishing process, use two kinds of dissimilar grinding and polishing pad, for example comprise high selectivity (high-selectivity-slurry, HSS) grinding and polishing pad and fixedly abrasive grains (fixed-abrasive, FA) grinding and polishing pad, advantage be in conjunction with the HSS grinding and polishing pad for the high selectivity that trench fill material had, and the FA grinding and polishing pad high evenness polishing ability that can provide.In this mixed type chemical mechanical polishing process, wafer is sent on first polished land earlier and utilizes the HSS grinding and polishing pad to carry out grinding and polishing, and that wherein uses on the HSS grinding and polishing pad normally contains ceria (CeO
2) the high selectivity polishing fluid.After dielectric layer on the wafer surface is polished to a target thickness, wafer is delivered on second polished land again, utilized the FA grinding and polishing pad to carry out grinding and polishing, remove the dielectric layer of remaining thickness.
In aforesaid mixed type chemical mechanical polishing process, when wafer enters second polished land, and utilize the FA grinding and polishing pad to carry out before the grinding and polishing, must advance preceding thickness (incoming oxide thickness) by the strict silica layer of controlling on the wafer surface.The polishing as 12 cun wafers was even more important for the wafer of large-size in the control of thickness before silica layer advanced, this is because so-called " fast grinding belt (fast-band) phenomenon " can cause when the technology enough and to spare reduction of wafer when utilizing the FA grinding and polishing pad to carry out grinding and polishing, make if polishing time one elongates slightly, promptly cause silicon nitride bed course consume (usually fast grinding belt appears at wafer belt-like zone on every side), but if polishing time is short slightly, promptly cause on wafer, staying silica residue (usually in non-fast grinding belt zone, for example near the wafer centre position).
When wafer utilizes the HSS grinding and polishing pad to carry out grinding and polishing, past is that thickness can just drop on the polishing impact point before adopting temporal mode (timemode) that silica layer on the wafer is advanced, the length of its polishing time is to judge according to the blank polishing speed table (blanket removal rate table) that produces in advance, this blank polishing speed table is to utilize the multi-disc blank wafer, cover on it with polished wafer on identical dielectric layer, polish on the HSS grinding and polishing pad with different polishing times respectively, and the measurement of medium thickness is resulting after polishing in regular turn.Yet the shortcoming of this practice is the blank polishing speed table that utilizes the blank wafer made to come out, it is not a fixed value at the resultant polishing speed for the silica dielectric layer of HSS grinding and polishing pad, as shown in Figure 1, can find (H1 and H2 represent different HSS grinding and polishing pad gained results) from polishing thickness to the mapping of polishing time, different polishing times has different polishing speeds, therefore if judge polishing time, produce inaccurate result most probably according to this blank polishing speed table.
From the above, one of ultimate challenge that existing skill mixed type chemical mechanical polishing technology is faced when being applied to STI technology is a polishing time how to control the HSS grinding and polishing pad, thickness can just drop on the polishing impact point before silica layer on the wafer was advanced, and the blank polishing speed table that utilizes the blank wafer made to come out in the past is obviously accurate inadequately, cause the reduction of technology enough and to spare and product easily, and still have the space of further improvement.
Summary of the invention
Main purpose of the present invention i.e. control method on the line that a kind of mixed type chemical mechanical polishing process is provided, two kinds of dissimilar grinding and polishing pad have wherein been used, especially can be applicable in channel insulation (STI) technology, dielectric layer on the wafer is polished to desired target thickness exactly, to avoid the consume of excessive polishing, dish polishing phenomenon, fast grinding belt phenomenon or silicon nitride bed course, improve the reliability of STI technology by this, increase the equipment output capacity simultaneously and reduce production costs.
According to a preferred embodiment of the invention, the invention provides control method on a kind of line of mixed type chemical mechanical polishing process, at first, one mixed type chemical mechanical polishing system is provided, comprise at least one first polished land and one second polished land, wherein be respectively equipped with dissimilar grinding and polishing pad on this first polished land and this second polished land.Then, provide one batch polished product wafer, wherein respectively be formed with pattern structure all on this polished product wafer, and one first dielectric layer deposition is on this pattern structure and one second dielectric layer.At least 3 in advance product wafer in the polished product wafer of this batch of polishing on this first polished land in regular turn then, remove respectively and respectively be somebody's turn to do this first dielectric layer of different-thickness above the product wafer in advance, then carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness to polishing time at the grinding and polishing pad on this first polished land, set up the polishing speed table of a linearity, then, according to being somebody's turn to do this polishing speed table that the product wafer of going ahead of the rest is set up, the product wafer that is left in this batch of polishing on this first polished land is controlled at a predetermined target thickness with this first medium thickness polishing on remaining respectively this product wafer in regular turn.
According to another preferred embodiment of the invention, the invention provides control method on a kind of line of mixed type chemical mechanical polishing process, comprise the steps: to provide a mixed type chemical mechanical polishing system, comprise at least one first polished land and one second polished land, wherein be respectively equipped with a high selectivity (high-selectivity slurry on this first polished land and this second polished land, HSS) the fixing abrasive grains (fixed-abrasive of grinding and polishing pad and, FA) grinding and polishing pad, one batch polished product wafer is provided, wherein respectively be formed with pattern structure all on this polished product wafer, and one first dielectric layer deposition on this pattern structure and one second dielectric layer, in regular turn on this first polished land, utilize this HSS grinding and polishing pad to polish the product wafer in advance of 3-8 sheet in the polished product wafer of this batch, remove respectively and respectively be somebody's turn to do this first dielectric layer of different-thickness above the product wafer in advance, carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness to polishing time at this HSS grinding and polishing pad on this first polished land, set up the polishing speed table of a linearity, and according to being somebody's turn to do this polishing speed table that the product wafer of going ahead of the rest is set up, in regular turn on this first polished land, utilize this HSS grinding and polishing pad to polish product wafer remaining in this batch, this first medium thickness polishing on remaining respectively this product wafer is controlled at a predetermined target thickness.
According to another preferred embodiment of the invention, the invention provides control method on a kind of line of mixed type chemical mechanical polishing process, comprise the steps: to provide a mixed type chemical mechanical polishing system, comprise at least one first polished land and one second polished land, wherein be respectively equipped with dissimilar grinding and polishing pad on this first polished land and this second polished land, one batch polished product wafer is provided, wherein respectively be formed with pattern structure all on this polished product wafer, and one first dielectric layer deposition on this pattern structure and one second dielectric layer, the product wafer in advance of at least 3 in the polished product wafer of this batch of polishing on this first polished land is removed respectively this first dielectric layer of different-thickness above the product wafer in advance respectively in regular turn; Carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness to polishing time at the grinding and polishing pad on this first polished land, set up one first polishing speed table, on this second polished land, polish this product wafer in advance of at least 3 in regular turn, remove respectively and respectively be somebody's turn to do this first dielectric layer of different-thickness above the product wafer in advance, carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness to polishing time at the grinding and polishing pad on this second polished land, set up one second polishing speed table, according to being somebody's turn to do this first polishing speed table that the product wafer of going ahead of the rest is set up, on this first polished land, polish product wafer remaining in this batch in regular turn, this first medium thickness polishing on remaining respectively this product wafer is controlled at a predetermined target thickness, and according to being somebody's turn to do this second polishing speed table that the product wafer of going ahead of the rest is set up, the product wafer that is left in this batch of polishing on this second polished land is removed this remaining first medium thickness polishing in regular turn.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and explanation usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the blank polishing speed table that utilizes the blank wafer made to come out, and it is not a fixed value at the resultant polishing speed for the silica dielectric layer of HSS grinding and polishing pad;
Fig. 2 to Fig. 4 illustrates is the generalized section that mixed type chemical mechanical polishing system that preferred embodiment of the present invention utilization has three polished land carries out the STI CMP process;
What Fig. 5 illustrated is according to the schematic flow sheet of controlling the method for target medium thickness in the preferred embodiment of the present invention mixed type chemical mechanical polishing process;
What Fig. 6 illustrated is to utilize 3 to 8 flake products wafers after finishing polishing on first polished land in advance, carry out the measurement of residue medium thickness on each wafer on the direct-on-line, constitute the mapping of polishing thickness at the HSS grinding and polishing pad, the linear polishing speed table of setting up to polishing time (removal amount vs.polish time);
What Fig. 7 illustrated is the schematic flow sheet of controlling the method for target medium thickness according to the present invention in another preferred embodiment mixed type chemical mechanical polishing process.
The simple symbol explanation
100 semiconductor substrates, 110 semiconductor layers
115 silica bed courses, 120 silicon nitride bed courses
130 dielectric layers, 135 insulating groove structures
140 irregular height surfaces 145 exceed the thickness part
150 dielectric layers surface, 160 channel insulation structures
The specific embodiment
The present invention is relevant for control method on the line of a kind of hybrid (hybrid) CMP process, two kinds of dissimilar grinding and polishing pad have wherein been used, especially can be applicable in channel insulation (STI) technology, dielectric layer on the wafer is polished to desired target thickness exactly, to avoid the consume of excessive polishing (over-polish), dish polishing (dishing) phenomenon, fast grinding belt (fast-band) phenomenon or silicon nitride bed course, improve the reliability of STI technology by this, increase the equipment output capacity simultaneously and reduce production costs.It is minimum that chemically mechanical polishing control method of the present invention can guarantee that the defective of wafer surface is reduced to.
Below in described the preferred embodiments of the present invention employed chemical-mechanical polisher can be to be equipped with two polished land or three polished land persons, do not limit.For instance, employed chemical-mechanical polisher can be the Reflexion that US business Applied Materials is produced in the preferred embodiment
TMPolishing system, Mirra
TMPolishing system or Mirra
TMMesa
TMPolishing system or the like.
Below in the explanation, so-called mixed type chemical mechanical polishing system general reference is equipped with two kinds of dissimilar polishing pads in the chemical-mechanical polishing mathing platform, for example, high selectivity (high-selectivity-slurry, HSS) grinding and polishing pad and fixedly abrasive grains (fixed-abrasive, FA) grinding and polishing pad, it is separately fixed on former and later two polished land of chemical-mechanical polishing mathing platform.
The inventive method can be applied in the situation that has the two layers of dielectric layer on the polished wafer at least, and for example nitrogenize is dielectric layer and silica dielectric layer, and wherein one dielectric layer is to utilize the FA grinding and polishing pad to carry out grinding and polishing to handle at least.The inventive method can for instance, can be carried out a polishing step with full depth that removes aforementioned dielectric layer or segment thickness, utilizes the FA grinding and polishing pad to remove the unevenness place of wafer surface, does not perhaps polish clean dielectric layer residue.
Below in the explanation, the irregular surface of wafer may comprise any protrusion that is formed on the dielectric layer or the structure of depression, for instance, this irregular surface may be because the characteristic of high density plasma CVD makes so, cause the silica layer that is deposited to have the wedge angle relief fabric that protrudes at pattern comparatively dense place, above other more smooth zone, and these wedge angle relief fabrics also can touch with polishing pad earlier when polishing.
Below in the explanation, the dielectric layer residue can be any polished dielectric layer through once or behind the polishing step for several times and still stay remaining dielectric layer material on the wafer surface, but also may be included in the residue that other dielectric layer produced under the polished dielectric layer.This dielectric layer residue can be the chip area that covers part, perhaps covers wafer fully.
In addition, the present invention can be applied in the polishing of various dielectric layer material, and these dielectric layer material can be applied in the manufacturing of semiconductor element, for example, and silica, silicon nitride and silicon oxynitride or the like.Except above-mentioned dielectric layer material, the present invention can also be applied in the polishing field of other material layer, for example, polysilicon, carborundum, phosphorosilicate glass, boron-phosphorosilicate glass and TEOS silica layer, utilize the high-density plasma silica layer that the high density plasma CVD method deposited or utilize silica layer that the plasma enhanced chemical vapor deposition method deposited or the like.
In a polishing embodiment of the present invention, deposit one first dielectric layer on the wafer, silica layer for example, this first dielectric layer covers on one second dielectric layer, for example silicon nitride layer.On the polishing order, wafer carries out primary polishing step earlier, wafer is contacted with first polishing pad, the fixing polishing pad of abrasive grains (abrasive-free polishing pad) of tool not normally, first polishing fluid that then disperses on it to contain abrasive grains is formed, remove first dielectric layer of most thickness, then, wafer is contacted with second polishing pad, be generally the fixedly polishing pad of abrasive grains of tool, second polishing fluid that dispersion does not contain abrasive grains on it is formed, and the first remaining dielectric layer is worn on the wafer surface.
For instance, aforementioned not tool fixedly the polishing pad of abrasive grains can be the IC-1000 series polishing pad that Rodel company is produced.The aforementioned tool fixedly polishing pad of abrasive grains can be SWR-159 type or the SWR-521 type polishing pad that 3M company is produced.And aforementioned cooperation tool fixedly employed second polishing fluid that does not contain abrasive grains of the polishing pad of abrasive grains to form can be proline series polishing fluid or the I-proline series polishing fluid that US business Applied Materials is produced.
See also Fig. 2 to Fig. 4, it illustrates is the generalized section that mixed type chemical mechanical polishing system that preferred embodiment of the present invention utilization has three polished land carries out the STI CMP process, wherein this mixed type chemical mechanical polishing system is included in and is fixed with a HSS grinding and polishing pad on first polished land, and is fixed with a FA grinding and polishing pad on second polished land.
As shown in Figure 2, semiconductor substrate 100 comprises semi-conductor layer 110, has defined insulating groove structure 135, silica bed course 115 and the silicon nitride bed course 120 of a plurality of patterned formation on it.Then, carry out a chemical vapor deposition method, for example high density plasma CVD (HDPCVD) technology deposits a dielectric layer 130 comprehensively on semiconductor substrate 100, makes it fill up insulating groove structure 135.
Wherein, dielectric layer 130 can be considered as aforesaid first dielectric layer, and silica bed course 115 and silicon nitride bed course 120 can be considered as aforesaid second dielectric layer.Dielectric layer 130 outside insulating groove structure 135, be positioned at and exceed thickness part 145 directly over the silicon nitride bed course 120, form irregular height surface 140.
As shown in Figure 3, then semiconductor substrate 100 is sent on first polished land, utilizes the HSS grinding and polishing pad and disperses the height on it to select polishing fluid to form the grinding and polishing that carries out dielectric layer 130.In this polishing stage, most of thickness of removable dielectric layer 130 on silicon nitride bed course 120, form smooth haply dielectric layer surface 150, and feasible remaining dielectric layer 130, THICKNESS CONTROL on silicon nitride bed course 120 is in thickness t, and this thickness t is the silica layer of aforesaid required strict control before entering next FA grinding and polishing pad polished land and advances preceding thickness (incoming oxidethickness).
As previously mentioned, in the mixed type chemical mechanical polishing process, when wafer enters second polished land, and utilize the FA grinding and polishing pad to carry out before the grinding and polishing, the silica layer on must strict control wafer surface advance preceding thickness t.The polishing as 12 cun wafers was even more important for the wafer of large-size in the control of thickness t before silica layer advanced, this is because so-called " fast grinding belt (fast-band) phenomenon " can cause when the technology enough and to spare reduction of wafer when utilizing the FA grinding and polishing pad to carry out grinding and polishing, make if polishing time one elongates slightly, promptly cause the consume of silicon nitride bed course, but, promptly cause on wafer, staying the silica residue if polishing time is short slightly.
According to a preferred embodiment of the invention, thickness t preferably can be controlled between about 200 dust to 250 dusts before silica layer advanced.
The aforesaid high polishing fluid of selecting is formed, and it can provide the selection ratio of silica to silicon nitride, preferably can reach about more than 5: 1, perhaps reaches 30: 1, even 50: 1 above better.The aforesaid high polishing fluid of selecting is formed, and its constituent that can comprise has abrasive grains solution (abrasive solution), additive (additives) and solvent composition or the like, is as the criterion according to the different supplier suppliers of institute.
Wherein, if the configuration proportion X of aforesaid abrasive grains solution, additive and solvent composition: Y: Z, then X is about about 1 to 20 usually, and Y is about about 0 to 20 usually, and Z is about about 0 to 20 usually.
Aforesaid abrasive grains solution, its composition can contain the silica abrasive grains (silica abrasive particles) of about 10% to 30% (percentage by weights) of having an appointment, and perhaps can contain the ceria abrasive grains (ceria abrasive particles) of about 0.5% to 5% (percentage by weights) of having an appointment.For instance, if aforesaid abrasive grains solution, its composition contains the ceria abrasive grains, and the particle size of its abrasive grains is preferably 300 nanometers (nm) or below 300 nanometers usually.
Then, as shown in Figure 4, semiconductor substrate 100 is sent on second polished land, utilize the FA grinding and polishing pad and disperse the polishing fluid that does not have abrasive grains on it to form the grinding and polishing of the dielectric layer 130 be left, form smooth semiconductor substrate surface fully, form channel insulation structure 160 simultaneously.
At last, any silicon nitride bed course 120 lip-deep dielectric layer residues of may staying can utilize another post processing polishing pad on the 3rd polished land, remove in the mode of crossing polishing.
See also Fig. 5, what it illustrated is according to the schematic flow sheet of controlling the method for target medium thickness in the preferred embodiment of the present invention mixed type chemical mechanical polishing process.The present invention is characterized in not use blank wafer (blanket wafer) to set up the polishing speed table, (in-line) utilizes in the product wafer of each batch (being generally 25) of waiting to send into polishing but directly adopt on line, to wherein arrange 3 to 8 wafer of front earlier and only carry out the polishing of different time respectively with the HSS grinding and polishing pad on first polished land, then after finishing polishing on first polished land, directly carry out the measurement of thickness, constitute the mapping of polishing thickness at the HSS grinding and polishing pad to polishing time (removal amount vs.polish time), set up the polishing speed table, and then according to remaining product wafer in same batch of this polishing speed table polishing.
As shown in Figure 5, the inventive method includes following main step:
Step 10: begin to carry out the CMP process of a certain batch products wafer, these product wafers have been finished the etching of sti trench groove and the backfill deposition step of dielectric layer all;
Step 12: in regular turn in the product wafer to this batch, 3 to 8 wafer of front are wherein only carried out the polishing of different time respectively with the HSS grinding and polishing pad on first polished land, for example, the 1st flake products wafer, the 2nd flake products wafer and the 3rd flake products wafer are carried out the polishing of 70 seconds, 80 seconds and 90 seconds respectively, and by that analogy;
Step 14: this 3 to 8 wafer is after finishing polishing on first polished land, carry out the measurement of residue medium thickness on each wafer on the direct-on-line, constitute the mapping of polishing thickness at the HSS grinding and polishing pad, set up the polishing speed table (polishing thickness is original thickness and cuts the thickness that is measured) of a linearity polishing time (removal amount vs.polish time);
Step 16: polish in this batch remaining product wafer according to this polishing speed table in regular turn with the HSS grinding and polishing pad on first polished land, the medium thickness on this product wafer respectively is controlled at a certain predetermined target thickness;
Step 18: polish product wafer remaining in this batch in regular turn with the FA grinding and polishing pad on second polished land, remove remaining medium thickness, expose the silicon nitride bed course of below;
Whether step 20:(can select to carry out) on the 3rd polished land, utilize another polishing pad, remove any silica dielectric layer residue that may stay on the pad silicon nitride laminar surface in the mode of crossing polishing;
Step 22: after finishing polishing on the 3rd polished land, carry out the measurement action of each wafer;
Step 24: with this 3 to 8 wafer, deliver on second polished land, polish this 3 to 8 wafer of reforming in regular turn with the FA grinding and polishing pad;
Step 26: carry out the measurement action of this 3 to 8 wafer; And
Step 28: the CMP process that finishes this batch products wafer.
See also Fig. 6, what it illustrated is to utilize aforementioned 3 to 8 flake products wafers of going ahead of the rest after finishing polishing on first polished land, carry out the measurement of residue medium thickness on each wafer on the direct-on-line, constitute the mapping of polishing thickness at the HSS grinding and polishing pad, the linear polishing speed table of setting up to polishing time (removal amount vs.polish time).Utilize line style computing match, can calculate linear gradient in the drawings, this slope can accurately be represented the polishing speed of HSS grinding and polishing pad for this batch product wafer, utilize this information immediate feedback to give follow-up polished same batch products wafer again, and under temporal mode, terminal point pattern (end-point mode) or polishing speed pattern (removal rate mode), polish, to reach before utilizing the polishing of FA grinding and polishing pad, the purpose of thickness before precisely controlling silica layer and advancing.
See also Fig. 7, what it illustrated is the schematic flow sheet of controlling the method for target medium thickness according to the present invention in another preferred embodiment mixed type chemical mechanical polishing process.The present invention can utilize in the product wafer of each batch of waiting to send into polishing on the line, to wherein arrange 3 to 8 wafer of front respectively with the HSS grinding and polishing pad on first polished land, and the polishing of carrying out different time with the FA grinding and polishing pad on second polished land, set up the polishing speed table then respectively, and then according to remaining product wafer in same batch of the polishing speed table polishing.
As shown in Figure 7, another preferred embodiment according to the present invention, the inventive method includes following main step:
Step 30: begin to carry out the CMP process of a certain batch products wafer, these product wafers have been finished the etching of sti trench groove and the backfill deposition step of dielectric layer all;
Step 32: in regular turn in the product wafer to this batch, 3 to 8 wafer of front are wherein carried out the polishing of different time respectively with the HSS grinding and polishing pad on first polished land, for example, the 1st flake products wafer, the 2nd flake products wafer and the 3rd flake products wafer are carried out the polishing of 70 seconds, 80 seconds and 90 seconds respectively, and by that analogy;
Step 34: this 3 to 8 wafer is after finishing polishing on first polished land, carry out the measurement of residue medium thickness on each wafer on the direct-on-line, constitute the mapping of polishing thickness at the HSS grinding and polishing pad, set up one first polishing speed table (polishing thickness is original thickness and cuts the thickness that is measured) polishing time;
Step 36: in regular turn this 3 to 8 wafer is carried out the polishing of different time with the FA grinding and polishing pad on second polished land respectively;
Step 38: this 3 to 8 wafer is carried out the measurement of residue medium thickness on each wafer on the direct-on-line after finishing polishing on second polished land, constitute the mapping of polishing thickness to polishing time at the FA grinding and polishing pad, sets up one second polishing speed table;
Step 40: according to this first polishing speed table, polish in this batch remaining product wafer in regular turn, the medium thickness on this product wafer respectively is controlled at a certain predetermined target thickness with the HSS grinding and polishing pad on first polished land;
Step 42: according to this second polishing speed table, polish product wafer remaining in this batch in regular turn, remove remaining medium thickness, expose the silicon nitride bed course of below with the FA grinding and polishing pad on second polished land;
Whether step 44:(can select to carry out) on the 3rd polished land, utilize another polishing pad, remove any silica dielectric layer residue that may stay on the pad silicon nitride laminar surface in the mode of crossing polishing;
Step 46: after finishing polishing on the 3rd polished land, carry out the measurement action of each wafer;
Step 48: this 3 to 8 wafer that will only polish through the HSS grinding and polishing pad, deliver on second polished land, polish this 3 to 8 wafer of reforming in regular turn with the FA grinding and polishing pad;
Step 50: carry out the measurement action of this 3 to 8 wafer; And
Step 52: the CMP process that finishes this batch products wafer.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (28)
1. control method on the line of a mixed type chemical mechanical polishing process comprises the steps:
The mixed type chemical mechanical polishing system is provided, comprises at least one first polished land and one second polished land, wherein be respectively equipped with dissimilar grinding and polishing pad on this first polished land and this second polished land;
One batch polished product wafer is provided, wherein respectively be formed with pattern structure all on this polished product wafer, and first dielectric layer deposition is on this pattern structure and second dielectric layer;
The product wafer in advance of at least 3 in the polished product wafer of this batch of polishing on this first polished land is removed respectively this first dielectric layer of different-thickness above the product wafer in advance respectively in regular turn;
Carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness, set up linear polishing speed table polishing time at the grinding and polishing pad on this first polished land; And
According to this polishing speed table that the product wafer of should going ahead of the rest is set up, the product wafer that is left in this batch of polishing on this first polished land is controlled at predetermined target thickness with this first medium thickness polishing on remaining respectively this product wafer in regular turn.
2. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein at this polishing speed table of being set up according to the product wafer of should going ahead of the rest, after the product wafer that is left in this batch of polishing on this first polished land, this method also comprises the steps: in regular turn
On this second polished land, polish this remaining in this batch product wafer in regular turn,, expose this second dielectric layer of below to remove this remaining first medium thickness.
3. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 2 is wherein polished on this second polished land after this remaining in this batch product wafer in regular turn, and this method also comprises the steps:
On the 3rd polished land, polish this remaining in this batch product wafer in regular turn in the mode of crossing polishing, remove and anyly may stay the lip-deep residue of this second dielectric layer.
4. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein this dissimilar grinding and polishing pad includes high selectivity grinding and polishing pad and fixing abrasive grains grinding and polishing pad.
5. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein this pattern structure includes insulating groove structure.
6. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein this first dielectric layer includes silica.
7. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein this second dielectric layer includes silicon nitride.
8. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under temporal mode.
9. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under the polishing speed pattern.
10. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 1, wherein target thickness that should be predetermined is between 200 dust to 250 dusts.
11. control method on the line of a mixed type chemical mechanical polishing process comprises the steps:
The mixed type chemical mechanical polishing system is provided, comprises at least one first polished land and one second polished land, wherein be respectively equipped with high selectivity grinding and polishing pad and fixing abrasive grains grinding and polishing pad on this first polished land and this second polished land;
One batch polished product wafer is provided, wherein respectively be formed with pattern structure all on this polished product wafer, and first dielectric layer deposition is on this pattern structure and second dielectric layer;
On this first polished land, utilize this high selectivity grinding and polishing pad to polish the product wafer in advance of 3-8 sheet in the polished product wafer of this batch in regular turn, remove respectively this first dielectric layer of different-thickness above the product wafer in advance respectively;
Carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness, set up linear polishing speed table polishing time at this high selectivity grinding and polishing pad on this first polished land; And
According to being somebody's turn to do this polishing speed table that the product wafer of going ahead of the rest is set up, in regular turn on this first polished land, utilize this high selectivity grinding and polishing pad to polish product wafer remaining in this batch, this first medium thickness polishing on remaining respectively this product wafer is controlled at predetermined target thickness.
12. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein after the product wafer that is left in this batch of polishing on this first polished land, this method also comprises the steps:
On this second polished land, polish this remaining in this batch product wafer in regular turn,, expose this second dielectric layer of below to remove this remaining first medium thickness.
13. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 12 is wherein polished on this second polished land after this remaining in this batch product wafer in regular turn, this method also comprises the steps:
On the 3rd polished land, polish this remaining in this batch product wafer in regular turn in the mode of crossing polishing, remove and anyly may stay the lip-deep residue of this second dielectric layer.
14. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein this pattern structure includes insulating groove structure.
15. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein this first dielectric layer includes silica.
16. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein this second dielectric layer includes silicon nitride.
17. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under temporal mode.
18. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under the polishing speed pattern.
19. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 11, wherein target thickness that should be predetermined is between 200 dust to 250 dusts.
20. control method on the line of a mixed type chemical mechanical polishing process comprises the steps:
The mixed type chemical mechanical polishing system is provided, comprises at least one first polished land and one second polished land, wherein be respectively equipped with dissimilar grinding and polishing pad on this first polished land and this second polished land;
One batch polished product wafer is provided, wherein respectively be formed with pattern structure all on this polished product wafer, and first dielectric layer deposition is on this pattern structure and second dielectric layer;
The product wafer in advance of at least 3 in the polished product wafer of this batch of polishing on this first polished land is removed respectively this first dielectric layer of different-thickness above the product wafer in advance respectively in regular turn;
Carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness, set up the first polishing speed table polishing time at the grinding and polishing pad on this first polished land;
This product wafer in advance of at least 3 of polishing on this second polished land is removed respectively this first dielectric layer of different-thickness above the product wafer in advance respectively in regular turn;
Carry out respectively being somebody's turn to do the measurement of residue medium thickness on the product wafer of going ahead of the rest on the line, and constitute of the mapping of corresponding polishing thickness, set up the second polishing speed table polishing time at the grinding and polishing pad on this second polished land;
According to being somebody's turn to do this first polishing speed table that the product wafer of going ahead of the rest is set up, the product wafer that is left in this batch of polishing on this first polished land is controlled at predetermined target thickness with this first medium thickness polishing on remaining respectively this product wafer in regular turn; And
This second polishing speed table according to the product wafer of should going ahead of the rest is set up polishes product wafer remaining in this batch in regular turn on this second polished land, with this remaining first medium thickness polishing removal.
21. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20 is wherein polished on this second polished land after this remaining in this batch product wafer in regular turn, this method also comprises the steps:
On the 3rd polished land, polish this remaining in this batch product wafer in regular turn in the mode of crossing polishing, remove and anyly may stay the lip-deep residue of this second dielectric layer.
22. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein this dissimilar grinding and polishing pad includes high selectivity grinding and polishing pad and fixing abrasive grains grinding and polishing pad.
23. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein this pattern structure includes insulating groove structure.
24. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein this first dielectric layer includes silica.
25. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein this second dielectric layer includes silicon nitride.
26. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under temporal mode.
27. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein the product wafer that is left in this batch of polishing on this first polished land is to utilize to carry out under the polishing speed pattern.
28. control method on the line of mixed type chemical mechanical polishing process as claimed in claim 20, wherein target thickness that should be predetermined is between 200 dust to 250 dusts.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610092381 CN101081488A (en) | 2006-06-02 | 2006-06-02 | Online control method of mixed type chemical mechanical buffing technics |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610092381 CN101081488A (en) | 2006-06-02 | 2006-06-02 | Online control method of mixed type chemical mechanical buffing technics |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034703A (en) * | 2009-09-29 | 2011-04-27 | 无锡华润上华半导体有限公司 | Grinding method |
| CN102380815A (en) * | 2010-09-01 | 2012-03-21 | 无锡华润上华半导体有限公司 | Chemical mechanical grinding method and chemical mechanical grinding system |
| CN102049735B (en) * | 2009-10-29 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method and system for controlling chemical mechanical polishing time |
| CN103165487A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Method for detecting grinding rate of pattern silicon wafers |
| CN113192829A (en) * | 2021-05-13 | 2021-07-30 | 上海芯物科技有限公司 | Method, apparatus, device and storage medium for dynamically adjusting wafer polishing time |
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2006
- 2006-06-02 CN CN 200610092381 patent/CN101081488A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034703A (en) * | 2009-09-29 | 2011-04-27 | 无锡华润上华半导体有限公司 | Grinding method |
| CN102049735B (en) * | 2009-10-29 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method and system for controlling chemical mechanical polishing time |
| CN102380815A (en) * | 2010-09-01 | 2012-03-21 | 无锡华润上华半导体有限公司 | Chemical mechanical grinding method and chemical mechanical grinding system |
| CN103165487A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Method for detecting grinding rate of pattern silicon wafers |
| CN103165487B (en) * | 2011-12-12 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | The method of test pattern sheet silicon grinding rate |
| CN113192829A (en) * | 2021-05-13 | 2021-07-30 | 上海芯物科技有限公司 | Method, apparatus, device and storage medium for dynamically adjusting wafer polishing time |
| CN113192829B (en) * | 2021-05-13 | 2023-04-18 | 上海芯物科技有限公司 | Method, apparatus, device and storage medium for dynamically adjusting wafer polishing time |
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