CN102034703A - Grinding method - Google Patents

Grinding method Download PDF

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Publication number
CN102034703A
CN102034703A CN2009101967266A CN200910196726A CN102034703A CN 102034703 A CN102034703 A CN 102034703A CN 2009101967266 A CN2009101967266 A CN 2009101967266A CN 200910196726 A CN200910196726 A CN 200910196726A CN 102034703 A CN102034703 A CN 102034703A
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CN
China
Prior art keywords
dielectric layer
electrode
grinding
medium layer
wafer
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Pending
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CN2009101967266A
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Chinese (zh)
Inventor
李健
周祖源
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Wuxi CSMC Semiconductor Co Ltd
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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Priority to CN2009101967266A priority Critical patent/CN102034703A/en
Publication of CN102034703A publication Critical patent/CN102034703A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a grinding method comprising the following steps: providing a wafer, wherein the surface of the wafer is provided with a plurality of electrodes extruding out of the surface; growing a first medium layer on the surface of the wafer, which is provided with the electrodes, wherein the first medium layer completely covers the electrodes; grinding the first medium layer until the first medium layer just is exposed out of the surface of the electrode; growing a second medium layer on the first grinded medium layer and the surface of the electrode; and grinding the surface of the second medium layer. The invention has the advantages that a method of growing the medium layers twice is adopted, wherein a medium layer firstly grows and is ground to the surface of the electrode to improve surface planeness, and then another medium layer grows to cover the exposed electrode, thus the medium layer covering the surface of the electrode has a flat surface.

Description

Ginding process
[technical field]
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of Ginding process.
[background technology]
In the production process of field of semiconductor manufacture, what the chemico-mechanical polishing of metal wiring layer and intermetallic dielectric layer was adopted usually is the mode of grinding the set time, and dielectric layer to be ground is ground to another thicknesses of layers (as 600nm) from a certain thicknesses of layers (as 1000nm).
If dielectric layer is the surface that is grown in transistor gate, have grid and cause its surface to have very big fluctuating owing to being subjected to the transistor surface, therefore also very inhomogeneous at the thickness of the dielectric layer of its surface deposition, and the existing this mode by the set time grinding of CMP can not be with the complete planarization of film, and the surface topography after the grinding can be inherited the pattern before grinding.
Be the wafer 10 that above-mentioned surface has electrode shown in the accompanying drawing 1, comprise a plurality of electrodes on support substrates 11 and surface, this sentences electrode 13 and 15 expressions.As shown in Figure 2, next at its superficial growth dielectric layer 19.The surface topography of dielectric layer 19 has been inherited the surface topography of wafer 10, is occurring projection equally with electrode 13 and 15 corresponding positions.At last dielectric layer 19 is carried out the grinding of set time to obtain to have the dielectric layer 19 of target thickness, because the projection that the surface of dielectric layer 19 has is caused by grid structure 13 and 15, this fluctuating quantity may surpass the maximum surface undulation scope that grinding technics can be handled in this set time, thereby the surface after dielectric layer 19 grinds still has certain fluctuating.Perhaps the fluctuating on surface can be polished and prolong milling time, still but changed the thickness of dielectric layer 19 simultaneously, this is can not be received equally.
Therefore, the relatively poor surface of the uniformity that causes owing to the intrinsic fluctuating of crystal column surface in the prior art can be caused potential threat to follow-up photoetching process.
[summary of the invention]
Technical problem to be solved by this invention is, a kind of Ginding process is provided, and can improve the relatively poor surface of the uniformity that causes owing to the intrinsic fluctuating of crystal column surface, thereby obtains to have the dielectric layer of flat surface.
In order to address the above problem, the invention provides a kind of Ginding process, comprise the steps: to provide a wafer, described crystal column surface has the electrode of a plurality of protuberates; Have superficial growth first dielectric layer of electrode at described wafer, described first dielectric layer is with the electrode all standing; Grind described first dielectric layer to the surface of exposing electrode just; And superficial growth second dielectric layer of first dielectric layer after grinding and electrode.
As optional technical scheme, the material of described first dielectric layer is different with the material of electrode surface.
As optional technical scheme, the material of described first dielectric layer is a silica, and the surfacing of electrode is a silicon nitride.
As optional technical scheme, described first dielectric layer of described grinding to the step of exposing electrode just further comprises: begin to grind first dielectric layer, and the load with motor is ground in monitoring simultaneously; When grinding load with motor when changing, stop grinding to first dielectric layer.
As optional technical scheme, described Ginding process further comprises: after growth regulation second medium layer, and the surface of grinding second dielectric layer.
As optional technical scheme, described first dielectric layer is identical with the described second dielectric layer material.
As optional technical scheme, the material of described first dielectric layer and described second dielectric layer is silica.
The invention has the advantages that, adopt the method for twice dielectric layer of growth, the surface of at first growing one deck dielectric layer and being ground to electrode is to improve the evenness on surface, and regrowth one deck dielectric layer covers with the electrode that will expose, thereby makes the dielectric layer of the surface coverage of electrode have even curface.
[description of drawings]
Accompanying drawing 1 is process schematic representations of prior art of the present invention with accompanying drawing 2;
Accompanying drawing 3 is implementation step schematic diagrames of Ginding process embodiment of the present invention;
Accompanying drawing 4 is process schematic representations of Ginding process embodiment of the present invention to accompanying drawing 8.
[embodiment]
Elaborate below in conjunction with the embodiment of accompanying drawing to a kind of Ginding process provided by the invention.
Be the implementation step schematic diagram of this embodiment shown in the accompanying drawing 3, comprise: step S20, a wafer is provided, described crystal column surface has the electrode of a plurality of protuberates; Step S21 has superficial growth first dielectric layer of electrode at described wafer, and described first dielectric layer is with the electrode all standing; Step S22 grinds first dielectric layer, and the load with motor is ground in monitoring simultaneously; Step S23 when grinding load with motor when changing, stops the grinding to first dielectric layer; Step S24, superficial growth second dielectric layer of first dielectric layer after grinding and electrode.
The Ginding process of better embodiment of the present invention is described below in conjunction with crystal circle structure schematic diagram shown in the accompanying drawing 4.As shown in Figure 4, refer step S20 provides a wafer 200, and described wafer 200 surfaces have the electrode 201,202 and 203 of a plurality of protuberates.
The height on described electrode 201,202 and 203 outstanding wafer 200 surfaces and the width of electrode are proportional.Described electrode can be transistorized grid, and the common height of grid is between tens nanometer to tens nanometers, is made of multiple-level stack structures such as polysilicon layer, silica medium layers, therefore is also referred to as stacking gate.No matter described electrode 201,202 and 203 is that grid or other have the electrode of similar structures, this highly tend to surpass follow-up grinding technics the maximum fluctuating scope that can handle.
Described electrode 201,202 and 203 surface are generally insulating barrier, and with the stacked structure of guard electrode, the material of described insulating barrier is generally silicon nitride.
Shown in the accompanying drawing 5, refer step S21 has superficial growth first dielectric layer 210 of electrode 201,202 and 203 at described wafer 200, and described first dielectric layer 210 is with electrode 201,202 and 203 all standings.
As optimized technical scheme, the material of described first dielectric layer 210 is different with the material on electrode 201,202 and 203 surfaces, can more easily surveying the load that motor produces owing to the frictional force of grinding in the technology that helps follow-up grinding, and exactly grinding step is stopped at the surface of electrode 201,202 and 203.In this embodiment, the material of described first dielectric layer 210 is a silica, and electrode 201,202 and 203 surfacing are silicon nitride.
Because the electrode 201,202 and 203 that wafer 200 has protuberate, first dielectric layer 210 that therefore covers electrode surface also has similar contoured surface.
Shown in the accompanying drawing 6, refer step S22 begins to grind first dielectric layer 210, and the load with motor 280 is ground in monitoring simultaneously.
Normally, the major part of grinder is a grinding head, and grinding head engages with motor, and motor is used to drive grinding head and is rotated.The grinding head axle head is thin film fixedly, is used for directly contacting with the back side of wafer.Exert pressure to wafer by film, wafer is pressed on the grinding pad.Gas is arranged in the grinding head, can control the pressure of film by the pressure of control gaseous to wafer.
Continue with reference to the accompanying drawings 6, described grinding is adopted motor 280 to drive an abrasive disk 290 and is rotated, and abrasive disk 290 is placed first dielectric layer 210 surface to be ground, by rotation the surface of first dielectric layer 210 is implemented to grind.
Shown in the accompanying drawing 7, refer step S23 when grinding load with motor 280 when changing, stops the grinding to first dielectric layer 210.
Under the material of first dielectric layer 210 situation different with the material on electrode 201,202 and 203 surfaces, be ground to when abrasive disk 290 under the situation on electrode 201,202 and 203 surfaces, because surface mass changes, therefore and the frictional force between the abrasive disk 290 also must change, thereby the output current that further causes grinding with motor 280 changes.With the material that adopts first dielectric layer 210 in this embodiment is silica, and electrode 201,202 is that silicon nitride is an example with 203 surfacing, and resistance becomes big when being ground to electrode 201,202 and 203 surperficial, and the output current change that causes motor 280 greatly.Therefore under the big situation of the output current change that monitors motor 280, mean that promptly grinding has made the surface of electrode 201,202 and 203 come out, need stop the grinding to first dielectric layer 210 this moment.
Owing to be ground to the surface of electrode 201,202 and 203 always, the surface after therefore grinding is smooth in the obvious above-mentioned steps.
Above step S22 and step S23 are optional step, and its essence is to grind described first dielectric layer 210 to the surface of exposing electrode 201,202 and 203 just.Also can utilize other technology to realize above-mentioned technology.Can select other suitable detection methods according to first dielectric layer 210 and electrode surface material, for example adopt the variation of monitoring surfacial pattern or the method for reflectance varies to realize the above-mentioned technique effect identical with step S23 with step S22.
Shown in the accompanying drawing 8, refer step S24, first dielectric layer 210 after grinding and superficial growth second dielectric layer 220 of electrode 201,202 and 203.
The purpose of somatomedin layer is electrode 201,202 and 203 is all covered in this embodiment, but be ground to always and expose electrode 201,202 and 203 in order to obtain smooth surface in the grinding steps of above-mentioned steps S23, therefore need further growth second dielectric layer 220 with electrode 201,202 and 203 coverings.Different is with growth first dielectric layer, because second dielectric layer 220 is in smooth superficial growth, therefore the surface of second dielectric layer 220 also is a relatively flat.
Described second dielectric layer 220 can be identical with the material of first dielectric layer 210, and is preferably silica, to avoid that technology is produced unnecessary pollution and because the difference of two layers of material and produce residual stress in the inside of material.
If think that second dielectric layer 220 surface is because growth technique self reason and spontaneous slight fluctuating still can have influence on follow-up photoetching process can also further utilize grinding technics that milled processed is implemented on the surface of second dielectric layer 220 once more.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (7)

1. a Ginding process is characterized in that, comprises the steps:
One wafer is provided, and described crystal column surface growth has the electrode of protuberate;
Have superficial growth first dielectric layer of electrode at described wafer, described first dielectric layer is with the electrode all standing;
Grind described first dielectric layer to the surface of exposing electrode just; And
Superficial growth second dielectric layer of first dielectric layer after grinding and electrode.
2. Ginding process according to claim 1 is characterized in that, the material of described first dielectric layer is different with the material of electrode surface.
3. Ginding process according to claim 2 is characterized in that, the material of described first dielectric layer is a silica, and the surfacing of electrode is a silicon nitride.
4. according to claim 2 or 3 described Ginding process, it is characterized in that described first dielectric layer of described grinding to the step of exposing electrode just further comprises:
Begin to grind first dielectric layer, and the load with motor is ground in monitoring simultaneously;
When grinding load with motor when changing, stop grinding to first dielectric layer.
5. Ginding process according to claim 1 is characterized in that, described Ginding process further comprises:
After growth regulation second medium layer, the surface of grinding second dielectric layer.
6. Ginding process according to claim 1 is characterized in that, described first dielectric layer is identical with the described second dielectric layer material.
7. according to claim 1 or 6 described Ginding process, it is characterized in that the material of described first dielectric layer and described second dielectric layer is silica.
CN2009101967266A 2009-09-29 2009-09-29 Grinding method Pending CN102034703A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206383A (en) * 2016-09-05 2016-12-07 江苏纳沛斯半导体有限公司 Film forming method and semiconductor structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1812096A (en) * 2004-11-10 2006-08-02 三星电子株式会社 Cross-point nonvolatile memory devices and methods of fabricating the same
CN101005025A (en) * 2006-01-17 2007-07-25 三星电子株式会社 Fabrication method of semiconductor device having reduced thickness variations and semiconductor device fabricated using the same
CN101081488A (en) * 2006-06-02 2007-12-05 联华电子股份有限公司 Online control method of mixed type chemical mechanical buffing technics
CN101192569A (en) * 2006-12-01 2008-06-04 中芯国际集成电路制造(上海)有限公司 Semicondutor device polycrystalline silicon contact structure for mounting chip and grid structure preparation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1812096A (en) * 2004-11-10 2006-08-02 三星电子株式会社 Cross-point nonvolatile memory devices and methods of fabricating the same
CN101005025A (en) * 2006-01-17 2007-07-25 三星电子株式会社 Fabrication method of semiconductor device having reduced thickness variations and semiconductor device fabricated using the same
CN101081488A (en) * 2006-06-02 2007-12-05 联华电子股份有限公司 Online control method of mixed type chemical mechanical buffing technics
CN101192569A (en) * 2006-12-01 2008-06-04 中芯国际集成电路制造(上海)有限公司 Semicondutor device polycrystalline silicon contact structure for mounting chip and grid structure preparation method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
周国安等: "CMP综合终点检测研究", 《微纳电子技术》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206383A (en) * 2016-09-05 2016-12-07 江苏纳沛斯半导体有限公司 Film forming method and semiconductor structure

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Application publication date: 20110427