CN103165487A - Method for detecting grinding rate of pattern silicon wafers - Google Patents
Method for detecting grinding rate of pattern silicon wafers Download PDFInfo
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- CN103165487A CN103165487A CN2011104126611A CN201110412661A CN103165487A CN 103165487 A CN103165487 A CN 103165487A CN 2011104126611 A CN2011104126611 A CN 2011104126611A CN 201110412661 A CN201110412661 A CN 201110412661A CN 103165487 A CN103165487 A CN 103165487A
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Abstract
The invention discloses a method for detecting the grinding rate of pattern silicon wafers. The method for detecting the grinding rate of the pattern silicon wafers includes the following steps: step 1, initial sectional differences at different positions of a specific measurement pattern of each pattern silicon wafer are measured and recorded; step two, several pattern silicon wafers with the same growing thickness are chosen, and a chemical mechanical polishing device is used for polishing each of the pattern silicon wafer at different time; step three, the final values of the sectional differences at the position of the specific measurement pattern of each pattern silicon wafer polished at different time are obtained through measurement and recording; and step four, the final values of the sectional differences of each pattern silicon wafer and the different polishing time are used for drawing a graph to obtain a straight line. The gradient K of the straight line is the grinding rate at any position of each pattern silicon wafer. Through the method for detecting the grinding rate of the pattern silicon wafers, the grinding rate of any pattern silicon wafer can be detected accurately, quickly and effectively. The method for detecting the grinding rate of the pattern silicon wafers is different from a destructive detecting method for the pattern silicon wafers through slicing, and the reutilization rate of the pattern silicon wafers is high.
Description
Technical field
The present invention relates to a kind of method of semiconductor grinding speed monitoring.
Background technology
At present, semiconductor technology silicon epitaxial wafer thickness method of testing mainly adopts fourier infrared (FTIR) method of testing, the method is that the doping content according to silicon epitaxy layer and substrate layer has obvious difference to demarcate the thickness of epitaxial loayer (substrate generally has high doping content, for example highly doped P type or N-type substrate).But (generally higher than 1000 degree) are carried out in epitaxial growth under hot conditions, the dopant of substrate can spread in epitaxial loayer in epitaxial process, thereby cause moving and thickening on the interface of substrate and epitaxial loayer, the degree of moving on different epitaxial growth conditions interface is different, the result of measuring with the method exists larger error, and the accurate required measurement pattern of positioning pattern silicon chip surface, therefore FTIR is inapplicable in the silicon graphics sheet.Due to opaqueness and the surface roughness of silicon, traditional MTE measures and also exists certain error to lose efficacy.The monitoring of pattern piece silicon grinding rate now is mainly that after relying on the FA section to carry out X-SEM video picture measurement EPI extension CMP, thereby value is calculated the silicon grinding rate by the relation of thickness difference and time, and is complicated and not high to the utilance of silicon chip.
The traditional graph sheet is in the chemical mechanical milling tech (CMP) of silicon, because the epitaxial silicon on the monocrystalline of filling in deep trench and substrate belongs to commaterial, to not selecting ratio with the silicon lapping liquid.If directly touch the substrate silicon surface in process of lapping, may affect some electric property of device.Traditional (MTE) thus ellipse inclined to one side thickness measurement platform removes to measure its thickness accurately monitors process of lapping.Usually the monocrystalline thickness of non-pattern piece measures with FTIR, the method is that the doping content according to silicon epitaxy layer and substrate layer has obvious difference to demarcate the thickness of epitaxial loayer (substrate generally has high doping content, for example highly doped P type or N-type substrate).But (generally higher than 1000 degree) are carried out in epitaxial growth under hot conditions, the dopant of substrate can spread in epitaxial loayer in epitaxial process, thereby cause moving and thickening on the interface of substrate and epitaxial loayer, the degree of moving on different epitaxial growth conditions interface is different, the result of measuring with the method exists larger error, and the accurate required measurement pattern of positioning pattern silicon chip surface, therefore FTIR is inapplicable in the silicon graphics sheet.
For CMP technique, the grinding rate of non-figure and pattern piece has larger difference usually.Rate detection for pattern piece, can't complete with FTIR, at present often by being that (FA section) carried out the X-SEM video picture and measured thickness and then calculate pattern piece (patternwafer) rate detection in conjunction with milling time, process is complicated and do not have a practicality.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of, and it can solve silicon epitaxy pattern piece grinding rate monitoring problem, controls easily and effectively adjustment CMP technique.
In order to solve above technical problem, the invention provides a kind of method of test pattern sheet silicon grinding rate, comprise the following steps: step 1, measure and recording geometry structure sheet specified quantitative mapping shape diverse location initial offset; Step 2, several pieces of pattern piece that silicon growth thickness is suitable of selection are ground with different time each piece epitaxial wafer with chemical-mechanical polisher; Step 3, silicon graphics structure sheet value after after the offset of specified quantitative mapping shaped position, value is measured and recorded that each piece ground with different time; Step 4, value after the offset of each piece silicon graphics structure sheet and the mapping of different milling time are drawn straight line.The slope K of this straight line is the grinding rate in the silicon chip any position.
Beneficial effect of the present invention is: the method can obtain can any different graphic sheet of Accurate Determining the silicon grinding rate, fast effectively.Be different from section to the destructiveness detection of silicon chip, high to the recycling rate of silicon chip.
In described step 1, measurement platform can be MRH scan-probe or AFM atomic force microscope.
The silicon graphics sheet that in described step 2, each piece thickness is suitable grinds with different time, and it can be any time that certain intervals is arranged that the time is chosen.
Carry out respectively the grinding of different time with many pieces of silicon graphics structure sheets in described step 4, thereby the speed sudden change that may produce when having avoided grinding separately causes the error of mensuration, has linear correlation with this rate value of making on one piece.
The present invention also provides the preparation method of the silicon graphics sheet of required use: comprise the following steps:
Step 1, surface of silicon hard mask hardmask deposition, hard mask hardmask used can be oxide-film, nitride film or nitrogen oxidation film;
In described step 2, the growth technique of the etching of nitride film and oxide-film can be plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, and the low pressure chemical gas phase is sunk method LP-CVD.
In described step 2, the thickness of nitride film and oxide-film is 10～5000 dusts.
Hard mask hardmask etching in described step 3, the oxide-film dry etching, channel bottom is carved into the end; The characteristic size size can be 5～50 microns.
In described step 4, the extension height can be the 10.0-100.0 micron.
Description of drawings
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the initial offset H0 of pattern piece growing epitaxial silicon schematic diagram;
Fig. 2 is value H1 schematic diagram after pattern piece silicon grinding t1 time offset;
Fig. 3 is value H2 schematic diagram after pattern piece silicon grinding t2 time offset;
Fig. 4 is value H3 schematic diagram after pattern piece silicon grinding t3 time offset;
Fig. 5 is straight line schematic diagram of pattern piece silicon grinding rate.
Description of reference numerals in figure:
1: silicon substrate, 2: oxide-film (nitride film) barrier layer, 3: silicon epitaxy layer.
Embodiment
The present invention propose a kind of by (MRH) thus the poor instrument of section measure the offset value mapping test pattern sheet silicon grinding rate of a certain specified quantitative mapping shapes after many pieces of silicon graphics sheet different times grind and (be applicable to detect the Different Silicon pattern piece at the wafer diverse location, as (center C enter the middle part Middle edge Edge) speed) method, the grinding rate of the silicon graphics sheet under it can detect any time fast and effectively, without cut sections for microscopic examination, guaranteed the recycling of silicon chip.The present invention is by the process of selective epitaxial, and preparation has the pattern piece of certain section difference, by detecting remaining section difference of different milling time crystal column surfaces with the poor instrument of section, comes the grinding rate of test pattern sheet.
The present invention is by the process of selective epitaxial, and preparation has the pattern piece of certain section difference, by detecting remaining section difference of different milling time crystal column surfaces with the poor instrument of section, comes the grinding rate of test pattern sheet.
The preparation method of the silicon graphics sheet of required use:
1, silicon substrate 1 surface hard mask hardmask deposition, hard mask hardmask used can be oxide-film, nitride film or nitrogen oxidation film 2.The growth technique of the etching of nitride film and oxide-film 2 can be plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, the heavy method LP-CVD of low pressure chemical gas phase etc.Thickness is 10～5000 dusts.
2, hard mask hardmask etching, the oxide-film dry etching, channel bottom is carved into the end.The characteristic size size can be 5～50 microns.
3, selectivity monocrystalline silicon extension 3 depositions make the height of silicon epitaxy 3 greater than hard mask hardmask surface.(here take super junction EPI extension as example, need to accomplish hard mask hardmask open, then carry out selective epitaxial process.) the extension height can be the 10.0-100.0 micron.
The method of a kind of test pattern sheet silicon grinding rate of the present invention, it comprises:
1) as shown in Figure 1, measure and recording geometry structure sheet specified quantitative mapping shape diverse location initial offset;
2) as Fig. 2-shown in Figure 4, select several pieces of pattern piece that silicon growth thickness is suitable, with chemical-mechanical polisher, each piece Epi epitaxial wafer is ground with different time;
3) rear value is measured and recorded to each piece with silicon graphics structure sheet value after the offset of specified quantitative mapping shaped position (can be the optional position of silicon chip) that different time grinds;
4) as shown in Figure 5, value after the offset of each piece silicon graphics structure sheet and different milling time mappings are drawn straight line.The slope K of this straight line is the grinding rate in the silicon chip any position.
Described step 1) in, measurement platform can be MRH scan-probe or AFM atomic force microscope, because the opaqueness of silicon and rough surface, can't measure the Epi epitaxial thickness with conventional MTE board (ellipse inclined to one side thickness measurement platform), because silicon has conformality preferably, the offset top can be more smooth, applicable MRH scan-probe method.
Described step 2) the silicon graphics sheet that each piece thickness is suitable grinds with different time, and it can be any time that certain intervals is arranged that the time is chosen.
Described step 4) carry out respectively the grinding of different time with many pieces of silicon graphics structure sheets in, thereby the speed sudden change that may produce when having avoided grinding separately causes the error of mensuration, has linear correlation with this rate value of making on one piece.
On the silicon graphics sheet, remove to measure its selected offset (can be the figure of any position of silicon chip) that measures figure with MRH scan-probe board, record primary data, then select several pieces of silicon graphics sheets that level is suitable, with chemical-mechanical polisher, each piece silicon graphics sheet is ground with different time respectively, be worth after removing to measure the offset of selected figure of each piece pattern piece with MRH more afterwards, with this slope straight line of making, slope K is namely that the silicon graphics sheet is at the grinding rate of selected graph position.
In example, silicon fiml can be that the LPC growth can be also the EPI epitaxial growth, measuring instrument used can be MRH offset instrument and AFM atomic force microscope, and the method is applicable to the pattern piece of any silicon growth, and the detection of silicon grinding rate is cut into slices without FA, is not destructive.
The present invention is not limited to execution mode discussed above.Above description to embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the apparent conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.
Claims (9)
1. the method for a test pattern sheet silicon grinding rate, is characterized in that, comprises the following steps:
Step 1, measure and recording geometry structure sheet specified quantitative mapping shape diverse location initial offset;
Step 2, several pieces of pattern piece that silicon growth thickness is suitable of selection are ground with different time each piece epitaxial wafer with chemical-mechanical polisher;
Step 3, silicon graphics structure sheet value after after the offset of specified quantitative mapping shaped position, value is measured and recorded that each piece ground with different time;
Step 4, value and different milling times after the offset of each piece silicon graphics structure sheet are drawn straight line, the slope K of this straight line is the grinding rate in the silicon chip any position.
2. the method for test pattern sheet silicon grinding rate as claimed in claim 1, is characterized in that, in described step 1, measurement platform can be MRH scan-probe or AFM atomic force microscope.
3. the method for test pattern sheet silicon grinding rate as claimed in claim 1, is characterized in that, the silicon graphics sheet that in described step 2, each piece thickness is suitable grinds with different time, and it can be any time that certain intervals is arranged that the time is chosen.
4. the method for test pattern sheet silicon grinding rate as claimed in claim 1, is characterized in that, carries out respectively the grinding of different time with many pieces of silicon graphics structure sheets in described step 4.
5. the method for test pattern sheet silicon grinding rate as claimed in claim 1, is characterized in that, the preparation method of the silicon graphics sheet of required use: comprise the following steps:
Step 1, surface of silicon hard mask deposition, hard mask used can be oxide-film, nitride film or nitrogen oxidation film;
Step 2, hard mask etching, the oxide-film dry etching, channel bottom is carved into the end;
Step 3, selective epitaxial monocrystalline deposition make the height of epitaxy single-crystal greater than the hard mask surface.
6. the method for test pattern sheet silicon grinding rate as claimed in claim 5, it is characterized in that, in described step 2, the growth technique of the etching of nitride film and oxide-film can be plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, the low pressure chemical gas phase is sunk method LP-CVD.
7. the method for test pattern sheet silicon grinding rate as claimed in claim 6, is characterized in that, in described step 2, the thickness of nitride film and oxide-film is 10～5000 dusts.
8. the method for test pattern sheet silicon grinding rate as claimed in claim 5, is characterized in that, hard mask etching in described step 3, and the oxide-film dry etching, channel bottom is carved into the end; The characteristic size size can be 5～50 microns.
9. the method for test pattern sheet silicon grinding rate as claimed in claim 5, is characterized in that, in described step 4, epitaxial deposition process can be normal pressure or reduced pressure epitaxy growth, highly can be the 10.0-100.0 micron.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5658183A (en) * | 1993-08-25 | 1997-08-19 | Micron Technology, Inc. | System for real-time control of semiconductor wafer polishing including optical monitoring |
| CN1340210A (en) * | 1999-10-13 | 2002-03-13 | 皇家菲利浦电子有限公司 | Method and system for polishing semiconductor wafers |
| CN1492213A (en) * | 2002-10-23 | 2004-04-28 | 台湾积体电路制造股份有限公司 | Method for measuring non-metal layer thickness in chemical and mechanical grinding process |
| CN101081488A (en) * | 2006-06-02 | 2007-12-05 | 联华电子股份有限公司 | Online control method of mixed type chemical mechanical buffing technics |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5658183A (en) * | 1993-08-25 | 1997-08-19 | Micron Technology, Inc. | System for real-time control of semiconductor wafer polishing including optical monitoring |
| CN1340210A (en) * | 1999-10-13 | 2002-03-13 | 皇家菲利浦电子有限公司 | Method and system for polishing semiconductor wafers |
| CN1492213A (en) * | 2002-10-23 | 2004-04-28 | 台湾积体电路制造股份有限公司 | Method for measuring non-metal layer thickness in chemical and mechanical grinding process |
| CN101081488A (en) * | 2006-06-02 | 2007-12-05 | 联华电子股份有限公司 | Online control method of mixed type chemical mechanical buffing technics |
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