CN116504720A - Integration method of full-surrounding grid nano-sheet CMOS device - Google Patents

Integration method of full-surrounding grid nano-sheet CMOS device Download PDF

Info

Publication number
CN116504720A
CN116504720A CN202310535127.2A CN202310535127A CN116504720A CN 116504720 A CN116504720 A CN 116504720A CN 202310535127 A CN202310535127 A CN 202310535127A CN 116504720 A CN116504720 A CN 116504720A
Authority
CN
China
Prior art keywords
side wall
outer side
etching
medium
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310535127.2A
Other languages
Chinese (zh)
Inventor
黎明
施明旻
许晓燕
安霞
黄如
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University
Original Assignee
Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University filed Critical Peking University
Priority to CN202310535127.2A priority Critical patent/CN116504720A/en
Publication of CN116504720A publication Critical patent/CN116504720A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a full-surrounding grid nano-sheet CMOS device integration method, and belongs to the technical field of ultra-large scale integrated circuit manufacturing. After the dummy gate and the outer side wall are formed, a second outer side wall is formed, the second outer side wall and the Si/inner side wall at the lower part of the second outer side wall are etched and removed along the same interface by using a cyclic etching process through filling the same dielectric material as that of the second outer side wall in the concave inner side wall, and the final inner side wall is formed. Compared with the existing method for forming the inner side wall through the single outer side wall, the secondary outer side wall method provided by the invention has the advantages that the structural parameters of the inner side wall and the gate length are completely determined by the pseudo gate length, the thickness of the first outer side wall and the SiGe corrosion amount. And the structure formed in the N/P type region is kept consistent, so that the process difference and the inter-chip fluctuation between N/P type devices are effectively avoided.

Description

Integration method of full-surrounding grid nano-sheet CMOS device
Technical Field
The invention belongs to the technical field of ultra-large scale integrated circuit manufacturing, and particularly relates to a full-surrounding grid nano-sheet CMOS device integration method.
Background
With the continuous development of integrated circuit manufacturing technology, a nano-sheet device with a Gate-all-around (GAA) structure becomes a new generation of semiconductor devices with great potential.
Under the development state of continuous miniaturization of semiconductor device size, the process of device preparation has direct influence on device performance and reliability. The process preparation difficulty of the full-surrounding grid nano-sheet device is higher and higher, and part of key process steps have bottlenecks.
The process of forming the inner sidewall of the fully-surrounding gate nano-sheet device structure is one of the key steps of device integration. The inner side wall has direct influence on the parasitic resistance and parasitic capacitance of the device.
Currently, the main preparation method of the GAA inner sidewall forming process is to first perform source drain back etching after the dummy gate and the outer sidewall are formed, so as to expose the silicon (Si)/silicon germanium (SiGe) superlattice sidewall. Next, the SiGe is selectively etched using dry etching to form a local recess. Next, the dielectric material is filled using Chemical Vapor Deposition (CVD). And finally, removing redundant media covered on the side wall by dry anisotropic etching, and reserving the media filled in the concave as an inner side wall.
However, if the method is used to form the inner sidewall of the GAA nano-sheet device, the following problems occur:
(1) In order to ensure that the source and drain epitaxy is successful, the side wall needs to be subjected to natural oxide layer removal. The dielectric loss exists for the inner side wall structure, and when the thickness of the inner side wall is smaller, the short circuit of the source drain-gate electrode is easy to occur;
(2) In order to form N-P epitaxial source and drain, an epitaxial protection layer needs to be covered on an N-type region. After the epitaxy of the P-type device is finished, the protective layer needs to be completely removed, which may cause the inner side wall of the N-type device to be completely damaged. Therefore, a secondary sidewall process is required for the N-type devices, resulting in process variations and inter-wafer fluctuation between N/P-type devices.
Therefore, there is a strong need in the industry for a method of forming the interior sidewall of a boom nanosheet device.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a full-surrounding grid nanosheet CMOS device integration method, which is characterized in that the structural parameters of the inner side wall and the grid length of the device are completely determined by the length of a pseudo grid, the thickness of the side wall and the selective corrosion amount of SiGe.
The technical scheme provided by the invention is as follows:
the integration method of the full-surrounding grid nano-sheet CMOS device comprises the following steps:
A. providing a semiconductor substrate, and manufacturing a dummy gate for forming the GAA nano-sheet device according to the existing process, wherein the width of the dummy gate defines the channel length of the GAA nano-sheet device;
B. two outer side walls 1 and 2 are respectively formed on two sides of the pseudo gate; the specific implementation steps are as follows:
B1. depositing a layer of medium as an outer wall 1, wherein the thickness and the dummy gate width of the outer wall jointly define the superlattice structure retaining width in the source drain back etching step;
B2. depositing a layer of medium as an outer side wall 2; wherein, the etching selectivity of the medium in B2 and the medium in B1 is larger than 5:1, and the selectivity of the medium in B2 and the Si channel is smaller. The requirement on the deposition thickness of the outer side wall 2 is moderate, the removal of the outer side wall 2 and the inner side wall cannot be controlled stably due to the fact that the outer side wall 2 and the inner side wall cannot be thinned, the removal rate is slow due to the fact that the outer side wall is too thick, materials cannot be removed completely, and the like;
C. removing the superlattice of the source and drain regions exposed outside the outer side wall; the specific implementation steps are as follows:
C1. depositing a layer of medium as an etching mask to protect the dummy gate and the side wall structure;
C2. exposing a source drain back etching window through photoetching;
C3. removing the exposed Si/SiGe superlattice lamination by anisotropic etching, and etching to finish source drain back etching;
C4. selectively removing the dielectric layer in the C1;
D. selectively etching SiGe by isotropic etching to form an inner side wall recess; the depth of the concave is larger than the thickness of the outer side wall 2, and the width of the inner side wall is defined by the distance between the depth of the concave and the edge of the outer side wall 1;
wherein, the etching process should ensure that the selection ratio of SiGe to Si should be greater than 5:1;
E. filling the concave as an inner side wall by depositing a dielectric material;
wherein the dielectric material in E is the same as the dielectric material in B2;
F. removing the material of the outer side wall 2 of the P-type device region and the vertical downward part of the material to expose the Si channel;
the specific implementation steps are as follows:
F1. depositing a layer of hard mask medium, and etching the hard mask medium of the P-type device region by photoetching, so as to keep the hard mask medium of the N-type region;
F2. removing the inner side wall and the outer side wall 2 in the P-type device region by photoetching to expose the Si channel;
G. forming a source drain of a P-type device region and a protective layer thereof;
the specific implementation steps are as follows:
G1. removing the side wall natural oxide layer through wet etching;
G2. epitaxially growing dielectric layers on two sides of the exposed Si channel to form a device source drain and activating source drain impurities of the N/PMOS through an annealing process;
G3. a dielectric protective layer is deposited by chemical vapor deposition.
H. Removing the outer side wall 2 of the N-type device region to form an inner side wall structure consistent with the PMOS structure;
the specific implementation steps are as follows:
H1. removing the surface medium protective layer of the N-type device region by dry etching;
H2. depositing a layer of hard mask medium, etching the hard mask medium of the N-type device region by photoetching, and reserving the hard mask medium of the P-type region;
H3. removing the outer side wall 2 and the vertical downward part thereof in the N-type device region by photoetching to expose the Si channel;
H4. removing the side wall natural oxide layer through wet etching;
H5. epitaxially growing dielectric layers on two sides of the exposed Si channel respectively to form source and drain of the N-type device and activating source and drain impurities of the N/PMOS through an annealing process;
H6. depositing a dielectric protective layer through chemical vapor deposition to form an inner side wall structure consistent with the PMOS structure;
I. and finishing device integration according to the existing back-end process.
Further, the structural parameters (such as the thickness and material of the outer side wall 1 and the outer side wall 2, the corrosion depth, the thickness and material of the hard mask and the protective layer, etc.) are set according to the performance requirements of the specific device;
further, the semiconductor substrate in a includes bulk silicon substrate, SOI substrate, bulk germanium substrate, GOI substrate, compound substrate, etc.;
further, in the deposition step described in E, in order to ensure good interfacial properties, good thermal stability and chemical stability between dielectric materials, the deposition method is preferably Atomic Layer Deposition (ALD) with good conformality.
The invention has the following advantages and positive effects:
the preparation process has the following specific advantages:
1) Compared with the existing method for forming the inner side wall through the single outer side wall, the secondary outer side wall method provided by the invention can accurately control the sizes of the inner side wall and the grid. The structural parameters of the inner side wall and the gate length are completely determined by the length of the pseudo gate, the thickness of the outer side wall 1 and the corrosion amount of SiGe;
2) When the SiGe selective corrosion amount is larger than the second outside wall thickness, the invention has a very stable process window, and the structure formed in the N/P type region is kept consistent, so that the process difference and the fluctuation between sheets in the N/P type device are not caused, and one of the difficulties which are difficult to overcome by the process is solved.
Drawings
Is a schematic diagram of the process of the method for forming the inner side wall of the fence nano-sheet device. In each figure, (a) is a plan view, (B) is a sectional view taken along A-A 'in (a), and (c) is a sectional view taken along B-B' in (a).
Wherein:
FIG. 1 forms a GAA nanoplate device dummy gate;
FIG. 2 forms a secondary sidewall;
FIG. 3 removes the source drain portions;
FIG. 4 forms an interior sidewall recess;
FIG. 5 fills the recess to form an interior sidewall;
FIG. 6 forms a hard mask;
FIG. 7 is a hard mask covering the N-type region;
FIG. 8 removal of the second external sidewall of the P-type GAA nanoplatelet device by photolithography;
FIG. 9 forms the source and drain of a P-type GAA nanoplate device;
FIG. 10 illustrates the formation of a source drain protective layer;
FIG. 11 removes the N-type region hard mask;
FIG. 12 forms a P-type device hard mask;
FIG. 13 is a hard mask covering the P-type region;
FIG. 14 is a view of removing the second external sidewall of the N-type GAA nanoplatelet device by photolithography;
FIG. 15 forms the source drain of an N-type GAA nanoplate device;
FIG. 16 is a diagram of an N-type device source drain protection layer;
FIG. 17 removes the P device region hard mask;
fig. 18 is a diagram illustrating fig. 1 to 17.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples.
The N/P integration of GAA nanoplatelet devices can be achieved according to the following steps:
1) Forming 3 cycles of Si/SiGe superlattice and SiO on a (100) bulk silicon substrate in accordance with a disclosed bulk silicon process 2 Shallow trench isolation (Shallow Trench Isolation, STI), surface planarization by Chemical-mechanical polishing (Chemical-Mechanical Polishing, CMP), and formation of 6nm thick dummy gate by one-step lithography, as shown in fig. 1; the dummy gate width defines the channel length of the GAA nanoplate device.
2) Forming 9nm thick Si on both sides of the dummy gate by PECVD deposition 3 N 4 A first outer side wall 1; the thickness of the outer side wall 1 and the width of the dummy gate are defined in the source and drainThe superlattice structure of the back etching step remains wide.
3) Depositing the surface of the first outer side wall 1 by PECVD to form 3nm thick SiOC as a second outer side wall 2, as shown in figure 2; the etching selection ratio of the dielectric material adopted by the outer side wall 2 to the dielectric material adopted by the outer side wall 1 is larger than 5:1, and the selection ratio of the dielectric material adopted by the outer side wall 2 to the Si channel is smaller.
4) The Si/SiGe superlattice in the source and drain regions exposed outside the second outer sidewall 2 is removed by photolithography and anisotropic etching, as shown in FIG. 3.
5) Selectively etching the superlattice material SiGe by isotropic etching to an etching depth of 6nm to form an inner side wall recess, as shown in FIG. 4; the etching process should ensure that the selectivity of SiGe to Si should be greater than 5:1, the recess depth should be greater than the thickness of the outer sidewall 2, and the recess depth and the edge distance of the outer sidewall 1 define the width of the inner sidewall.
6) SiOC was deposited by ALD to a thickness of 6nm, filling the recesses to form the interior sidewalls, as shown in FIG. 5.
1) Depositing SiCN by PECVD, covering the whole device surface as a hard mask, as shown in figure 6;
2) Removing SiCN on the surface of the P-type device region by photoetching, as shown in FIG. 7;
3) Removing the SiOC external side wall with the thickness of 3nm and the vertical downward part of the P-type device by photoetching and anisotropic etching to expose Si channels, as shown in figure 8;
4) After removing the side wall natural oxide layer by wet etching, the epitaxy is carried out, and N-type doped SiGe with the thickness of 6nm is grown on the two sides of the exposed Si channel respectively to form the source drain of the P-type device, as shown in figure 9;
5) Activating source and drain impurities of the N/PMOS through an annealing process;
6) Depositing a layer of Si with the thickness of 2nm on the surface of the source drain by LPCVD to form the source drain protection of the P-type device, as shown in figure 10;
7) Removing the SiCN hard mask on the surface of the N-type device by dry etching, as shown in FIG. 11;
8) Depositing SiCN by PECVD, covering the whole device surface as a hard mask, as shown in figure 12;
9) Removing SiCN on the surface of the N-type device region by photoetching, and covering the surface of the P-type region with a hard mask as a protective layer, as shown in FIG. 13;
10 Removing the SiOC external side wall with the thickness of 3nm and the vertical downward part of the SiOC external side wall of the N-type device by photoetching and anisotropic etching to expose Si channels, as shown in figure 14;
11 After removing the side wall natural oxide layer by wet etching, respectively growing 6nm thick P-type doped SiGe on two sides of the exposed Si channel to form a source drain of an N-type device, as shown in figure 15;
12 Activating source-drain impurities of the N/PMOS through an annealing process;
13 A layer of Si with the thickness of 2nm is deposited on the surface of the source drain by LPCVD to form the source drain protection of the P-type device, as shown in figure 16;
14 Removing SiCN hard mask on the surface of the N type device by dry etching, as shown in figure 17; forming an inner side wall structure consistent with the PMOS structure;
15 Subsequent device integration is completed according to the disclosed back-end process.
The examples of the present invention are not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (8)

1. The integration method of the full-surrounding grid nano-sheet CMOS device comprises the following steps:
A. providing a semiconductor substrate, and manufacturing a dummy gate for forming the GAA nano-sheet device according to the existing process, wherein the width of the dummy gate defines the channel length of the GAA nano-sheet device;
B. respectively depositing dielectric materials on two sides of the pseudo gate to form two outer side walls, namely an outer side wall 1 and an outer side wall 2;
C. removing the superlattice of the source and drain regions exposed outside the outer side wall;
D. selectively etching SiGe by isotropic etching to form an inner side wall recess; the depth of the concave is larger than the thickness of the outer side wall 2, and the width of the inner side wall is defined by the distance between the depth of the concave and the edge of the outer side wall 1;
E. filling the concave as an inner side wall by depositing a dielectric material; the dielectric material is the same as that adopted by the outer side wall 2;
F. removing the material of the outer side wall 2 of the P-type device region and the vertical downward part of the material to expose the Si channel;
G. forming a source drain of a P-type device region and a protective layer thereof;
H. removing the outer side wall 2 of the N-type device region to form an inner side wall structure consistent with the PMOS structure;
I. and finishing device integration according to the disclosed back-end process.
2. The method for integrating the full-surrounding-gate nano-sheet CMOS device according to claim 1, wherein the implementation step B is as follows:
B1. depositing a layer of medium as an outer wall 1, wherein the thickness and the dummy gate width of the outer wall jointly define the superlattice structure retaining width in the source drain back etching step;
B2. depositing a layer of medium as an outer side wall 2; wherein the medium in B2 should have an etch selectivity of greater than 5:1 with the medium in B1.
3. The method for integrating the full-surrounding-gate nano-sheet CMOS device according to claim 1, wherein the implementation step C is as follows:
C1. depositing a layer of medium as an etching mask to protect the dummy gate and the side wall structure;
C2. exposing a source drain back etching window through photoetching;
C3. removing the exposed Si/SiGe superlattice lamination by anisotropic etching, and etching to finish source drain back etching;
C4. and selectively removing the dielectric layer in C1.
4. The method for integrating the full-surrounding-gate nano-sheet CMOS device according to claim 1, wherein the implementation step F is as follows:
F1. depositing a layer of hard mask medium, and etching the hard mask medium of the P-type device region by photoetching, so as to keep the hard mask medium of the N-type region;
F2. and removing the inner side wall and the outer side wall 2 in the P-type device region by photoetching, and exposing the Si channel.
5. The method for integrating the full-surrounding-gate nano-sheet CMOS device according to claim 1, wherein the step G) is specifically implemented as follows:
G1. removing the side wall natural oxide layer through wet etching;
G2. epitaxially growing dielectric layers on two sides of the exposed Si channel to form a device source drain and activating source drain impurities of the N/PMOS through an annealing process;
G3. a dielectric protective layer is deposited by chemical vapor deposition.
6. The method for integrating the full-surrounding-gate nano-sheet CMOS device according to claim 1, wherein the implementation step H is as follows:
H1. removing the surface medium protective layer of the N-type device region by dry etching;
H2. depositing a layer of hard mask medium, etching the hard mask medium of the N-type device region by photoetching, and reserving the hard mask medium of the P-type region;
H3. removing the outer side wall 2 and the vertical downward part thereof in the N-type device region by photoetching to expose the Si channel;
H4. removing the side wall natural oxide layer through wet etching;
H5. epitaxially growing dielectric layers on two sides of the exposed Si channel respectively to form source and drain of the N-type device and activating source and drain impurities of the N/PMOS through an annealing process;
H6. and depositing a dielectric protective layer by chemical vapor deposition to form an inner side wall structure consistent with the PMOS structure.
7. The method of claim 1, wherein the semiconductor substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, a GOI substrate, or a compound substrate.
8. The method of claim 1, wherein the depositing in step E is by atomic layer deposition ALD.
CN202310535127.2A 2023-05-12 2023-05-12 Integration method of full-surrounding grid nano-sheet CMOS device Pending CN116504720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310535127.2A CN116504720A (en) 2023-05-12 2023-05-12 Integration method of full-surrounding grid nano-sheet CMOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310535127.2A CN116504720A (en) 2023-05-12 2023-05-12 Integration method of full-surrounding grid nano-sheet CMOS device

Publications (1)

Publication Number Publication Date
CN116504720A true CN116504720A (en) 2023-07-28

Family

ID=87322912

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310535127.2A Pending CN116504720A (en) 2023-05-12 2023-05-12 Integration method of full-surrounding grid nano-sheet CMOS device

Country Status (1)

Country Link
CN (1) CN116504720A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117476466A (en) * 2023-11-02 2024-01-30 北京大学 Preparation method of bottom dielectric isolation, semiconductor structure, device and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117476466A (en) * 2023-11-02 2024-01-30 北京大学 Preparation method of bottom dielectric isolation, semiconductor structure, device and electronic equipment

Similar Documents

Publication Publication Date Title
US10868186B2 (en) FinFETs with source/drain cladding
US10083874B1 (en) Gate cut method
US8039332B2 (en) Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit
US10236214B2 (en) Vertical transistor with variable gate length
US10396206B2 (en) Gate cut method
US8829617B2 (en) Uniform finFET gate height
US7749829B2 (en) Step height reduction between SOI and EPI for DSO and BOS integration
CN102751229B (en) Fleet plough groove isolation structure, its manufacture method and the device based on this structure
CN105793968A (en) Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
US11469146B2 (en) Methods of performing fin cut etch processes for FinFET semiconductor devices
US10199392B2 (en) FinFET device having a partially dielectric isolated fin structure
TW201711157A (en) Interconnection structure, fabricating method thereof, and semiconductor device using the same
US20150123211A1 (en) NARROW DIFFUSION BREAK FOR A FIN FIELD EFFECT (FinFET) TRANSISTOR DEVICE
TW201913748A (en) Methods for forming semiconductor devices
CN112750771A (en) Fin end gate structure and method of forming the same
CN116504720A (en) Integration method of full-surrounding grid nano-sheet CMOS device
US11610980B2 (en) Method for processing a FinFET device
US11888064B2 (en) Semiconductor device and method
CN113823599A (en) Method for protecting semiconductor material in active region of transistor device and transistor device
US10008582B2 (en) Spacers for tight gate pitches in field effect transistors
CN104103506B (en) Method, semi-conductor device manufacturing method
US20240145591A1 (en) Vertical mosfet device, manufacturing method and application thereof
WO2023035366A1 (en) Semiconductor structure and preparation method therefor
WO2023065492A1 (en) Semiconductor structure and method for forming same
EP4199113A1 (en) A method for forming a semiconductor device structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination