CN107305859B - Manufacturing method of deep trench structure, semiconductor device and electronic device - Google Patents
Manufacturing method of deep trench structure, semiconductor device and electronic device Download PDFInfo
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- CN107305859B CN107305859B CN201610240670.XA CN201610240670A CN107305859B CN 107305859 B CN107305859 B CN 107305859B CN 201610240670 A CN201610240670 A CN 201610240670A CN 107305859 B CN107305859 B CN 107305859B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Abstract
The invention provides a manufacturing method of a deep trench structure, a semiconductor device and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, forming a first groove in the semiconductor substrate, and forming a gap wall on the side wall of the first groove; forming a second trench in the semiconductor substrate below the first trench; forming an oxide layer on the surface of the second trench and a part of the side wall of the first trench close to the second trench by a thermal oxidation method, so that the part of the gap wall close to the second trench is inclined and closes the second trench; filling the first trench. The manufacturing method can form a deep groove structure with good filling and has higher pressure resistance. The semiconductor device and the electronic device have good process stability and pressure resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a deep trench structure, a semiconductor device and an electronic device.
Background
With the development of semiconductor process technology, deep trench structures are widely used in the current semiconductor technology. Trenches having a depth of 10 μm or more are generally called deep trenches. Deep trench structures have a wide variety of applications, for example, deep trenches can be used as isolation structures to isolate electronic devices with different operating voltages. As another example, the deep trench can be applied to a super junction MOS transistor (super junction MOSFET) as a PN junction to achieve high breakdown voltage performance through charge balance of a depletion state.
At present, a method for manufacturing a deep trench structure includes the following steps: firstly, forming a deep groove, and forming side wall protection on the side wall of the deep groove through thermal oxidation for transverse isolation of a device; and then filling the deep trench isolation with polysilicon. However, the current manufacturing method of the deep trench structure has the following disadvantages: 1) due to the large aspect ratio of the deep trench, there are gaps between the filled polysilicon as shown in fig. 1A, and these gaps are recrystallized in the following thermal process to form unevenly distributed polysilicon grains as shown in fig. 1B. 2) The stability of the filling process is poor.
Therefore, it is necessary to provide a new manufacturing method to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a deep trench structure, which can avoid the existence of gaps and unevenly distributed crystal grains in a filling material and improve the process stability.
In order to overcome the existing problems, the invention provides a method for manufacturing a deep trench structure, which comprises the following steps: providing a semiconductor substrate, forming a first groove in the semiconductor substrate, and forming a gap wall on the side wall of the first groove; forming a second trench in the semiconductor substrate below the first trench; forming an oxide layer on the surface of the second trench and a part of the side wall of the first trench close to the second trench by a thermal oxidation method, so that the part of the gap wall close to the second trench is inclined and closes the second trench; filling the first trench.
Further, the step of forming a spacer on the sidewall of the first trench includes: forming a spacer material layer on the side wall and the bottom of the first groove and on the surface of the semiconductor substrate; and etching the gap wall material layer to form the gap wall.
Further, the material of the gap wall is silicon nitride.
Further, a closed second groove forms a gap, and the cross section of the second groove is circular or oval.
According to the manufacturing method of the deep trench structure, the second trench is formed below the first trench, and then the oxide layer is formed on the surface layer of the second trench, so that on one hand, the oxide layer is formed to drive the gap walls on the side walls of the first trench to be close to each other and seal the second trench together with the oxide layer, and on the other hand, the oxide layer on the surface of the second trench and the gap walls on the side walls of the first trench can be better isolated in the transverse direction, so that the depth of the first trench can be relatively reduced, and therefore the filling effect and the stability are improved due to the reduction of the depth-to-width ratio when the first trench is.
Another aspect of the present invention provides a semiconductor device, including: the semiconductor substrate is provided with a first groove and a second groove which is positioned below the first groove, a gap wall is formed on the side wall of the first groove, an oxide layer is formed on the surface of the second groove, the part of the gap wall, which is close to the second groove, is obliquely arranged, the second groove is sealed by the oblique gap wall and the oxide layer, and the first groove is filled with a conductive material/a dielectric material.
Further, the material of the gap wall is silicon nitride.
Further, a closed second groove forms a gap, and the cross section of the second groove is circular or oval.
According to the semiconductor device provided by the invention, the spacer is formed on the side wall of the first groove, the oxide layer is formed on the side wall of the part, close to the second groove, of the first groove and the surface of the second groove, so that the transverse isolation can be better realized, the part, close to the second groove, of the spacer is obliquely arranged and seals the second groove with the oxide layer, so that the first groove only needs to be filled subsequently, the depth of the first groove can be reduced due to the existence of the second groove, the depth and the width of the first groove can be well controlled, and the aspect ratio of the first groove is relatively reduced due to the oblique arrangement of the spacer, so that the good filling is easy to realize, the process stability is improved, and the pressure resistance of the device is improved.
Still another aspect of the present invention provides an electronic device including a semiconductor device and an electronic component connected to the semiconductor device, the semiconductor device including: the semiconductor device includes a semiconductor substrate having a first trench and a second trench below the first trench formed therein, a spacer formed on a sidewall of the first trench, an oxide layer formed on a surface of the second trench, a portion of the spacer being inclined to enclose the second trench, and the first trench being filled with a conductive material/a dielectric material.
Further, the material of the gap wall is silicon nitride.
Further, a closed second groove forms a gap, and the cross section of the second groove is circular or oval.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A illustrates filling a thin gap in polysilicon in a prior art deep trench structure;
FIG. 1B illustrates the non-uniform distribution of grains in polysilicon in a prior deep trench structure;
FIG. 2 is a flow chart illustrating steps of a method for fabricating a deep trench structure in accordance with an embodiment of the present invention;
FIGS. 3A to 3D are schematic cross-sectional views of the deep trench structure obtained by sequentially performing the steps according to the method for manufacturing the deep trench structure of the embodiment of the present invention;
fig. 4 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to solve the problems and overcome the defects that the conventional deep trench is easy to have fine slits and unevenly distributed grains, the invention provides a manufacturing method of a deep trench structure, which comprises the following steps: providing a semiconductor substrate, forming a first groove in the semiconductor substrate, and forming a gap wall on the side wall of the first groove; forming a second trench in the semiconductor substrate below the first trench; forming an oxide layer on the surface of the second trench and a part of the side wall of the first trench close to the second trench by a thermal oxidation method, so that the part of the gap wall close to the second trench is inclined and closes the second trench; filling the first trench.
The manufacturing method of the deep trench structure of the present invention, by forming the second trench under the first trench, then forming an oxide layer on the surface layer of the second groove and the partial side wall of the first groove close to the second groove, so that the part of the gap wall close to the second groove is inclined and closes the second groove, thereby on one hand, the oxide layer is formed to drive the gap walls on the side wall of the first groove to close to each other, and the partial gap walls are inclined, and the oxide layer together seal the second trench, on the other hand, the oxide layer on the surface of the second trench and the spacer on the sidewall of the first trench can better realize lateral isolation, thereby enabling the depth of the first trench to be relatively reduced, and because part of the gap wall of the first groove is inclined, the depth-to-width ratio of the first groove is relatively reduced, therefore, the filling effect and stability are improved due to the reduced aspect ratio when the first trench is filled subsequently.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
The method for fabricating the deep trench structure according to an embodiment of the present invention will be described in detail with reference to fig. 2 and fig. 3A to 3D.
First, step 201 is executed: providing a semiconductor substrate 300, forming a first trench 303 in the semiconductor substrate, and forming a spacer material layer 304 covering the surface of the semiconductor substrate 300 and the surface of the first trench 303, wherein the structure is as shown in fig. 3A.
Wherein, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
The first trench 303 is a deep trench, illustratively 15 μm deep, which is formed by: a pad oxide layer 301 on the semiconductor substrate 300, the pad oxide layer 301 being illustratively a silicon dioxide layer formed by a thermal oxidation method to a thickness of
As a stress buffer layer for a subsequent silicon nitride layer; forming a silicon nitride layer 302 on the underlying oxide layer 301, wherein the silicon nitride layer 302 is formed by a CVD method to have a thickness of
Protecting the active region in the subsequent deep trench filling, and serving as a barrier layer of the subsequent CMP; the pad oxide layer (pad oxide)301 and the silicon nitride layer 302 are etched, that is, the active region is patterned by a photolithography technique, the pad oxide layer 301 and the silicon nitride layer 302 are etched by a suitable method such as dry etching or wet etching, and then the semiconductor substrate 300 is etched by using the pad oxide layer 301 and the silicon nitride layer 302 as a mask to form the first trench 303.
Illustratively, in the present embodiment, in order to improve the selectivity of the subsequent processes, the spacer material layer 304 is made of silicon nitride, which may be formed by PVD, CVD, ALD, etc. methods commonly used in the art. Of course, the spacer material layer 304 is not limited to silicon nitride, but may be other suitable materials.
Next, step 202 is performed, the spacer material layer 304 is etched to form spacers 305 on the sidewalls of the first trench 303, and a second trench 306 is formed under the first trench 303, the structure is shown in fig. 3B.
Illustratively, in this embodiment, the spacer material layer 304 is first etched by a suitable etching process to remove a portion of the spacer material layer 304 above the silicon nitride layer 302 and at a bottom portion of the first trench 303, thereby forming a spacer 305 on a sidewall of the first trench 303. The etching process may be a wet etching process or a dry etching process, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The source gases for the dry etch may include CF4, CHF3, or other fluorocarbon gases.
Illustratively, in this implementation, the isolation structure 303 is etched back by using a dry etching process, and as an example, in this embodiment, the etching is dry etching, and process parameters of the dry etching include: the etching gas comprises CF4, CHF3, etc., the flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.
Then, the semiconductor substrate under the first trench 303 is etched using the spacer 305 as a mask to form a second trench 306 under the first trench 303. The etching process is performed by an isotropic etching process, such as an isotropic dry etching process or a wet etching process. The depth and shape of the second trench 306 is controlled, for example, by a mixture of hydrofluoric acid and nitric acid of appropriate concentrations, and by controlling the etching time. Illustratively, in the present embodiment, the second trench 306 has a circular or elliptical shape, so that its surface area is large.
Next, step 103 is executed to form an oxide layer 307 on the surface of the second trench 306 and a portion of the sidewall of the first trench by thermal oxidation, so as to incline a portion of the spacer of the first trench and close the second trench 306, and the formed structure is as shown in fig. 3C.
For example, in this embodiment, an oxide layer 307 is formed on the surface of the second trench 306 by a thermal oxidation method, for example, oxygen or an oxygen-containing substance is introduced into the second trench 306 while heating, silicon on the surface of the second trench 306 reacts with oxygen to convert into an oxide, and silicon at the interface between the first trench 303 and the second trench 306, that is, a part of the sidewall of the first trench 303 also reacts with oxygen to convert into an oxide, so that the spacers 306 on the sidewall of the first trench 303 are driven to approach each other due to the increase in volume after the silicon is converted into the oxide, so that the spacers below the trench are inclined, and together with the oxide layer 307 on the surface of the second trench, the second trench 306 is closed to form a void.
Finally, step 104 is performed to fill the first trench 303, and the resulting structure is as shown in fig. 3D.
Illustratively, in the present embodiment, the first trench 303 is filled with polysilicon 308 by PVD, CVD, ALD processes commonly used in the art, thereby forming a deep trench isolation structure.
It is understood that although in the present embodiment, the first trench 303 is filled with polysilicon, in other embodiments, other conductive materials or dielectric materials may be filled.
Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing the deep trench structure of the present embodiment may include not only the above steps, but also other required steps before, during, or after the above steps, such as a planarization step, a removal step of the bottom oxide layer 301 and the silicon layer 302, which are included in the scope of the manufacturing method of the present embodiment.
It can be understood that the method for manufacturing a deep trench structure provided by the present invention can be applied to various semiconductor devices requiring a deep trench structure, such as a deep trench isolation structure, or a deep trench capacitor.
In the method for manufacturing the deep trench structure of this embodiment, the second trench is formed below the first trench, and then the oxide layer is formed on the surface layer of the second trench and a portion of the sidewall of the first trench, so that on one hand, the oxide layer is formed to drive the spacers on the sidewall of the first trench to approach each other, so that a portion of the spacers is inclined, and the second trench is closed together with the oxide layer, and on the other hand, the oxide layer on the surface of the second trench and the spacers on the sidewall of the first trench can better achieve lateral isolation, so that the depth of the first trench can be relatively reduced, and the aspect ratio of the first trench is relatively reduced due to the inclination of the portion of the spacers of the first trench, so that the filling effect and stability are improved due to the reduction of the aspect ratio when the first trench is subsequently filled.
Furthermore, the second groove is circular or elliptical, so that the transverse area of the second groove is large, transverse isolation can be better realized, interference of adjacent devices is avoided, and the pressure resistance of the devices is improved.
In addition, in the method for manufacturing a semiconductor device according to this embodiment, the first trench portion spacer is formed by driving the first trench portion spacer to be inclined by increasing the volume of the second trench surface layer and the first trench portion sidewall in the oxidation process, and the process difficulty and the cost are much lower than those in the case of directly forming the inclined spacer.
Example two
The present invention also provides a semiconductor device, as shown in fig. 4, including: the semiconductor substrate 400 is provided with a first trench 401 and a second trench 402 below the first trench 401, a gap wall 403 is formed on the sidewall of the first trench 401, an oxide layer 404 is formed on the surface of the second trench 402 and on the sidewall of the first trench 401 near the second trench 402, the portion of the gap wall 403 near the second trench 402 is inclined, and closes the second trench 402 with the oxide layer 404, the closed second trench forms a gap, and the first trench 401 is filled with a conductive material/dielectric material 405.
Illustratively, the spacers 403 are silicon nitride.
Illustratively, the cross-section of the second trench 402 is circular or elliptical.
Further, the semiconductor device further comprises a layer of gate material 405 covering one of the third dielectric layers 403.
Wherein the semiconductor substrate 400 may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate 400 is monocrystalline silicon.
In the semiconductor device of the embodiment, the deep trench is divided into the first trench and the second trench, the spacer is formed on the sidewall of the first trench, the oxide layer is formed on the sidewall of the first trench close to the second trench and on the surface of the second trench to realize lateral isolation, the portion of the spacer close to the second trench is obliquely arranged, and the second trench is sealed by the oxide layer on the surface of the portion and the oxide layer on the surface of the second trench, so that the first trench only needs to be filled subsequently, the depth of the first trench can be reduced due to the existence of the second trench, the depth and the width of the first trench can be well controlled, and the portion of the spacer close to the second trench is obliquely arranged, so that the aspect ratio of the first trench is relatively reduced, good filling is easy to realize, the process stability is improved, and the pressure resistance of the device is improved.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor substrate is provided with a first groove and a second groove positioned below the first groove, a gap wall is formed on the side wall of the first groove, an oxide layer is formed on the surface of the second groove, the gap wall and the oxide layer close the second groove, the closed second groove forms a gap, and the first groove is filled with a conductive material/a dielectric material.
Further, the spacer is silicon nitride.
Further, the cross section of the second groove is circular or oval.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
The electronic device according to the embodiment of the present invention has the advantages described above because the semiconductor device described above is used.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method for manufacturing a deep trench structure is characterized by comprising the following steps:
providing a semiconductor substrate, forming a first groove in the semiconductor substrate, and forming a gap wall on the side wall of the first groove;
forming a second trench in the semiconductor substrate below the first trench;
forming an oxide layer on the surface of the second trench and a part of the side wall of the first trench close to the second trench by a thermal oxidation method, so that the part of the gap wall close to the second trench is inclined and the second trench is closed;
filling the first trench;
the manufacturing method reduces the difficulty and cost of the manufacturing process.
2. The method of claim 1, wherein the step of forming a spacer on the sidewall of the first trench comprises:
forming a spacer material layer on the side wall and the bottom of the first groove and on the surface of the semiconductor substrate;
and etching the gap wall material layer to form the gap wall.
3. The method as claimed in claim 1 or 2, wherein the spacer is made of silicon nitride.
4. The method of claim 1, wherein the closed second trench forms a void, and the cross section of the second trench is circular or elliptical.
5. A semiconductor device, comprising: a semiconductor substrate, wherein a first trench and a second trench located below the first trench are formed in the semiconductor substrate, a gap wall is formed on the side wall of the first trench, an oxide layer is formed on the surface of the second trench, the portion of the gap wall close to the second trench is obliquely arranged, the second trench is closed by the obliquely arranged gap wall and the oxide layer, and the first trench is filled with a conductive material/a dielectric material; the semiconductor device improves the process stability and the pressure resistance of the device.
6. The semiconductor device according to claim 5, wherein a material of the spacer is silicon nitride.
7. The semiconductor device according to claim 5 or 6, wherein the closed second trench forms a void, and the cross section of the second trench is circular or elliptical.
8. An electronic device comprising a semiconductor device and an electronic component connected to the semiconductor device, wherein the semiconductor device comprises: a semiconductor substrate, wherein a first trench and a second trench located below the first trench are formed in the semiconductor substrate, a gap wall is formed on the side wall of the first trench, an oxide layer is formed on the surface of the second trench, the portion of the gap wall close to the second trench is obliquely arranged, the second trench is closed by the obliquely arranged gap wall and the oxide layer, and the first trench is filled with a conductive material/a dielectric material; the electronic device improves the process stability and the pressure resistance of the device.
9. The electronic device of claim 8, wherein the material of the spacer is silicon nitride.
10. An electronic device according to claim 8 or 9, characterized in that a closed second trench forms the void, said second trench having a circular or elliptical cross-section.
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