JP2858383B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for eliminating crystal defects when forming a deep groove in a silicon substrate.

[0002]

2. Description of the Related Art Conventionally, there has been known a method of forming a monolithic semiconductor integrated circuit by forming a deep groove to separate elements. For example, JP-A-61-598
No. 52 discloses a method for manufacturing a semiconductor device in which an isolation groove is formed in a bonded SOI substrate to perform element isolation. According to this method, an oxide film is formed as a mask having a predetermined opening on a surface of an SOI substrate manufactured by bonding a pair of silicon substrates via an insulating film, and one silicon substrate is etched through the opening. Then, after forming the separation groove reaching the insulating film, and forming an insulating film on the surface of the separation groove and the one silicon substrate by thermal oxidation or the like, the separation groove is filled with polycrystalline silicon and protrudes from the separation groove. By removing the insulating film, the polycrystalline silicon, and the oxide film as the mask, an element region electrically completely separated from other regions by the separation groove and the insulating film is formed.

[0003]

By the way, the above-mentioned separation groove is generally formed by an R.R. I. E (Reactive Ion Et
(Ching) processing to form a silicon substrate by etching. This R. I. In the E treatment, a high frequency is applied to an electrode on which a silicon substrate is mounted to generate a cathode drop voltage (bias voltage), and ions and radicals as active particles generated by plasma discharge of a fluorine-based source gas are generated. The etching is performed by colliding with and reacting with a silicon substrate.

However, this R. I. When the separation groove is formed by the E treatment, the R.E. I. Since the E process involves a physical etching mechanism and is highly aggressive, crystal defects due to etching damage occur on the inner wall surface of the separation groove of the silicon substrate and the silicon substrate surface around the separation groove,
It causes current leakage. For the purpose of removing such crystal defects, sacrificial oxidation treatment or C.I. D. E (Chemical Dry Etchin)
g) applying treatment. Note that the sacrificial oxidation process is a process of forming an oxide film that reaches the depth at which a crystal defect exists on the inner wall surface of the isolation groove, and removing the oxide film by etching to eliminate the crystal defect. C.I.
D. The E process is a process in which a portion having a crystal defect is etched away only by a chemical etching mechanism having low aggressiveness by radicals of a source gas activated by plasma discharge.

However, the sacrificial oxidation treatment and C.I. D. E
It was found that the treatment was still insufficient to completely eliminate the crystal defects, and the inconvenience caused by the crystal defects was not sufficiently solved. SUMMARY OF THE INVENTION It is an object of the present invention to suitably eliminate crystal defects generated on the inner wall surface of a groove or the surface of a silicon substrate around the groove when a deep groove is etched, and to prevent current leakage of a semiconductor device.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a groove in a silicon substrate and the step of forming an inner wall surface of the groove with a C.I. D. E (Chemical Dry E)
tching) treatment; D. Annealing the inner wall surface of the E-treated groove.

The above C.I. D. The conditions for the E treatment are not particularly limited, but the damaged layer generated during the formation of the groove can be completely removed by etching. D. It is preferable that the condition is such that generation of a new damaged layer due to the E treatment is suppressed as much as possible. This C. D. By the E process, a depth of 2 to 5 times the depth of the damaged layer generated at the time of forming the groove is removed by etching.

[0008] The annealing treatment is performed according to C.I. D. E, the damaged layer that could not be removed by the treatment, and C.I. D. The condition is not particularly limited as long as the damaged layer newly generated by the E treatment can be recovered. For example, by heating at a temperature of 1000 to 1100 ° C. for about 10 to 30 minutes under an inert N ₂ atmosphere. It can be carried out.

[0009]

According to the method of manufacturing a semiconductor device of the present invention, C.I. D. By performing the E treatment, a damaged layer generated on the inner wall surface of the groove or the surface of the silicon substrate around the groove during the formation of the groove is sufficiently or completely removed. And C.I. D. By annealing the inner wall surface of the groove subjected to the E treatment, C.I. D. E, the damaged layer that could not be removed by the treatment, and C.I. D. The damage layer newly generated by the E treatment is recovered. This makes it possible to eliminate crystal defects on the inner wall surface of the groove and the silicon substrate surface around the groove.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. An example in which the manufacturing method of the present invention is applied to an isolation bipolar IC will be described. After one main surface of the P ^- type first silicon substrate 1 was mirror-polished, thermal oxidation was performed to form an insulating film 2 having a predetermined thickness. Then, this first insulating film 2 side of the silicon substrate 1, N has a mirror-polished main surface ^- contact the second silicon substrate 3 types under a sufficiently clean atmosphere and heated, each of the silicon substrate 1 and 3 were integrally joined so as to sandwich the insulating film 2. Thus, an SOI substrate constituted by bonding the second silicon substrate 3 on the first silicon substrate 1 via the insulating film 2 was manufactured. The N ⁺ -type high-concentration impurity layer 4 is formed on the second silicon substrate 3 by doping from the surface of the second silicon substrate 3 before joining.

Then, a deep N ⁺ region 7 is formed by a series of oxidation, photolithography, and impurity diffusion steps.
It was formed on a silicon substrate 3. Thereafter, an SiO ₂ film 8 is formed on the surface of the second silicon substrate 3 by thermal oxidation (see FIG. 1), and then, as shown in FIG. 2, the Si ₃ N ₄ film 9 and the CV
D-SiO ₂ films 10 were sequentially deposited. This CVD
The SiO ₂ film 10 functions as a mask member when the separation groove 11 is etched in a later step, and is etched away after the formation of the separation groove 11.

Next, a photolithography process and CF
₄ , R.F. using an etching gas containing CHF ₃ as a main component. I. E (Reactive Ion Etchin
g) A process is performed, and using the resist film formed on the surface of the CVD-SiO ₂ film 10 as a mask, the SiO ₂ film 8 and Si ₃
The N ₄ film 9 and the CVD-SiO ₂ film 10 are selectively etched until they reach the surface of the second silicon substrate 3 to form an opening. Then, the resist film is removed, and the CVD-SiO 2 film is removed.
And ₂ film 10 as a mask R. using an etching gas mainly composed of HBr I. The second silicon substrate 3 is selectively etched by E processing, and the separation groove 1 reaching the insulating film 2 is formed.
1 was formed (see FIG. 2).

Then, the CVD-SiO ₂ film 10 was removed by wet etching using a fluorine solution.
(See FIG. 3). Next, C.I. D. E
Processing was performed. This C. D. In the E treatment, a high-frequency discharge type plasma generator is used, and raw material gases: CF ₄ , N ₂ , O
₂ , frequency: 13.56 MHz, etching rate: 15
00 ° / min, distance from plasma to wafer: 1
The test was performed under the condition of 00 cm. As a result, the inner wall surface of the separation groove 11 was etched at about 1500 °.

Next, C.I. D. The inner wall surface of the E-treated separation groove 11 was annealed. This annealing treatment was performed by heating at a temperature of 1000 ° C. for 30 minutes in an N ₂ atmosphere. Next, a sacrificial oxidation treatment was performed on the inner wall surface of the separation groove 11 subjected to the annealing treatment. This sacrificial oxidation treatment is performed at 1000 ° C.
After forming a sacrificial oxide film of 500 ° by dry oxidation, the sacrificial oxide film was removed with hydrofluoric acid.

Then, 1050 ° C. is applied to the inner wall surface of the separation groove 11.
An insulating film 12 was formed by wet thermal oxidation of
After that, the polycrystalline silicon 13 was deposited on the separation groove 11 and the Si ₃ N ₄ film 9 by the LP-CVD method, and the separation groove 11 was filled with the polycrystalline silicon 13 (see FIG. 5). Next, after the polycrystalline silicon 13 deposited on the Si ₃ N ₄ film 9 was etched back by dry etching, an oxide film 14 was formed on the polycrystalline silicon 13 in the isolation groove 11 by thermal oxidation. (See FIG. 6).

Next, the Si ₃ N ₄ film 9 was removed by etching using phosphoric acid (see FIG. 7). Next, a field oxide film 15 is formed by a LOCOS oxidation method, and a P ⁺ base region 5 and an N ⁺ emitter region 6 are formed by a series of photolithography and impurity diffusion steps. Finally, an Al electrode 16 is formed to form a semiconductor. The device was manufactured (see FIG. 8). (Evaluation) In the above embodiment, after the insulating film 12 was formed on the inner wall surface of the separation groove 11, the insulating film 12, the SiO ₂ film 8 and the Si ₃ N ₄ film 9 were removed by etching.
Crystal defects were made obvious by the etching treatment, and the surface of the second silicon substrate 3 was observed with an optical microscope. And
The defect density was calculated by counting the defects observed in a square 200 μm on a side. FIG. 9 shows the result.

For comparison, C.I. D. E treatment and annealing treatment, annealing treatment only, annealing treatment and sacrificial oxidation treatment,
C. D. E-treated only, C.I. D. E and sacrificial oxidation, and C.I. D. The defect density was similarly examined for the samples subjected to the E treatment and the annealing treatment. The results are also shown in FIG. In FIG. 9,
The diagram connecting the plots of + shows the result of observing the vicinity of the center of the surface of the second silicon substrate 3, and the diagram connecting the plots of □ shows the result of observing the vicinity of the upper portion of the surface of the second silicon substrate 3, The diagram connecting the plots of △ is the second silicon substrate 3
The result of observing the vicinity of the lower part of the surface is shown.

As a result, C.I. D. In the case where the E treatment and the annealing treatment were not performed, or in the case where only one of the treatments was performed, the decrease in the defect density was not recognized, and the separation groove 1 was not observed.
Crystal defects were observed on the surface of the second silicon substrate 3 around No. 1. On the other hand, C.I. D. E, annealed and sacrificial oxidation, and C.I. D. Both of the samples subjected to the E treatment and the annealing treatment were able to eliminate crystal defects. As a result, at least C.I. D. It can be confirmed that crystal defects can be eliminated by performing the E treatment and the annealing treatment. In FIG. 9, the density of these defects is 10 ⁴ / cm ² , but this value is due to the measurement limit, and no crystal defects were actually observed. The measurement of the defect density was performed by observing only the surface of the second silicon substrate 3. As a result of observing the cross section of the second silicon substrate 3, the crystal defect on the inner wall surface of the separation groove 11 was found. Was also eliminated by the method of this embodiment.

As described above, according to the manufacturing method of this embodiment,
C. is formed on the inner wall surface of the isolation groove formed for element isolation. D. By performing the E treatment and the annealing treatment, it becomes possible to eliminate crystal defects on the inner wall surface of the separation groove and the silicon substrate surface around the separation groove, and to prevent current leakage due to the crystal defects. In the above embodiment, an example in which the present invention is applied to an isolation groove of an SOI substrate has been described. However, the present invention can be applied to a simple trench capacitor or a trench isolation of a silicon substrate.

[0020]

As described in detail above, the method of manufacturing a semiconductor device according to the present invention, when forming a separation groove, removes crystal defects that inevitably occur on the inner wall surface of the separation groove and the silicon substrate surface around the separation groove. , Followed by C.I. D. The problem can be solved by the E treatment and the subsequent annealing treatment, and it is possible to prevent the disadvantage of current leakage due to crystal defects.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a process chart illustrating a method for manufacturing a semiconductor device according to an example.

FIG. 3 is a process chart showing a method for manufacturing a semiconductor device of an example.

FIG. 4 is a process diagram illustrating a method for manufacturing a semiconductor device according to an example.

FIG. 5 is a process chart showing a method for manufacturing a semiconductor device of an example.

FIG. 6 is a process chart showing a method for manufacturing a semiconductor device of an example.

FIG. 7 is a process chart showing a method for manufacturing a semiconductor device of an example.

FIG. 8 is a process chart showing a method for manufacturing a semiconductor device of an example.

FIG. 9 is a diagram showing a result of measuring a defect density.

DESCRIPTION OF REFERENCE NUMERALS 1 denotes a first silicon substrate, 2 denotes an insulating film, 3 denotes a second silicon substrate, 11 denotes a separation groove, and 12 denotes an insulating film.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-166230 (JP, A) JP-A-56-51580 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/3065 H01L 21/324 H01L 21/76

Claims (1)

(57) [Claims] A step of forming a groove in a silicon substrate; D. E (Chemical Dr
y Etching) process; D. Annealing the inner wall surface of the E-treated groove.