JPS5861671A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent scraping-out below the poly-si film, leakage current and drop of dielectric strength by removing the etching proof mask after etching the poly-Si film up to the desired depth and thereafter by forming a thermal oxide film on the exposed surface of substrate. CONSTITUTION:The SiO2 film 2 and the poly-Si 3 are stacked on the quartz substrate 1. The poly-Si 3 is photo-etched using CF4 and it is left in the thickness of about 500Angstrom . The remaining poly-Si 3 in the thickness of 500Angstrom is perfectly converted to the SiO2 by covering it the gate film 4 in the thickness of about 1,000Angstrom through high temperature oxidation. Thereafter, the poly-Si 5 is precipitated in the thickness of about 3,000Angstrom on the gate film 4 and the gate oxide film 4 is etched through patterning. At this time, even if a fine flaw is generated on the gate oxide film 4, any scraping-out is not generated on the SiO2 film 2 in the periphery of the poly-Si 3. Thereafter, the source, drain are provided in the poly-Si by diffusing the N<+>, the PSG film used in such a process is etched, the surface is covered with the SiO2 6 and the Al-Si electrode is provided. According to this structure, since there is no scraping-out, any breakage of wiring does not occur and leakage or drop of dielectric strength can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to etching and surface treatment of polycrystalline silicon in semiconductor devices such as silicon gate transistors or thin film transistors.

As is well known, the range of applications of polycrystalline silicon films is expanding from silicon gate transistors to thin film transistors.

In particular, recently, a flat panel liquid crystal display has been reported that consists of an active matrix circuit formed by forming a polycrystalline silicon film on a glass or quartz plate, and is seen as a promising future as a low-cost display that can be made into an Osato panel. ing.

Conventionally, a polycrystalline silicon film is formed on an insulating film such as an oxide film formed on a substrate by decomposing SiH4 (monosilane gas) in a furnace at about 600°C. The purpose of forming this polycrystalline silicon film is generally for use as a gate electrode, wiring, or even for an N-film transistor.

The present invention is intended to prevent the so-called gouge state in the vicinity of the interface between the polycrystalline silicon film and the underlying insulating film, which conventionally occurs during pattern formation of the polycrystalline silicon film and subsequent surface treatment. The occurrence of gouges around the interface will be explained through the manufacturing process of thin film transistors.

FIG. 1 is a cross-sectional view showing the manufacturing process of a conventional general thin film transistor.

First, as shown in FIG.
The polycrystalline silicon crotch 3 is photo-etched using J-b to perform predetermined patterning, the exposed surface layer of the polycrystalline silicon film is thermally oxidized to form a gate film 4, and then the polycrystalline silicon film 5 is formed on the entire surface of the substrate. form sip.

Next, as shown in FIG. 1C, the polycrystalline silicon film 5 is photoetched, and the exposed gate oxide film 4 is removed. At this time, the OVD oxide film 2 at the interface of the first layer polycrystalline silicon film is underetched at the pattern periphery, causing gouges.

Naturally, this amount of gouge is larger than the amount of gouge in the peripheral portion of the pattern of gate oxide film 4 by the amount of excessive etching.

Next, phosphorus is diffused into the exposed first and second polycrystalline silicon films by a thermal diffusion method to form source, drain parts, etc.

Next, as shown in FIG. 1d, an OVD film 6 is formed on the entire surface of the substrate, contact holes are formed by photolithography, and metal wiring 7 is formed by sputtering an aluminum-silicon alloy.

As described above, in the conventional manufacturing method, after patterning the second layer polycrystalline silicon film, there is always an etching process for the gate oxide film for the diffusion process, and for this etching, the first layer polycrystalline silicon film is etched. The area around the interface between the film and the OjD oxide film is hollowed out. Furthermore, since an etching step for removing the phosphor glass layer is added in the thermal diffusion step, the recess is further enlarged and a large space is created as shown in FIG. 3.

First, this gouge has an adverse effect on the coverage of the OVD oxide film in the subsequent process. Suppose this gouge part is OV
Even if covered by the D oxide film, it is impossible to completely fill this space, and the remaining gas causes cracks to occur at the stepped portions of the OVD oxide film during heat treatment in a subsequent step. Furthermore, the occurrence of cracks or incomplete step coverage causes the subsequent disconnection of the electrode arrangement, which not only lowers the initial yield but also adversely affects long-term reliability.

The same thing can be said about the gouges in the periphery of the gate s, but it is thought that these gouges may cause leaks in the transistor and lower the withstand voltage, so it is desirable to suppress gouges under the polycrystalline silicon film as much as possible. There is.

The present invention eliminates the drawbacks of the conventional method as described above and provides a method for preventing the polycrystalline silicon crotch from gouging, and will be described in detail below based on one embodiment.

FIGS. 2a to 2d are cross-sectional views of the substrate illustrating the manufacturing steps of the present invention in the order of the steps.

First, in FIG. 2 α, an OVD oxide film 2 of about 500X is coated on a quartz substrate. Furthermore, a first layer is placed on this OVD oxide film.
The polycrystalline silicon film of each layer is heated to approximately 600℃ in a low pressure OVD furnace.
The film is grown in a vapor phase to form a film with a thickness of 300X.

Next, as shown in FIG. 2, the first polycrystalline silicon film 3 is processed by photolithography.

In this step, the polycrystalline silicon film was etched by a dry etching method, and C74 (Freon) was used as the reaction gas. Furthermore, the etching in this process is
A method was adopted in which the etching was not performed until the OVD oxide film was exposed, and the etching was stopped at the shoulder where approximately 5001 of the polycrystalline silicon film remained.

At this time, the remaining film thickness can be controlled by experimentally determining the plasma output, Freon gas amount, etching time, etc.

Next, about 10,000 layers of gate film 4 are formed on the surface of the exposed polycrystalline silicon film by dry oxidation at 1100° C. for 50 minutes.

At this time, about 50% of the polycrystalline silicon film left in the above step
001 is completely oxidized and becomes an insulating film.

Subsequently, a second layer polycrystalline silicon alloy film 5ooo1 is formed on the gate film 4.

Next, as shown in FIG. 2C, the polycrystalline silicon film 5 is photoetched to form a predetermined pattern, and then the exposed gate oxide film is etched using the polycrystalline silicon pattern as a mask.

At this time, underetching occurs in the peripheral area of the gate film in an amount corresponding to the thickness of the gate film, but the amount is only a slight gouge.

However, it is in contact with the peripheral portion of the pattern of the first JI polycrystalline silicon film. Since only the oxide film above the aVD oxide film is etched in the vDo film, it will hardly be etched unless excessive etching is performed.

In the process, N+g dispersion is then performed at 960° C. to form source and drain portions in the polycrystalline silicon i.

At this time, the phosphorus glass film formed on the substrate surface is removed by etching for a short time with diluted hydrofluoric acid.

Next, the entire exposed surface is covered with a CVD oxide film 6, and contact holes are opened.

Further, an aluminum silicon alloy is sputtered to form electrode wiring 7.

As described above, in the present invention, when etching a polycrystalline silicon film, a small amount of the polycrystalline silicon film remains on the etched surface, and this polycrystalline silicon film is thermally oxidized in the next step to form a complete film, thereby preventing oxidation in the subsequent step. This prevents gouge development of the field film due to the film etching process, and also reduces the level difference between the field film and the polycrystalline silicon film, which is particularly effective in preventing disconnection of electrode wiring.

In the embodiments of the present invention, a method for manufacturing a thin film transistor using a polycrystalline silicon film is shown, and an example of application to the first layer of polycrystalline silicon film is shown. When processing a crystalline silicon film, the present invention can also be applied to the second layer polycrystalline silicon film in the above embodiment.

In particular, when applied to a polycrystalline silicon film on a gate oxide film, it has been proven that it not only has the effect of preventing wire breakage, but also has a great effect on leakage development of transistors caused by gouge development, reduction in breakdown voltage, etc.

[Brief explanation of the drawing]

FIGS. 1(α) to Cd) are cross-sectional views showing the manufacturing process of a conventional thin film transistor using a polycrystalline silicon film. FIGS. 2(cL) to 2(cd) are cross-sectional views showing the manufacturing process of a WljN transistor to which the present invention is applied. FIG. 3 is a cross-sectional view showing the erosion phenomenon of the field oxide film that occurs during the conventional manufacturing process, and is an enlarged view of section (A) in FIG. 1J. FIG. 4 is a cross-sectional view showing that the field oxide film is not hollowed out due to the manufacturing process according to the present invention, and is an enlarged cross-sectional view of section CB in FIG. 2d. 1...Quartz substrate 2...CVD oxide film 3...Polycrystalline silicon film 4...Gate oxide film 5...Polycrystalline silicon Film 6...CVD oxide film 7...Aluminum silicon wiring

Claims (1)

[Claims] A process of selectively forming an etching-resistant film on the surface of the substrate, then etching the exposed polycrystalline silicon film to a desired depth using the etching-resistant film as a mask, and removing the etching-resistant film to remove the exposed polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising the steps of exposing an underlying polycrystalline silicon film and then forming a thermal oxide film on the exposed surface of the substrate.