JPH06163452A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device where damage is prevented from occurring at a joint of a semiconductor substrate, wherein the semiconductor device can be obtained at a low cost restraining a TAT from increasing as much a possible. CONSTITUTION:Polycrystalline silicon films 5 and 6 are formed on a gate electrode forming region and a contact hole forming region through the intermediary of an oxide film 3, an interlayer insulating film 7 is formed on all the surface and patterned to enable the surface of the polycrystalline silicon film 6 formed on the contact hole forming region to be exposed, then the exposed polycrystalline silicon film 6 is subjected to a plasma-less etching process with fluorine halide gas until the surface of the oxide film 3 is exposed, and the exposed oxide film 3 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which is characterized in that the occurrence of damage to a junction region of a semiconductor substrate is suppressed when a contact hole is formed. .

[0002]

2. Description of the Related Art Conventionally, MOS (Metal Oxide Semico)
In a semiconductor device having a transistor, a gate electrode is formed through an oxide film on a semiconductor substrate, and then an interlayer insulating film having a large film thickness is formed on the entire surface to correspond to a contact hole forming region of the interlayer insulating film. The contact hole is formed by removing the portion by etching.

According to this method, the interlayer insulating film having a considerably large film thickness and having a film thickness variation due to the step of the underlying layer is etched, and the selection ratio between the interlayer insulating film and the semiconductor substrate is increased. However, since there is a limit, there is a problem that the etching inevitably progresses to the semiconductor substrate during the etching. Here, the reason why the selection ratio between the interlayer insulating film and the semiconductor substrate is limited during the etching process for forming the contact hole is that etching with strong sputterability is required because it is necessary to open a fine contact hole. Because.

Further, with the miniaturization of the element, as the junction at the contact portion becomes shallower, there is a problem that the junction is broken through during the etching process for forming the contact hole. Therefore, the pillar method is introduced as a method for reducing the load due to etching for forming the contact hole.

In the pillar method, after forming a gate electrode via an oxide film on a semiconductor substrate, a thin interlayer insulating film is formed on the entire surface, and a portion of the interlayer insulating film corresponding to a contact hole forming region is formed. Are removed by etching to expose the semiconductor substrate in this portion. At this time, since the interlayer insulating film is thin, the semiconductor substrate is hardly etched. Next, a wiring layer is deposited on the entire surface and patterned to form a pillar made of the wiring layer on the exposed semiconductor substrate (on the contact hole formation region). Next, after forming a thick interlayer insulating film on the entire surface, the interlayer insulating film is etched back until the surface of the pillar made of the wiring layer is exposed. Next, a wiring layer is further deposited on the entire surface, and this is patterned to form a wiring that is connected to the semiconductor substrate via the pillar made of the wiring layer.

[0006]

However, while the pillar method can suppress the occurrence of damage at the contact bonding portion of the semiconductor substrate, the number of times the wiring layer is formed and the number of times the interlayer insulating film is formed are reduced. As the number of TAT (Turn Around) increases, the film formation process becomes complicated and the cost increases.
There was a problem that Time) deteriorated significantly.

Further, when forming a pillar made of a wiring layer,
As wiring material, aluminum, aluminum alloy, etc.
If a metal with a relatively low melting point is used, it is necessary to keep the deposition temperature of the interlayer insulating film that will be formed later considerably low.
There is also a problem of deteriorating the deposition conditions of the interlayer insulating film. An object of the present invention is to solve such a problem, and to obtain a semiconductor device in which damage is prevented from occurring at a bonding portion of a semiconductor substrate at a low cost while suppressing an increase in TAT as much as possible. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of performing the above.

[0008]

In order to achieve this object, the present invention provides a first step of forming a polycrystalline silicon film via an oxide film in a gate electrode formation region and a contact hole formation region on a semiconductor substrate. And a second step of forming an interlayer insulating film on the oxide film surface and the polycrystalline silicon film surface,
A third step of patterning the interlayer insulating film to expose the surface of the polycrystalline silicon film formed in the contact hole formation region, and halogenating the exposed polycrystalline silicon film until the surface of the oxide film is exposed. A method for manufacturing a semiconductor device, comprising: a fourth step of performing plasmaless etching using fluorine gas; and a fifth step of removing the exposed oxide film.

[0009]

According to the present invention, a polycrystalline silicon film is formed on a gate electrode forming region and a contact hole forming region on a semiconductor substrate via an oxide film, and then an interlayer insulating film is formed on the entire surface and patterned. Then, the surface of the polycrystalline silicon film formed in the contact hole formation region is exposed, and the exposed polycrystalline silicon film is subjected to plasmaless etching using a fluorine fluoride gas until the surface of the oxide film is exposed. After that, by removing the exposed oxide film, the increase in TAT can be suppressed as much as possible without causing damage to the semiconductor substrate, and the contact hole can be formed at low cost.

That is, under the appropriate conditions, the fluorine fluoride gas hardly etches a dense oxide film having a low hydrogen content (silicon oxide film) such as a thermal oxide film, and does not etch a silicon single crystal or a polycrystal. It has the property of etching the crystalline silicon film. Therefore, only the polycrystalline silicon film is etched without damaging the underlying oxide film. Also, the exposed oxide film is thin,
When removing this, the semiconductor substrate is not damaged. Therefore, the contact hole can be formed without causing damage to the bonded portion of the semiconductor substrate.

Further, the plasmaless etching performed on the exposed polycrystalline silicon film is etching without ion bombardment, and since the underlying oxide film is not etched at all, no damage occurs even in a very shallow junction. In addition, since no damage is generated in the joint portion of the semiconductor substrate, it is not necessary to increase the diameter of the contact hole, which can contribute to high integration.

Since the exposed polycrystalline silicon film has a certain thickness, it is adversely affected even if the surface thereof is slightly damaged by the etching performed when patterning the interlayer insulating film. Never. Furthermore, in the method of manufacturing a semiconductor device according to the present invention, the steps of forming a polycrystalline silicon film and forming an interlayer insulating film do not increase. Further, the etching process performed when opening the contact hole includes two processes of etching the interlayer insulating film and etching the exposed polycrystalline silicon film. The etching of the polycrystalline silicon film is
Batch processing is possible, and etching from the interlayer insulating film can be continuously performed. Therefore, the etching process does not become complicated, the manufacturing cost does not increase, and the increase in TAT can be minimized.

Further, the interlayer insulating film formed on the contact hole forming region can be thinned because the polycrystalline silicon film is formed, and the flattening of the interlayer insulating film is improved. You can also Therefore, the step coverage of the wiring layer formed later can be improved.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 8 are partial cross-sectional views showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention. In the step shown in FIG. 1, after the field oxide film 2 is formed in the element isolation region on the semiconductor substrate 1 by a known method, the thin oxide film 3 is formed on the surface of the semiconductor substrate 1. Next, on the field oxide film 2 and the oxide film 3,
A polycrystalline silicon film 4 having a film thickness of about 3500Å is formed.

Next, in the step shown in FIG. 2, the polycrystalline silicon film 4 obtained in the step shown in FIG. 1 is subjected to desired patterning to form the polycrystalline film formed in regions other than the gate electrode forming region and the contact hole forming region. The silicon film 4 is removed. In this way, the gate electrode 5 is formed in the gate electrode formation region.
A polycrystalline silicon pillar 6 was formed in the contact hole formation region.

Next, in the step shown in FIG. 3, the surface of the gate electrode 5 and the polycrystalline silicon pillar 6 obtained in the step shown in FIG.
An interlayer insulating film 7 is formed on the surface of, the oxide film 3 and the field oxide film 2. At this time, since the interlayer insulating film 7 formed in the contact hole forming region is formed on the polycrystalline silicon pillar 6, the film thickness can be reduced by that amount. Therefore, the planarization of the interlayer insulating film 7 can be improved, and the step coverage of the wiring layer to be formed later can be improved.

Next, in the step shown in FIG. 4, after applying a photoresist on the interlayer insulating film 7 obtained in the step shown in FIG. 3, a portion corresponding to the contact hole forming region of the photoresist is selectively selected. Then, the resist pattern 8 is formed. Next, in the step shown in FIG. 5, anisotropic etching is performed until the surface of the polycrystalline silicon pillar 6 is exposed using the resist pattern 8 obtained in the step shown in FIG. 4 as a mask. At this time, since the polycrystalline silicon pillar 6 has a certain thickness, there is no problem even if it is over-etched.

Next, in the step shown in FIG. 6, ClF ₃ (chlorine trifluoride gas) as a halogenated fluorine gas is added to the polycrystalline silicon pillar 6 exposed in the step shown in FIG.
Plasma-less etching is performed by using a gas diluted to 1 to 100% with ₂ (nitrogen) at a pressure of 1 to 100 Torr and a temperature of 17 to 50 ° C. to expose the oxide film 3. At this time, the gas used in the plasmaless etching process is such that the oxide film 3 which is dense and has a low hydrogen content hardly etches under proper conditions and etches the polycrystalline silicon pillars 6. Only the polycrystalline silicon pillars 6 are etched without damaging the pillars 3. Furthermore, the plasma-less etching performed on the exposed polycrystalline silicon pillar 6 is etching without ion bombardment, and since the underlying oxide film 3 is not etched at all, no damage occurs even in a very shallow junction.

Next, in the step shown in FIG. 7, the oxide film 3 exposed in the step shown in FIG. 6 is removed to form a contact hole 9. At this time, the oxide film 3 has a small film thickness, so that when the oxide film 3 is removed, no damage occurs in the bonding portion of the semiconductor substrate 1. Therefore, unlike the conventional case, it is not necessary to increase the diameter of the contact hole in consideration of the damage that occurs in the bonding portion of the semiconductor substrate 1, which can contribute to high integration. Further, the contact hole 9 could be obtained without increasing the number of steps for forming the polycrystalline silicon film 4 and the interlayer insulating film 7 (one film formation each). Next, after removing the resist pattern 8, a wiring layer 10 is formed on the interlayer insulating film 7 and the exposed semiconductor substrate 1.

Next, in the step shown in FIG. 8, the wiring layer 10 obtained in the step shown in FIG. 7 was subjected to desired patterning to form the wiring 11 connected to the semiconductor substrate 1. Then, desired steps are performed to complete the semiconductor device. In addition, in the present embodiment, a gas obtained by diluting ClF ₃ with N ₂ to 1 to 100% was used as the halogenated fluorine gas, but the present invention is not limited to this, and a halogenated fluorine gas composed of other components may be used. Good.

[0021]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after the polycrystalline silicon film is formed via the oxide film in the gate electrode formation region and the contact hole formation region on the semiconductor substrate, , Forming an interlayer insulating film on the entire surface,
By patterning this, the surface of the polycrystalline silicon film formed in the contact hole formation region is exposed, and plasma using a halogenated fluorine gas is exposed on the exposed polycrystalline silicon film until the surface of the oxide film is exposed. After the etching is performed, the exposed oxide film is removed, so that the junction of the semiconductor substrate is not damaged. Further, the plasma-less etching performed on the exposed polycrystalline silicon film is etching without ion bombardment, and since the underlying oxide film is not etched at all, no damage occurs even in a very shallow junction. Furthermore, the contact hole can be formed without increasing the steps of forming the polycrystalline silicon film and the interlayer insulating film. As a result, it is possible to provide a high-performance and inexpensive semiconductor device with improved reliability.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 oxide film 4 polycrystalline silicon film 5 gate electrode 6 polycrystalline silicon pillar 7 interlayer insulating film 8 resist pattern 9 contact hole 10 wiring layer 11 wiring

Claims (1)

[Claims] 1. A first step of forming a polycrystalline silicon film via an oxide film in a gate electrode formation region and a contact hole formation region on a semiconductor substrate, and an interlayer between the oxide film surface and the polycrystalline silicon film surface. A second step of forming an insulating film,
A third step of patterning the interlayer insulating film to expose the surface of the polycrystalline silicon film formed in the contact hole forming region, and halogenating the exposed polycrystalline silicon film until the surface of the oxide film is exposed. A method of manufacturing a semiconductor device, comprising: a fourth step of performing plasmaless etching using fluorine gas; and a fifth step of removing the exposed oxide film.