KR0147675B1 - Method for etching aluminum alloy film - Google Patents

Method for etching aluminum alloy film

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Publication number
KR0147675B1
KR0147675B1 KR1019950008662A KR19950008662A KR0147675B1 KR 0147675 B1 KR0147675 B1 KR 0147675B1 KR 1019950008662 A KR1019950008662 A KR 1019950008662A KR 19950008662 A KR19950008662 A KR 19950008662A KR 0147675 B1 KR0147675 B1 KR 0147675B1
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KR
South Korea
Prior art keywords
etching
alloy film
aluminum alloy
gas
semiconductor device
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KR1019950008662A
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Korean (ko)
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KR960039287A (en
Inventor
양대근
이상용
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문정환
엘지반도체주식회사
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Priority to KR1019950008662A priority Critical patent/KR0147675B1/en
Publication of KR960039287A publication Critical patent/KR960039287A/en
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Publication of KR0147675B1 publication Critical patent/KR0147675B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Abstract

본 발명은 반도체장치 제조시의 알루미늄합금막 식각방법에 관한 것으로, Al-Si-Cu합금막의 건식식각시 발생하는 Cu, Si등의 잔류물을 제거하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching aluminum alloy films during semiconductor device manufacturing, and to a method for removing residues such as Cu and Si generated during dry etching of Al-Si-Cu alloy films.

본 발명은 건식식각방법을 이용하여 알루미늄합금막을 식각하는 방법에 있어서, BCL3+Cl2가스를 이용한 건식식각하는 제1식각단계와 As 또는 As + XeF2가스를 이용한 스퍼터링에 의해 식각하는 제2식각단계를 병행하여 상기 알루미늄합금막을 식각하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법을 제공한다.In the method of etching an aluminum alloy film using a dry etching method, the first etching step of dry etching using BCL 3 + Cl 2 gas and the second etching by sputtering using As or As + XeF 2 gas An aluminum alloy film etching method of manufacturing a semiconductor device, comprising etching the aluminum alloy film in parallel with the etching step.

Description

반도체장치 제조시의 알루미늄합금막 식각방법Aluminum alloy film etching method in semiconductor device manufacturing

제1도는 종래기술에 의한 반도체장치의 금속배선 형성방법을 공정순서에 따라 도시한 단면구조도.1 is a cross-sectional structure diagram showing a metal wiring formation method of a semiconductor device according to the prior art according to a process sequence.

제2도는 종래기술에 의한 반도체장치의 금속배선 형성을 위한 알루미늄합금막의 식각공정 흐름도.2 is a flowchart of an etching process of an aluminum alloy film for forming a metal wiring of a semiconductor device according to the prior art.

제3도는 본 발명에 의한 반도체장치의 금속배선 형성방법을 공정순서에 따라 도시한 단면구조도.3 is a cross-sectional structural view showing a method for forming metal wirings in a semiconductor device according to the present invention in accordance with a process sequence.

제4도는 본 발명에 의한 반도체장치의 금속배선 형성을 위한 알루미늄 합금막의 식각공정 흐름도.4 is a flowchart illustrating an etching process of an aluminum alloy film for forming metal wirings of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 하지층 2 : 하부 장벽금속층1: base layer 2: lower barrier metal layer

3 : Al-Si-Cu합금막 4 : 상부 장벽금속층3: Al-Si-Cu alloy film 4: upper barrier metal layer

5 : 감광막 6 : 잔유물5: photosensitive film 6: residue

본 발명은 반도체장치 제조시의 알루미늄합금막 식각방법에 관한 것으로, 특히 Al-Si-Cu합금막의 건식식각시 발생하는 Cu, Si등의 잔류물을 제거하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an aluminum alloy film etching method in the manufacture of semiconductor devices, and more particularly to a method for removing residues such as Cu and Si generated during dry etching of an Al-Si-Cu alloy film.

종래기술에 의한 반도체장치의 금속배선 형성방법을 공정순서에 따른 단면구조를 나타낸 제1도 및 식각공정의 흐름도를 도시한 제2도를 참조하여 설명하면 다음과 같다.A method of forming a metal wiring of a semiconductor device according to the prior art will be described with reference to FIG. 1 showing a cross-sectional structure according to a process sequence and FIG. 2 showing a flowchart of an etching process.

먼저, 제1도 (a)에 도시된 바와 같이 기판(도시하지 않음)상에 형성된 하지층(1)(산화막과 같은 절연이거나 다층배선구조의 상부배선층을 형성할 경우에는 BPSG와 같은 평탄화층일 수 있다)상에 하부 장벽금속층(Barrier metal)(2)을 형성하고, 이 위에 금속배선 형성용 도전층으로서, Al-Si-Cu합금막(3)을 증착한 후, 그 상부에 상부 장벽금속층(4)을 형성하고 이 위에 감광막(5)을 도포한 다음, 상기 감광막을 선택적으로 노광 및 현상하여 형성하고자 하는 금속배선패턴에 따라 소정의 감광막패턴을 형성한다. 이어서 상기 감광막패턴을 마스크로 하여 상부 장벽금속층(4)을 F계(Fluorine base) 가스를 이용하여 수~수백mTorr의 압력범위내에서 RIE(Reactive Ion Etching)에 의해 식각한다(제2도 A단계).First, as shown in FIG. 1A, the base layer 1 (not shown) formed on a substrate (not shown) may be a planarization layer such as BPSG when forming an insulating layer such as an oxide film or an upper wiring layer of a multilayer wiring structure. A lower barrier metal layer 2 is formed thereon, and an Al—Si—Cu alloy film 3 is deposited thereon as a conductive layer for forming metal wiring thereon, and then the upper barrier metal layer 3 is formed thereon. 4) and the photoresist film 5 is applied thereon, and then the photoresist film is selectively exposed and developed to form a predetermined photoresist pattern according to the metal wiring pattern to be formed. Subsequently, using the photoresist pattern as a mask, the upper barrier metal layer 4 is etched by using reactive ion etching (RIE) within a pressure range of several to several hundred mTorr using F-based (Fluorine base) gas (FIG. ).

이어서 제1도 (b)에 도시된 바와 같이 상기 감광막패턴 및 상부 장벽금속층(4)을 마스크로 하여 Al-Si-Cu합금막(3)을 BCl3+Cl2계 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 RIE에 의해 식각(제2도 B단계)한다. 이때, Al-Si-Cu합금막(3)내의 Cu, Cu화합물, Si등은 BCl3+Cl2와의 반응성이 낮기 때문에 식각되지 않고 금속의 입계(Grain boundary)에 그대로 남아 있게 된다(제1도 (b)의 3A참조).Subsequently, as shown in FIG. 1 (b), the Al-Si-Cu alloy film 3 was subjected to pressure using a BCl 3 + Cl 2 based gas using the photoresist pattern and the upper barrier metal layer 4 as masks; Several to several hundred mTorr, RF power; It is etched by RIE under the condition of 30% to 90% of the maximum power (Fig. 2 stage B). At this time, Cu, Cu compound, Si, etc. in the Al-Si-Cu alloy film 3 is not etched and remains at the grain boundary of the metal because it is low in reactivity with BCl 3 + Cl 2 (FIG. 1). See 3A in (b)).

다음에 제1도 (c)에 도시된 바와 같이 상기 Al합금막을 BCl3+Cl2계 가스를 이용한 RIE에 의해 과도식각(제2도 C단계)하여 완전히 제거함으로써 금속배선을 형성한 다음, 하부 장벽금속층(2)을 F계 가스를 이용하여 수~수백mTorr의 압력범위내에서 RIE에 의해 식각해낸다(제2도 D단계). 이때, 상기 금속입계에 남아 있는 Cu, Cu화합물, Si등이 마스크로 작용하여 하부 장벽금속층(2)이 환전히 제거되지 않고 잔유물(6)로서 Cu, Cu화합물, Si등과 함께 남아 있게 된다.Next, as shown in FIG. 1 (c), the Al alloy film is excessively etched by RIE using a BCl 3 + Cl 2 -based gas (step 2 in FIG. C) to completely remove the metal wiring, and then The barrier metal layer 2 is etched by RIE within a pressure range of several to several hundred mTorr using F-based gas (step D in FIG. 2). At this time, Cu, Cu compound, Si, etc. remaining in the metal grain boundary act as a mask so that the lower barrier metal layer 2 is not removed, but remains together with Cu, Cu compound, Si, etc. as the residue 6.

이와 같이 Cu, Cu화합물, Si 및 장벽금속층 잔유물이 남아 있게 됨으로써 금속배선의 단락을 유발시키게 되며, 이에 따라 수율감소 및 소자의 신회성저하등의 문제가 발생하게 된다.As such, the Cu, Cu compound, Si, and the residue of the barrier metal layer remain, causing short circuits of the metal wiring, thereby causing problems such as reduced yield and deterioration of the device.

본 발명은 이와 같은 문제를 해결하기 위한 것으로, Al합금막 식각시 원치 않는 잔유물을 완전히 제거해낼 수 있는 식각방법을 제공하는데 그 목적이 있다.The present invention has been made to solve such a problem, and an object thereof is to provide an etching method capable of completely removing unwanted residues during Al alloy film etching.

상기 목적을 달성하기 위한 본 발명의 금속막 식각방법은 건식식각방법을 이용하여 알루미늄합금막을 식각하는 방법에 있어서 BCL3+Cl2가스를 이용한 건식식각하는 제1식각단계와 As 또는 As + XeF2가스를 이용한 스퍼터링에 의해 식각하는 제2식각단계를 병행하여 상기 알루미늄합금막을 식각하는 것을 특징으로 한다.Metal film etching method of the present invention for achieving the above object in the method of etching the aluminum alloy film using a dry etching method of the first etching step using dry etching with BCL 3 + Cl 2 gas and As or As + XeF 2 The aluminum alloy film is etched by performing a second etching step of etching by sputtering using gas.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

본 발명에 의한 반도체장치의 금속배선 형성방법을 공정순서에 따른 단면구조를 나타낸 제3도 및 식각공정의 흐름도를 도시한 제4도를 참조하여 설명하면 다음과 같다.A method of forming a metal wiring in a semiconductor device according to the present invention will be described with reference to FIG. 3 showing a cross-sectional structure according to the process sequence and FIG. 4 showing a flowchart of an etching process.

먼저, 제3도 (a)에 도시된 바와 같이 기판(도시하지 않음)상에 형성된 하지층(1)(산화막과 같은 절연이거나 다층배선구조의 상부배선층을 형성할 경우에는 BPSG와 같은 평탄화층일 수 있다)상에 하부 장벽금속층(Barrier metal)(2)을 형성하고, 이 위에 금속배선 형성용 도전층으로서, Al-Si-Cu합금막(3)을 증착한 후, 그 상부에 상부 장벽금속층(4)을 형성하고, 이 위에 감광막(5)을 도포한 다음, 상기 감광막을 선택적으로 노광 및 현상하여 형성하고자 하는 금속배선패턴에 따라 소정의 감광막패턴을 형성한다. 이어서 상기 감광막패턴을 마스크로 하여 상부 장벽금속층(4)을 F계(Fluorine base) 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 RIE에 의해 시간 또는 종점검출(End point detetion)방법으로 식각한다(제4도 A'단계).First, as shown in FIG. 3A, a base layer 1 (not shown) formed on a substrate (not shown) may be a planarization layer such as BPSG when forming an insulating layer such as an oxide film or an upper wiring layer of a multilayer wiring structure. A lower barrier metal layer 2 is formed thereon, and an Al—Si—Cu alloy film 3 is deposited thereon as a conductive layer for forming metal wiring thereon, and then the upper barrier metal layer 3 is formed thereon. 4), the photoresist film 5 is applied thereon, and then the photoresist film is selectively exposed and developed to form a predetermined photoresist pattern according to the metal wiring pattern to be formed. Subsequently, the upper barrier metal layer 4 was pressed using F-based (Fluorine base) gas using the photoresist pattern as a mask; Several to several hundred mTorr, RF power; Etch by time or end point detetion method by RIE under conditions of 30% ~ 90% of maximum power (Fig. 4A step).

이어서 제3도 (b)에 도시된 바와 같이 상기 감광막패턴 및 상부 장벽금속층(4)을 마스크로 하여 Al-Si-Cu합금막(3)을 BCl3+Cl2계 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 RIE에 의해 약 30초간 식각(제4도 B'단계)하여 일정두께만큼 제거해낸다. 이때, Al-Si-Cu합금막(3)내의 Cu, Cu화합물, Si등은 BCl3+Cl2와의 반응성이 낮기 때문에 식각되지 않고 금속의 입계(Grain boundary)에 그대로 남아 있게 된다(제3도 (b)의 3A참조).Subsequently, as shown in FIG. 3 (b), the Al-Si-Cu alloy film 3 was subjected to pressure using a BCl 3 + Cl 2 based gas using the photoresist pattern and the upper barrier metal layer 4 as masks; Several to several hundred mTorr, RF power; It is etched by RIE for about 30 seconds under the condition of 30% to 90% of the maximum power (step B 'in FIG. 4) and removed to a certain thickness. At this time, Cu, Cu compound, Si, etc. in the Al-Si-Cu alloy film 3 is not etched because it is low in reactivity with BCl 3 + Cl 2 and remains at the grain boundary of the metal (FIG. 3). See 3A in (b)).

다음에 제3도 (c)에 도시된 바와 같이 상기 금속입계에 남아 있는 Cu, Cu화합물, Si등(3A)을 As 또는 As + XeF2가스를 이용한 스퍼터링에 의해 1초~수분간, 예컨대 약 10초간 식각하여 제거해낸다(제4도 C'단계). 이때, 상기 스퍼터링의 식각조건은 상기 Al-Si-Cu합금막의 식각조건과 동일한 조건으로 한다.Next, as shown in FIG. 3 (c), Cu, Cu compound, Si, etc. (3A) remaining in the metal grain boundary are sputtered with As or As + XeF 2 gas for 1 second to several minutes, for example, about Etch for 10 seconds to remove (Step C '). At this time, the etching conditions of the sputtering are the same as the etching conditions of the Al-Si-Cu alloy film.

이어서 남아 있는 상기 Al-Si-Cu합금막(3)을 BCl3+Cl2계 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 RIE에 의해 약 30초간 식각(제4도 D'단계)한다. 이때도 역시 Al-Si-Cu합금막내의 Cu, Cu화합물, Si등이 BCl3+Cl2와 반응하지 않고 금속의 입계에 남아 있게 되는데, 이와 같이 금속입계에 남아 있는 Cu, Cu화합물, Si등을 다시 As 또는 As + XeF2가스를 이용한 스퍼터링에 의해 1초~수분간, 예컨대 약 10초간 식각하여 제거해낸다(제4도 E'단계). 이때, 상기 스퍼터링의 식각조건은 상기 Al-Si-Cu합금막의 식각조건과 동일한 조건으로 한다.Then, the remaining Al-Si-Cu alloy film 3 was pressurized using BCl 3 + Cl 2 -based gas; Several to several hundred mTorr, RF power; It is etched by RIE for about 30 seconds under the condition of 30% to 90% of the maximum power (Fig. 4 D'step). At this time, Cu, Cu compound, Si, etc. in the Al-Si-Cu alloy film remain at the grain boundary of the metal without reacting with BCl 3 + Cl 2. Thus, Cu, Cu compound, Si, etc. remaining at the metal grain boundary Is removed again by etching for 1 second to several minutes, for example, about 10 seconds by sputtering using As or As + XeF 2 gas (step E '). At this time, the etching conditions of the sputtering are the same as the etching conditions of the Al-Si-Cu alloy film.

이어서 상기 Al-Si-Cu합금막을 BCl3+Cl2계 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 RIE에 의해 약 20초간 과도식각함으로써 (제4도 F'단계) 제3도 (d)와 같이 Al-Si-Cu합금막(3)을 형성한다.Subsequently, the Al-Si-Cu alloy film was pressured using BCl 3 + Cl 2 -based gas; Several to several hundred mTorr, RF power; The Al-Si-Cu alloy film 3 is formed as shown in FIG. 3 (d) by over-etching for about 20 seconds by RIE under the conditions of 30% to 90% of the maximum power.

이어서 상기 하부 장벽금속층(2)을 F계 가스를 이용하여 수~수백mTorr의 압력범위내에서 RIE에 의해 식각하면(제4도 G'단계) 원치않는 잔유물등을 남기는 일없이 원하는 금속배선을 얻을 수 있게 된다.Subsequently, the lower barrier metal layer 2 is etched by RIE using a F-based gas within a pressure range of several hundreds to several hundred mTorr (step 4'G ') to obtain a desired metal wiring without leaving unwanted residues. It becomes possible.

본 발명은 상기한 RIE방법 외에도 RF바이어스를 인가하는 ECR, MERIE등을 이용한 식각시에도 적용가능하다.The present invention can be applied to an etching process using ECR, MERIE, etc. to apply an RF bias in addition to the above RIE method.

이상 상술한 바와 같이 본 발명에 의하면, Al-Si-Cu합금막의 식각시 입계에 남아 마스크 역할을 하는 Cu, Cu화합물, Si등 및 장벽금속층의 잔유물을 완전히 제거할 수 있으므로 금속배선의 단락을 방지할 수 있고 이에 따라 수율향상 및 소자의 신뢰성 향상을 도모할 수 있다.As described above, according to the present invention, it is possible to completely remove the residues of the Cu, Cu compound, Si, and the barrier metal layer which remain at the grain boundary during etching of the Al-Si-Cu alloy film and act as a mask, thereby preventing short circuit of the metal wiring. As a result, the yield can be improved and the reliability of the device can be improved.

Claims (7)

건식식각방법을 이용하여 알루미늄합금막을 식각하는 방법에 있어서,BCl3+Cl2가스를 이용한 건식식각하는 제1식각단계와 As 또는 As + XeF2가스를 이용한 스퍼터링에 의해 식각하는 제2식각단계를 병행하여 상기 알루미늄합금막을 식각하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.In the method of etching the aluminum alloy film using a dry etching method, the first etching step of dry etching using BCl 3 + Cl 2 gas and the second etching step of etching by sputtering using As or As + XeF 2 gas The aluminum alloy film etching method of manufacturing a semiconductor device, characterized in that for etching the aluminum alloy film in parallel. 제1항에 있어서, 상기 제1식각단계는 BCl3+Cl2계 가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 행하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The method of claim 1, wherein the first etching step comprises: pressure using BCl 3 + Cl 2 -based gas; Several to several hundred mTorr, RF power; An aluminum alloy film etching method in the manufacture of a semiconductor device, characterized in that the conditions are performed at 30% to 90% of the maximum power. 제1항에 있어서, 상기 제1식각단계는 As 또는 As + XeF2가스를 이용하여 압력 ; 수~수백mTorr, RF파워 ; 최대파워의 30%~90%의 조건으로 행하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The method of claim 1, wherein the first etching step is performed by using As or As + XeF 2 gas; Several to several hundred mTorr, RF power; An aluminum alloy film etching method in the manufacture of a semiconductor device, characterized in that the conditions are performed at 30% to 90% of the maximum power. 제1항에 있어서, 상기 알루미늄합금막은 Al-Si-Cu합금막임을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The aluminum alloy film etching method of claim 1, wherein the aluminum alloy film is an Al—Si—Cu alloy film. 제1항에 있어서, 상기 제1식각단계 및 제2식각단계는 RIE 또는 ECR 또는 MERIE의 식각장비를 이용하여 행하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The aluminum alloy film etching method of claim 1, wherein the first etching step and the second etching step are performed using etching equipment of RIE, ECR, or MERIE. 제1항에 있어서, 상기 제1식각단계를 진행한후 제2식각단계를 진행하는 공정을 적어도 2회 실시하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The aluminum alloy film etching method of claim 1, wherein the second etching step is performed at least twice after the first etching step. 제1항에 있어서, 상기 제2식각단계를 1초~수분간 실시하는 것을 특징으로 하는 반도체장치 제조시의 알루미늄합금막 식각방법.The aluminum alloy film etching method of claim 1, wherein the second etching step is performed for 1 second to several minutes.
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Publication number Priority date Publication date Assignee Title
KR100604798B1 (en) * 1999-12-30 2006-07-26 삼성전자주식회사 Method of etching thin layer preventing surface roughness

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604798B1 (en) * 1999-12-30 2006-07-26 삼성전자주식회사 Method of etching thin layer preventing surface roughness

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