KR100221585B1 - Forming method for via hole of semiconductor device - Google Patents
Forming method for via hole of semiconductor device Download PDFInfo
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- KR100221585B1 KR100221585B1 KR1019960024952A KR19960024952A KR100221585B1 KR 100221585 B1 KR100221585 B1 KR 100221585B1 KR 1019960024952 A KR1019960024952 A KR 1019960024952A KR 19960024952 A KR19960024952 A KR 19960024952A KR 100221585 B1 KR100221585 B1 KR 100221585B1
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- Prior art keywords
- via hole
- forming
- interlayer insulating
- gas
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 26
- 229920000642 polymer Polymers 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 비아홀 형성방법을 제공하는 것으로, 비아홀 형성시 두꺼운 폴리머를 생성하도록 하는 메인 식각단계와, 폴리머를 제거하면서 티타늄 나이트라이드의 식각비를 높여 금속성 풋을 제거하도록 한 오버 식각단계로 나누어서 실시하여 비아홀의 측벽에 발생되는 풋 현상을 제거하므로써 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method of forming a via hole in a semiconductor device, including a main etching step of forming a thick polymer when forming a via hole, and an over etching step of removing a polymer foot and removing a metallic foot by increasing an etching ratio of titanium nitride. It is possible to improve the yield of the device by eliminating the foot phenomenon generated on the sidewall of the via hole by dividing.
Description
제1a 및 1b 도는 종래 반도체 소자의 비아홀을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of devices for describing via holes in a conventional semiconductor device.
제2a 내지 2c도는 본 발명에 따른 반도체 소자의 비아홀 형성 방법을 설명하기 위한 소자의 단면도.2A through 2C are cross-sectional views of a device for explaining a method of forming a via hole in a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호설명* Explanation of symbols on the main parts of the drawings
1 및 11 : 실리콘 기판 2 및 12 : 알루미늄 패턴1 and 11: silicon substrate 2 and 12: aluminum pattern
3 및 13 : 티타늄 나이트라이드층 4 및 14 : 제1층간 절연막3 and 13: titanium nitride layer 4 and 14: first interlayer insulating film
5 및 15 : SOG막 6 및 16 : 제2층간 절연막5 and 15: SOG film 6 and 16: Second interlayer insulating film
7a, 7b 및 17 : 폴리머 8 및 18 : 감광막 패턴7a, 7b and 17: polymer 8 and 18: photoresist pattern
10 및 20 : 비아홀 A : 보잉현상10 and 20: Via Hole A: Boeing phenomenon
본 발명은 반도체 소자의 비아홀 형성방법에 관한 것으로 특히, 다층 금속배선간 접속을 위한 비아홀 형성시 발생되는 SOG막의 보잉(Bowing)현상 또는 폴리머로 인한 풋(Foot)을 방지할 수 있는 반도체 소자의 비아홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a via hole of a semiconductor device. In particular, a via hole of a semiconductor device capable of preventing a bowing phenomenon or a foot caused by a polymer of SOG film generated when a via hole is formed for connection between multilayer metal interconnections. It relates to a forming method.
일반적으로 반도체 소자가 고집적화 됨에 따라 금속 배선은 다층구조로 이루어지고 있으며, 콘택홀 또는 선폭이 0.35㎛ 이하로 감소되고 있다. 기존의 장비로는 이러한 콘택홀 또는 선폭의 구현이 어렵기 때문에 새로운 장비가 개발되고 있으며 대표적으로 HDP(High Density Plasma)식각기가 있다. 그러나 이러한 장비는 기존의 장비에 비해서 1000배 이상의 플라즈마를 사용하는 관계로 다른막에 비해서 부드러운 SOG막에 심각한 보잉현상을 초래하게 된다. 즉, 제1a도에 도시한 바와 같이 알루니늄 패턴(2)이 형성된 실리콘기판(1)상에 티타늄 나이트라이드층(3), 제1층간 절연막(4), SOG막(5) 및 제2층간 절연막(6)을 순차적으로 형성하고, 제2층간 절연막 (6)상에 감광막 패턴(8)을 형성한 후 알루미늄 패턴(2)이 노출되도록 얇은 폴리머(7A)가 생성되는 비아홀(10)을 형성할 때 노출되는 SOG막(5)은 보잉현상(A)이 발생된다. 따라서 이러한 현상을 방지하기 위하여 비아홀(10) 형성시 C2F6및 CHF3의 혼합가스를 이용하여 생성된 폴리머가 비아홀(10)측벽에 두껍게 달라붙게하여 SOG막(5)의 보잉현상(A)을 방지하였다. 즉, 제1b도에 도시한 바와 같이 알루미늄 패턴(2)이 형성된 실리콘기판(1)상에 티타늄 나이트라이드층(3), 제1층간 절연막(4), SOG막(5) 및 제2층간 절연막(6)을 순차적으로 형성하고, 제2층간 절연막(6)상에 감광막 패턴(8)을 형성한 후 알루미늄 패턴(2)이 노출되도록 두꺼운 폴리머(7B)가 생성되는 비아홀(10)을 형성할 때 이 비아홀(10)의 측벽에는 폴리머(7B)가 두껍게 형성되어 SOG막(5)의 보잉현상(A)은 억제할 수 있으나 두꺼운 폴리머(7B)가 완전히 제거되지 않은 상태에서 알루미늄 패턴(2)이 식각되기 때문에 이로인하여 발생되는 풋 현상은 CD편차를 유발함은 물론 금속층간의 접촉을 불량하게 하므로써 소자의 특성을 저하시키게 된다.In general, as semiconductor devices are highly integrated, metal wirings have a multilayer structure, and contact holes or line widths are reduced to 0.35 μm or less. Existing equipment is difficult to implement such a contact hole or line width, new equipment is being developed, and the representative HDP (High Density Plasma) etcher. However, this equipment uses more than 1000 times more plasma than the existing equipment, which causes serious boeing on a soft SOG film compared to other films. That is, as shown in FIG. 1A, the titanium nitride layer 3, the first interlayer insulating film 4, the SOG film 5, and the second film are formed on the silicon substrate 1 on which the aluminum pattern 2 is formed. After the interlayer insulating film 6 is formed sequentially, the photoresist pattern 8 is formed on the second interlayer insulating film 6, and the via hole 10 in which the thin polymer 7A is formed to expose the aluminum pattern 2 is formed. The SOG film 5 exposed when formed generates a bowing phenomenon (A). Therefore, in order to prevent such a phenomenon, when the via hole 10 is formed, the polymer generated using the mixed gas of C 2 F 6 and CHF 3 adheres thickly to the side wall of the via hole 10 so that the SOG film 5 is boeing phenomenon (A). ). That is, as shown in FIG. 1B, the titanium nitride layer 3, the first interlayer insulating film 4, the SOG film 5, and the second interlayer insulating film are formed on the silicon substrate 1 on which the aluminum pattern 2 is formed. (6) are sequentially formed, and after the photoresist pattern 8 is formed on the second interlayer insulating film 6, a via hole 10 in which a thick polymer 7B is formed to expose the aluminum pattern 2 is formed. At this time, a thick polymer 7B is formed on the sidewall of the via hole 10 so that the bowing phenomenon A of the SOG film 5 can be suppressed, but the aluminum pattern 2 is not completely removed. Because of this etching, the foot phenomenon caused by this causes not only CD deviation but also poor contact between metal layers, thereby degrading device characteristics.
따라서 본 발명은 비아홀 형성시 두꺼운 폴리머를 생성하도록 하는 메인 식각단계와, 폴리머를 제거하면서 티타늄 나이트라이드의 식각비를 높여 금속성 풋을 제거하도록 한 오버 식각단계로 나누어 실시하므로써 상기와 같은 문제점을 해소할 수 있는 반도체 소자의 비아홀 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention solves the above problems by dividing the main etching step to form a thick polymer when the via hole is formed, and the over etching step to remove the metallic foot by increasing the etching ratio of titanium nitride while removing the polymer. It is an object of the present invention to provide a method for forming a via hole of a semiconductor device.
상기한 목적을 달성하기 위한 본 발명의 비아홀 형성방법은 알루미늄 패턴이 형성된 실리콘기판상에 티타늄 나이트라이드층, 제1층간 절연막, SOG막 및 제2층간 절연막을 순차적으로 형성한 후 제2층간 절연막상에 감광막 패턴을 형성하는 단계와, 상기 단계로부터 티타늄 나이트라이드층이 노출되도록 메인식각 공정을 실시하여 두꺼운 폴리머를 갖는 비아홀을 형성하는 단계와, 상기 단계로부터 알루미늄 패턴이 노출되도록 오버식각 공정을 실시하여 완전한 비아홀을 형성하는 단계로 이루어지는 것을 특징으로 한다.In the method of forming a via hole of the present invention for achieving the above object, a titanium nitride layer, a first interlayer insulating film, an SOG film, and a second interlayer insulating film are sequentially formed on a silicon substrate on which an aluminum pattern is formed. Forming a photoresist pattern on the substrate, performing a main etching process to expose the titanium nitride layer from the step, forming a via hole having a thick polymer, and performing an overetching process to expose the aluminum pattern from the step And forming a complete via hole.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a 내지 2c 도는 본 발명에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 소자의 단면도로서, 제2a도는 알루미늄 패턴(12)이 형성된 실리콘 기판(11)상에 티타늄 나이트라이드층(13), 제1층간 절연막(14), SOG막(15)및 제2층간 절연막(16)을 순차적으로 형성한 후 제2층간 절연막(16)상에 감광막 패턴(18)을 형성한 상태를 도시한다.2A through 2C are cross-sectional views illustrating a method of forming a via hole of a semiconductor device according to the present invention, and FIG. 2A illustrates a titanium nitride layer 13 and a second layer on a silicon substrate 11 on which an aluminum pattern 12 is formed. The state where the photosensitive film pattern 18 was formed on the 2nd interlayer insulation film 16 after forming the 1st interlayer insulation film 14, the SOG film 15, and the 2nd interlayer insulation film 16 sequentially is shown.
제2b도는 티타늄 나이트라이드층(13)이 노출되도록 메인식각 공정을 실시하여 두꺼운 폴리머(17)를 갖는 비아홀(20)을 형성한 상태를 도시한다. 메인식각 공정은 2500 내지 3100W의 소스전력, 500 내지 900W의 바이어스 전력, 5 내지 15mTorr의 압력조건에서 10 내지 50sccm의 C2F6, 20 내지 60sccm의 CHF3및 80 내지 160sccm의 아르곤(Ar)가스를 공급하므로써 진행된다. 이러한 조건에서의 메인식각 공정시 티타늄 나이트라이드층(13)의 식각 선택비가 낮아진 상태에서 제2층간 절연막(16), SOG막(15) 및 제1층간 절연막이 순차적으로 식각되어 진다. 이때 비아홀(20)의 측벽에는 두꺼운 폴리머(17)가 형성된다.FIG. 2B illustrates a state in which the via hole 20 having a thick polymer 17 is formed by performing a main etching process to expose the titanium nitride layer 13. The main etching process includes source power of 2500 to 3100W, bias power of 500 to 900W, C 2 F 6 of 10 to 50 sccm, CHF 3 of 20 to 60 sccm and argon (Ar) gas of 80 to 160 sccm under pressure conditions of 5 to 15 mTorr. Proceed by supplying In the main etching process under such a condition, the second interlayer insulating layer 16, the SOG film 15, and the first interlayer insulating layer are sequentially etched while the etching selectivity of the titanium nitride layer 13 is lowered. In this case, a thick polymer 17 is formed on the sidewall of the via hole 20.
제2c도는 알루미늄 패턴(12)이 노출되도록 오버식각 공정을 실시하여 완전한 비아홀(20)을 형성한 상태를 도시한다. 오버식각 공정은 2500 내지 3100W의 소스전력, 500 내지 900W의 바이어스 전력, 5 내지 15mTorr의 압력조건에서 10 내지 50sccm의 C2F6및 50 내지 150sccm의 산소(O2)가스를 공급하므로써 진행한다. 이러한 조건에서의 오버식각 공정시 티타늄 나이트라이드층(13)의 식각 선택비가 높아진 상태에서 폴리머(17)가 제거되면서 티타늄 나이트라이드층(13)이 식각되어진다. 오버식각 공정은 C2F6및 산소 (O2)가스에 CHF3가스를 추가하여 사용하여도 좋다.FIG. 2C illustrates a state in which a complete via hole 20 is formed by performing an overetch process to expose the aluminum pattern 12. The overetch process is performed by supplying 10 to 50 sccm of C 2 F 6 and 50 to 150 sccm of oxygen (O 2 ) gas under a source power of 2500 to 3100 W, a bias power of 500 to 900 W, and a pressure of 5 to 15 mTorr. During the over-etching process under such conditions, the titanium nitride layer 13 is etched while the polymer 17 is removed while the etching selectivity of the titanium nitride layer 13 is increased. The over-etching process may be used by adding CHF 3 gas to C 2 F 6 and oxygen (O 2 ) gas.
상술한 바와 같이 본 발명에 의하면 비아홀 형성시 두꺼운 폴리머를 생성하도록 하는 메인 식각단계와, 폴리머를 제거하면서 티타늄 나이트라이드의 식각비를 높여 금속성 풋을 제거하도록 한 오버 식각단계로 나누어서 실시하여 비아홀의 측벽에 발생되는 풋 현상을 제거하므로써 소자의 수율을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the sidewall of the via hole is divided into a main etching step of forming a thick polymer when the via hole is formed, and an over etching step of removing the polymer and removing the metallic foot by increasing the etching rate of titanium nitride. It is an excellent effect to improve the yield of the device by eliminating the foot phenomenon occurs in the.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019960024952A KR100221585B1 (en) | 1996-06-28 | 1996-06-28 | Forming method for via hole of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960024952A KR100221585B1 (en) | 1996-06-28 | 1996-06-28 | Forming method for via hole of semiconductor device |
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| KR980005574A KR980005574A (en) | 1998-03-30 |
| KR100221585B1 true KR100221585B1 (en) | 1999-09-15 |
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| Country | Link |
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| KR (1) | KR100221585B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744243B1 (en) | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for fabricating a metal line in a semiconductor |
-
1996
- 1996-06-28 KR KR1019960024952A patent/KR100221585B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744243B1 (en) | 2005-12-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for fabricating a metal line in a semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980005574A (en) | 1998-03-30 |
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