JPH0817924A - Multilayered wiring forming method and multilayered wiring structure - Google Patents

Abstract

PURPOSE:To provide a multilayered wiring forming method and its structure wherein misalignment margin at the time of forming a connection hole is introduced, without forming an overlapping part in a lower layer wiring, in the interlayer connection of a multilayered wiring. CONSTITUTION:After a first pattern is formed by etching a part of the thickness direction of a lower layer wiring 3, a sublimation side wall 9 composed of sulfur based material is formed on the side surfaces of a mask 8 and the first pattern, and a second pattern is formed by etching the residual part in the thickness direction of the lower wiring. A terrace part 3T of the second pattern is turned into the misalignment margin at the time of forming a connection hole. When the connection hole is misaligned, the terrace part 3T acts as an etching stopper, and an insulating layer 2 is not damaged. Since the width of the terrace part 3T is determined by self-alignment, the process is stable, and wiring density is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring forming method and a multilayer wiring structure used for a semiconductor device or the like, and more particularly to a multilayer wiring forming method for forming a connection hole portion of a lower layer wiring of a multilayer wiring without overlapping. The present invention relates to a multilayer wiring structure.

[0002]

2. Description of the Related Art With the increasing integration of semiconductor devices such as LSIs, the importance of the multi-layer wiring process is increasing.
One of the key points in improving the integration of semiconductor devices is narrowing the wirings that occupy a large area on the semiconductor chip and the pitches between the wirings. Therefore, the design rules are also reduced from sub-half micron to quarter micron level. It is becoming popular.

In a multi-layer wiring process in which a contact hole is formed in an interlayer insulating film on a lower wiring of such a fine width and a contact plug is formed therefor to make an interlayer connection with an upper wiring, mask misalignment during lithography is caused. In order to secure a margin to be compensated, it is usual to provide an overlap portion. This will be described with reference to FIGS.

FIG. 3A is a schematic sectional view showing an overlapping portion of a multi-layer wiring. A lower layer wiring 3 is formed on the insulating layer 2 on the semiconductor substrate 1, and a connection hole 6 facing the lower layer wiring 3 is opened in the upper interlayer insulating film 5. In the lower layer wiring 3 of the opening of the connection hole 6, an overlap portion 4 in which the width of the lower layer wiring 3 is widened is formed in advance. FIG. 3B is also a schematic plan view showing an overlapping portion of the multilayer wiring, showing a plurality of adjacent lower layer wirings 3. In pattern exposure of the resist layer for forming the connection hole 6, alignment is performed by an alignment mark (not shown) on the semiconductor chip.
In consideration of this misalignment, the overlap part 4 is shown in FIG.
As shown in (b), it is formed to be wider than the lower layer wiring 3. Thereby, even if the mask for opening the contact hole is displaced from the lower layer wiring 3, it is possible to avoid the disadvantage that the insulating layer 2 is dug by etching when the contact hole 6 is opened and the ohmic contact becomes unstable.

However, between the spaces between the lower layer wirings 3
Distance D₁Is a certain limit as long as the overlap section 4 exists.
It is impossible to narrow down below. That is, over
Space interval D for lap₂Resolution limit during lithography
Even if it is set to the threshold, D ₁Is D₂Overlap section
Overhang width D₃Because the interval is twice the
It This relationship is D₁= D₂+ 2D₃It is represented by sand
That is, the space between the lower layer wirings 3 other than the overlap section 4
Interval D₂Is a useless 2D in the wiring layout₃caused by
Area is included, which hinders high integration of semiconductor devices.
It was.

[0006]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to form a base layer without forming an overlapping portion in a lower layer wiring of a connection hole opening and even when a mask misalignment for forming a connection hole occurs. It is an object of the present invention to provide a method for forming a multi-layer wiring and a multi-layer wiring structure without damaging an insulating layer.

Another object of the present invention is to narrow the space between the lower layer wirings without forming an overlapping portion in the lower layer wirings of the connection hole openings, thereby improving the integration degree of the semiconductor device. A method for forming a multi-layer wiring and a multi-layer wiring structure. Other problems of the present invention will be made clear by the description of the present specification and the accompanying drawings.

[0008]

The method for forming a multi-layered wiring according to the present invention was devised to solve the above-mentioned problems. That is, it is a method for forming a multi-layer wiring, which comprises a step of opening a connection hole facing the lower layer wiring in an interlayer insulating film on the lower layer wiring, wherein the lower layer wiring forming step uses the mask layer as a mask to reduce the thickness of the lower wiring layer. Patterning a portion in the vertical direction to form a first pattern, forming a sublimable side wall on the side surface of the mask layer and the first pattern, and using the mask layer and the sublimable side wall as a new mask, the lower layer wiring It is characterized by including the step of patterning the remaining portion in the thickness direction of the layer to form a second pattern.

The sublimable side wall is formed of an S (sulfur) layer or a (SN) _n (polythiazyl) layer. Among these, the sulfur layer is formed from the gas phase by using a gas that can generate free sulfur in plasma under discharge dissociation conditions.
The polythiazyl layer is also formed from the gas phase by using a gas that can generate free sulfur in plasma under discharge dissociation conditions and an N-based gas.

Gases capable of producing free sulfur in plasma under discharge dissociation conditions include S ₂ F ₂ , SF ₂ , SF
₄ , S ₂ F ₁₀ , S ₂ Cl ₂ , S ₃ Cl ₂ , SCl ₂ , S
Either a halogenated sulfur-based gas such as ₂ Br ₂ , S ₃ Br ₂ , or SBr ₂ and H ₂ S gas are used. SF _{6, which} is a common halogenated sulfur gas, is excluded from the present invention because it does not produce free sulfur in the plasma under discharge dissociation conditions.

The N-based gas includes N ₂ , NF ₃ , and N.
Either ₂ F ₄ or N ₂ H ₄ is used. Of the N-based gases, NH ₃ does not form polythiazyl, but rather forms sublimable (NH ₄ ) ₂ S (ammonium sulfide) and is therefore excluded from the present invention.

On the other hand, the multilayer wiring structure of the present invention is also devised to solve the above-mentioned problems. That is, in a multilayer wiring structure having a connection hole facing the lower layer wiring in an interlayer insulating film on the lower layer wiring, the lower layer wiring is in contact with a narrow first pattern and a lower portion of the first pattern, In addition, the second pattern having a width wider than the first pattern width forms a cross section perpendicular to the longitudinal direction of the wiring in a convex shape.

The first pattern includes an Al-based metal layer, and the second pattern includes a refractory metal layer such as W. Further, the first pattern width is preferably 0.5 μm or less from the viewpoint of use in a highly integrated semiconductor device.

[0014]

The point of the present invention resides in the structure of the lower layer wiring which does not require the overlapping portion and the forming process thereof. That is, a margin is introduced by previously adding an overlapping portion to the lower layer wiring patterning mask so that the above-mentioned inconvenience does not occur even when the mask misalignment occurs at the time of exposure when forming the mask for opening the contact hole. That is, the lower layer wiring forming process and the structure thereof do not depend on the conventional mask shape.

According to the method of forming a multilayer wiring of the present invention, the lower wiring layer is patterned halfway using a mask having a fine space interval to form a first pattern, and then the mask and the side surface of the first pattern are formed. A sublimable side wall is formed to expand the apparent mask width, and the lower wiring layer is further patterned by using the mask having the side wall as a new mask to form a second pattern to complete the lower wiring pattern. According to this two-step patterning method, the terrace portion by the second pattern that fills the lower portion of the lower layer wiring is formed over the entire length of the lower layer wiring, and when the above-described mask misalignment occurs, the misalignment occurs. It acts as a margin. This relationship will be described with reference to FIGS. 2A and 2B which are schematic cross-sectional views showing the principle of the present invention.

FIG. 2A shows a cross-sectional shape of the lower layer wiring 3 employed in the multilayer wiring structure of the present invention, showing a cross section perpendicular to the longitudinal direction of the wiring. As is clear from the figure, the lower layer wiring 3 is formed in a convex shape by the upper first pattern 3A and the lower first pattern 3B, and the second pattern 3B is formed from the first pattern 3A. A terrace portion 3T that overhangs is formed.

Next, the function of the terrace portion 3T will be described. FIG. 2B shows a state in which a plurality of lower layer wirings 3 according to the multilayer wiring structure of the present invention are formed in parallel with a certain space interval, and a plurality of connection holes (via holes) 6 facing the plurality of lower layer wirings are opened. Show. The connection hole 6 should originally be opened immediately above the first pattern 3A. However, in FIG. 2B, due to misalignment during exposure of the mask for forming the connection hole, the connection hole 6
Are partially displaced from the first pattern 3A and opened. In this case, if the pattern of the lower layer wiring 3 is simply rectangular, the underlying insulating layer 2 may be dug and damaged due to overetching when the connection hole 6 is opened. However, in the structure of the lower layer wiring 3 according to the multilayer wiring structure of the present invention, the terrace portion 3T protruding from the second pattern 3A serves as an etching stopper, and such a disadvantage can be avoided.

Further, the terrace portion 3T is formed by the sublimable side wall and its width is self-aligned. That is,
The space spacing between the second patterns 3B is also determined in a self-aligned manner. Therefore, even when the space intervals between the plurality of first patterns 3A are set to the resolution limit at the time of lithography or a value close to the resolution limit, the space intervals between the second patterns 3B are limited to the resolution limit. It is formed in a self-aligned pattern with a fine width exceeding .about. And contributes to high integration.

[0019] Normally, in the case of forming such side wall after forming the insulating film such as formed after SiO ₂ the first pattern 3A conformally, may remain formed by etching back is performed. However, when the second pattern 3B is etched by using the side wall thus formed as a mask as well, a mask for protecting the first pattern 3A needs to be newly formed, which complicates the process. As another method, after forming the first pattern 3A, if a carbon-based polymer is deposited on the side wall and is used as a mask layer, the process is simplified. However, in this case, the surplus carbon-based polymer adheres to the inner wall of the etching chamber and the like, which causes a new problem in cleaning the process such as deterioration of the particle level.

The present invention solves all of the above problems,
It is possible to achieve a clean process without reducing throughput. That is, the sulfur-based material layer can be deposited from the vapor phase on the substrate to be etched, the temperature of which is controlled below the sublimation point. This temperature is about 90 ° C or less for sulfur and about 150 ° C for polythiazyl.
It is the following. After the etching is finished, if the substrate to be etched is heated, these sulfur-based material layers are removed by sublimation and no contamination is left. The sublimation removal temperature is about 90 ° C. for the sulfur layer and over 150 ° C. for the polythiazyl layer.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings.

Example 1 This example is an example of using a sublimable side wall made of a sulfur layer when patterning a lower wiring layer including an Al-based metal layer formed on a refractory metal layer. Figure 1 (a)
This will be described with reference to (c). In the figure, the same components as those in FIGS. 2 and 3 are designated by the same reference numerals.

First, SiO _{2 is formed} on a semiconductor substrate 1 such as Si.
Insulating layer 2 made of, for example, is formed. The semiconductor substrate 1 may be a wiring layer made of polycrystalline silicon or Al-based metal.
Further, a connection hole (not shown) may be opened in the insulating layer 2. Next, Ti and TiON were added in this order to 30 nm and 7 respectively.
It is formed by sputtering to have a thickness of 0 nm to form an adhesion layer / barrier metal layer 31. Blanket CVD continuously
The refractory metal layer 32 made of W has a thickness of 200 nm, the Ti layer 33 formed by sputtering has a thickness of 50 nm, and Al-1% S
The Al-based metal layer 34 of i is 500 nm, and Ti
The antireflection layer 7 made of ON is formed to a thickness of 25 nm. Adhesion layer / barrier metal layer 31 to Al-based metal layer 34
The layers up to this point are the layers that form the lower layer wiring. Note that the thickness and layer configuration of each layer show typical examples, and the present invention is not limited to these. Next, using a chemically amplified resist and KrF excimer laser lithography, for example, 0.35 is obtained.
A plurality of masks 8 having a width of μm are formed. The space between the masks 8 is also 0.35 nm. Figure 1 formed so far
The sample shown in (a) is used as a substrate to be etched.

The substrate to be etched is etched by using an RF bias-applied helicon wave plasma etching device to etch the antireflection layer 7, the Al-based metal layer 34 and the Ti layer 33 under the following conditions as an example to form the first pattern 3A. Form. BCl ₃ 80 sccm Cl ₂ 120 sccm Gas pressure 0.13 Pa Helicon wave power source power 2500 W (13.56 MHz) RF bias power 100 W (2 MHz) Substrate temperature 0 ° C. Refractory metal layer in the etching process using Cl-based gas When 32 is exposed, etching stops and a first pattern is formed.

Next, the gas is switched in the same etching apparatus, and the sublimable side wall 9 made of a sulfur layer is formed under the following conditions. S ₂ F ₂ 40 sccm H ₂ 10 sccm Gas pressure 0.13 Pa Helicon wave power source power 2500 W (13.56 MHz) RF bias power 30 W (2 MHz) Substrate temperature 0 ° C. In this process, S generated by dissociation in plasma ^* (S radicals) become free sulfur and are deposited on the entire surface of the substrate to be etched, but since a weak RF bias is applied, the sublimable side wall 9 is formed only on the mask 8 and the first pattern side wall. . The thickness of the sublimable side wall 9 is 75 nm as an example.
Is. This state is shown in FIG. No RF bias need be applied, but in this case sulfur is conformally formed on the substrate to be etched. The addition of H ₂ gas has the effect of supplementing F ^* (F radicals) and promoting the deposition of sulfur, but it is not necessary to add it. Other H-based gas such as SiH ₄ may be used as the gas having the effect of supplementing the halogen radicals.

Subsequently, the refractory metal layer 3 is changed under the following conditions by switching the gas by the same etching apparatus.
2 and the adhesion layer / barrier metal layer 31 are etched, and the second
Pattern 3B is formed. S ₂ F ₂ 30 sccm Cl ₂ 20 sccm Gas pressure 0.13 Pa Helicon wave power source power 2500 W (13.56 MHz) RF bias power 100 W (2 MHz) Substrate temperature 0 ° C. In this etching process, the mask 8 and sublimable sidewalls are used. As a result of the etching progressing using 9 and 9 as an etching mask, a second pattern 3B wider than the first pattern is formed. After etching is completed, the substrate to be etched is about 9
When heated to 0 ° C. or higher, the sublimable side wall 9 is removed by sublimation.
The sublimable thin film 9 may be removed by oxidation at the same time when the mask 8 is ashed. This state is shown in FIG.
The terrace portion 3T is formed in the second pattern 3B in a self-aligned manner, and its width is about 75 nm which corresponds to the thickness of the sublimable side wall 9. The space between the adjacent second patterns is reduced to about 200 nm.

The mask 9 is ashed or wet stripped to complete the lower layer wiring 3 having a convex cross section. Hereinafter, the interlayer insulating film 5 is formed as shown in FIG.
A connection hole 6 facing the lower layer wiring 3 is opened, and an upper layer wiring or contact plug (not shown) is formed to complete a multilayer wiring structure. According to the present embodiment, by utilizing the sublimable side wall of sulfur, it is possible to realize a multilayer wiring structure having an alignment margin without an overlapping portion.

Example 2 This example is an example in which a sublimable side wall made of a polythiazyl layer was used when patterning a lower wiring layer including an Al-based metal layer formed on a refractory metal layer. The description will be made again with reference to FIGS. However, this embodiment is basically the same as the first embodiment except that the sulfur layer is changed to a polythiazyl layer as the sublimable side wall 9, and only this characteristic portion will be described.

After forming the first pattern 3A with the Cl-based gas, the gas is switched in the same helicon wave plasma etching apparatus, and the sublimable side wall 9 made of the polythiazyl layer is formed under the following conditions. S ₂ F ₂ 40 sccm N ₂ 10 sccm Gas pressure 0.13 Pa Helicon wave power source power 2500 W (13.56 MHz) RF bias power 30 W (2 MHz) Substrate temperature 0 ° C. In this step, S generated by dissociation in plasma ^* (S radical) reacts with N atom to first form thiazyl (S≡N). Since thiazyl has an unpaired electron in its molecule, it is easily polymerized to form (SN) ₂ . Further, this (SN) ₂ is repeatedly polymerized to become a polymer-like (SN) _n . Polythiazyl is a stable substance and does not decompose up to about 150 ° C. In this embodiment, since the substrate temperature is controlled to 0 ° C., polythiazyl can be deposited on the substrate to be etched. Further, by applying a weak RF bias, the sublimable side wall 9 is formed only on the mask 8 and the side wall of the first pattern 3A. The thickness of the sublimable side wall 9 is 75 as an example.
nm. This state is shown in FIG. An RF bias need not be applied, but in this case the polythiazyl layer is conformally formed on the substrate to be etched. In addition, as N-based gas other than N ₂ , NF ₃ , N ₂ F ₄
Alternatively, N ₂ H ₄ may be used.

The following steps are the same as those in the first embodiment, and the duplicate description will be omitted. The sublimable thin film made of polythiazil may also be removed by ashing. According to the present embodiment, by using the sublimable side wall made of polythiazyl having stronger ion irradiation resistance than the sulfur layer as an etching mask as a part of the mask, the controllability of the width of the terrace portion 321 of the second pattern is improved. Can be improved. As a result, it is possible to stably realize a multilayer wiring structure having an alignment margin without an overlapping portion.

Although the present invention has been described with reference to two embodiments, the present invention is not limited to these embodiments.

As the layer structure of the lower layer wiring, the structure in which the Al-based metal layer is laminated on the refractory metal layer is exemplified, but the polycide layer in which the refractory metal silicide layer is laminated on the polycrystalline silicon, or the polycrystalline It may be a single layer such as a silicon layer or an Al-based metal layer. The present invention provides an alignment margin in a self-aligning manner when a connection hole facing the lower layer wiring is formed in the interlayer insulating film on the lower layer wiring formed by these material layers and having a fine line width and space width. It is possible to introduce.

Although SiO ₂ is exemplified as the interlayer insulating film,
SiO ₂ containing impurities, that is, PSG, BSG, BP
It may be SG, AsSG, SiON, or Si ₃ N ₄ . SiOF and SiONF containing a halogen element such as F generally have a small relative dielectric constant, and are useful for reducing the capacitance between wirings and the signal transmission delay in the multilayer wiring structure in which the wiring interval is narrowed to the limit as in the present invention. is there. These F-containing interlayer insulating films can be formed by CVD or sputtering using an F-based gas such as C ₂ F ₆ or NF ₃ .

A helicon wave plasma etching apparatus was used as the etching apparatus, but a more general parallel plate type R
IE and ECR plasma etching equipment, and ICP
(Inductively Coupled Plas
ma) Etching device, TCP (Transform)
A r Coupled Plasma) etching device or the like may be used as appropriate. The substrate RF is applied to these etching devices.
Bias applying means and substrate stage temperature control means can be incorporated and used.

[0035]

As is apparent from the above description, according to the present invention, a mask misalignment occurs at the time of lithography for forming a contact hole without forming an overlap portion in a lower wiring of a contact hole opening. Even if it does, the base insulating layer is not damaged. For this reason, useless space can be eliminated from the design stage of the wiring layout, and the lower layer wiring group can be arranged with high density.

Even if the upper part of the lower layer wiring, that is, the space between the first patterns is designed to have a value close to or close to the resolution limit of lithography, the lower part of the lower layer wiring, that is, the second pattern interval is determined by self-alignment, so that it is high. In addition to contributing to integration, no accident such as short circuit between wirings will occur. Further, since the cross-sectional area is rather increased due to the convex-shaped wiring cross section, it is also useful for reducing the wiring resistance.

The sublimable side wall made of a sulfur-based material can be removed by heating the substrate after etching or by ashing without leaving substrate contamination. Similarly, the sulfur-based material attached to the inner wall of the etching chamber can be removed by heating. Therefore, a clean process without particle contamination is possible.

As a result of the above effects, it has become possible to provide a multi-layer wiring structure including a mask alignment countermeasure at the time of opening a contact hole and a method for forming the multilayer interconnection structure by self-alignment with high reliability. The multilayer wiring structure and the forming method according to the present invention are particularly applicable to 0.5 μ
The present invention is effective when used for a lower layer wiring of a semiconductor device having a fine wiring width of m or less, and the effect of the present invention is extremely large.

[Brief description of drawings]

FIG. 1 is a first embodiment to which a method for forming a multilayer wiring according to the present invention is applied.
3A and 3B are schematic cross-sectional views showing a dry-etching step of the lower wiring in FIGS. 2 and 3, where (a) shows a lower wiring layer and a mask having a laminated structure formed on a base insulating layer, and (b) shows a thickness direction of the lower wiring layer. A part of is patterned to form a first pattern, and further a sublimable side wall is formed,
(C) is a state in which the remaining portion of the lower wiring layer in the thickness direction is subsequently patterned to form a second pattern and the sublimable side wall is removed.

2A and 2B are schematic cross-sectional views showing the principle of the multilayer wiring structure of the present invention, in which FIG. 2A is a cross-sectional shape of a lower layer wiring, and FIG. 2B is a state in which a connection hole facing the lower layer wiring is opened.

3A and 3B are schematic diagrams showing an overlapping portion in a conventional multilayer wiring, FIG. 3A is a sectional view, and FIG. 3B is a plan view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating layer 3 Lower wiring 31 Adhesion layer and barrier metal layer 32 Refractory metal layer 33 Ti layer 34 Al metal layer 3A 1st pattern 3B 2nd pattern 3T Terrace part 4 Overlap part 5 Interlayer insulation film 6 Connection Hole 7 Antireflection Layer 8 Mask 9 Sublimable Sidewall

Claims (9)

[Claims] 1. A method for forming a multi-layered wiring, which comprises a step of opening a connection hole facing the lower layer wiring in an interlayer insulating film on the lower layer wiring, wherein the step of forming the lower layer wiring uses the mask layer as a mask. Patterning part of the wiring layer in the thickness direction to form a first pattern; forming sublimable sidewalls on the mask layer and the first pattern side surface; masking the mask layer and sublimable sidewall And a step of patterning the remaining portion of the lower wiring layer in the thickness direction to form a second pattern, as described above. 2. The method for forming a multilayer wiring according to claim 1, wherein the sublimable side wall is formed of any one of a sulfur layer and a polythiazyl layer. 3. The method for forming a multilayer wiring according to claim 2, wherein the sulfur layer is formed by using a gas that can generate free sulfur in plasma under discharge dissociation conditions. 4. The method for forming a multi-layer wiring according to claim 2, wherein the polythiazyl layer is formed by using a gas capable of generating free sulfur in plasma under discharge dissociation conditions and an N-based gas. . 5. Gases capable of producing free sulfur in plasma under discharge dissociation conditions include S ₂ F ₂ , SF ₂ , SF ₄ ,
S ₂ F ₁₀ , S ₂ Cl ₂ , S ₃ Cl ₂ , SCl ₂ , S ₂ B
r ₂ , S ₃ Br ₂ , SBr ₂ and H ₂ S, which is at least one selected from the group consisting of:
The multilayer wiring system method according to claim 3 or 4. 6. The multilayer wiring according to claim 4, wherein the N-based gas is at least one selected from the group consisting of N ₂ , NF ₃ , N ₂ F ₄ and N ₂ H _4. System method. 7. A multi-layer wiring structure having a connection hole facing the lower layer wiring in an interlayer insulating film on the lower layer wiring, wherein the lower layer wiring includes a first pattern having a narrow width and the first pattern. A multi-layer wiring / wiring structure, which is in contact with a lower portion and is composed of a second pattern having a width wider than the first pattern width, and has a convex cross section. 8. The first pattern includes an Al-based metal layer,
The multilayer wiring structure according to claim 7, wherein the second pattern includes a refractory metal layer. 9. The multilayer wiring structure according to claim 7, wherein the first pattern width is 0.5 μm or less.