JP3331065B2 - Method for forming contact hole in semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for forming a contact hole on a semiconductor substrate by a self-alignment method.

[0002]

2. Description of the Related Art With the recent high integration of devices,
As the pattern size becomes finer, the margin for misalignment in photolithography is reduced. Therefore, as a method for forming a contact hole that exposes a semiconductor substrate, a self-alignment method has been proposed in which an etching mask pattern larger than the actual contact hole size is formed and a contact hole is formed using a surrounding pattern. .

FIGS. 32 to 38 are process sectional views showing a method of forming a contact hole by a conventional flattening self-alignment method.

A field oxide film 2 used for element isolation is formed on a silicon substrate 1 shown in FIG. 32 by a selective oxidation method, and an active region (element region) is separated by a field oxide film (element isolation region) 2 ( (FIG. 33). Note that the silicon substrate 1 and the element isolation region 2 are collectively referred to as a semiconductor substrate.

Next, a gate oxide film 3 is formed on the element active region by, for example, a hydrochloric acid oxidation method (FIG. 34). Then, after depositing a polycrystalline Si film (gate electrode) 4 by, for example, a low pressure CVD method, a protective oxide film 5 is deposited thereon by, for example, a normal pressure CVD method. Then, a pattern of a photoresist is formed by ordinary photolithography (resist coating → exposure → development), and dry etching of the protective oxide film 5 is performed using the photoresist as a mask. Next, the photoresist is ashed to form a patterned oxide film 5.
Is used as a mask to dry-etch the gate electrode 4 (FIG. 35). In FIG. 35, the gate electrodes 4a, 4
b is collectively represented as a gate electrode 4. or,
The protective oxide films 5a and 5b are collectively referred to as a protective oxide film 5.

Next, an oxide film is deposited on the entire surface of the wafer by, for example, a low pressure CVD method or the like, and this oxide film is etched back by dry etching to protect the side walls of the gate oxide film 3 and the gate electrode 4. Next, a sidewall oxide film 6 is formed (FIG. 36). The side wall oxide film 6 (6a, 6b, 6c, 6d) and the oxide film 5 (5a, 5b) on the gate electrode 4 form the gate electrode 4 (4a, 4b) during dry etching when forming a contact hole in a later step.
b) is exposed to prevent exposure to short circuit with the upper wiring. Note that the sidewall oxide films 6a, 6b, 6c, and 6d are collectively referred to as sidewall oxide films 6, which correspond to the inclined portions of the first wirings in Examples 1 to 3 described below. .

Next, an oxide film 7 is deposited on the entire surface of the wafer by, for example, a low-pressure CVD method, and subsequently, a stopper film (etching stopper film) (Si
An N film or a film having a selectivity with respect to an oxide film such as polycrystalline Si) 8 is deposited, then an interlayer oxide film 9 is deposited by, for example, a low pressure CVD method, and the interlayer oxide film 9 is etched back by dry etching. By doing so, it is flattened. Thereafter, patterning by photolithography is performed to form a photoresist pattern 10 (FIG. 37). In the figure, 8a,
8b is an inclined portion of the stopper film 8, and 8c is a flat portion thereof.

After that, the contact hole is etched by using the photoresist pattern 10 as a mask.
This is performed by E (reactive ion etching).

[0009]

In FIG. 37, over-etching is performed to expose the semiconductor substrate 1. However, since the interlayer oxide film 9 is flattened, the inclined portions 8a and 8b of the stopper film 8 are formed first. Exposure to For this reason, it is preferable that the selectivity with respect to the stopper film 8 in the inclined portions 8a and 8b is high. However, since the inclined portions 8a and 8b are more easily etched by the ion sputtering than the flat portions 8c, the protective oxide films 5a and 5b and the sidewall oxide films 6b and 6b for protecting the gate electrodes 4 (4a and 4b) are formed.
6c is etched to form a gate electrode 4 (4a, 4b).
Are exposed as shown in FIG.

On the other hand, when the thicknesses of the protective oxide film 5 (5a, 5b) and the stopper film 8 are increased, the exposure of the gate electrode is improved, but the step in the surface becomes remarkable. Is difficult.

As described above, in the conventional method of forming a contact hole by the flattening self-alignment method illustrated in FIGS. 32 to 38, the stopper film is etched by the ion sputtering at the inclined portion of the sidewall oxide film. Therefore, the protective oxide film and the sidewall oxide film on the gate electrode are etched from that portion,
There is a problem that the gate electrode is exposed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a main object of the present invention is to prevent a stopper film from penetrating on an inclined portion of a first wiring so that a margin for photolithography is small. That is, a contact hole can be formed. It is also an additional object to reduce the absolute step, to enable the opening diameter of the contact hole to be controlled to a desired value, and to reduce damage to the main surface of the semiconductor substrate.

[0013]

The invention according to claim 1 is
Forming two adjacent first wirings on the main surface of the semiconductor substrate; forming two adjacent first wirings on and between the first wirings;
Depositing an oxide film on the step and Flip, on the oxide film, film on the stepped bottom of the step on the step
Sputter so that the film thickness above the step is thicker than the thickness
A step of forming a film, a step of dry-etching back the sputtered film under anisotropic conditions until the oxide film on the step bottom is exposed, and a photo-resist on the sputtered film by photolithography. Forming a pattern;
Performing dry etching of the exposed oxide film using the photoresist pattern and the sputtered film as a mask,
Exposing a main surface of the semiconductor substrate.

According to a second aspect of the present invention, there is provided the method for forming a contact hole in a semiconductor device according to the first aspect, wherein the step of performing the ashing process of the photoresist pattern after the dry etching of the oxide film; further comprises the step of selecting removed by wet-type etching solution.

According to a third aspect of the present invention, in the method for forming a contact hole of a semiconductor device according to the second aspect, the sputtered film is made of a TiN film or a Ti film, and the wet etching solution is NH ₄ OH / H _2. O ₂ .

According to a fourth aspect of the present invention, there is provided the contact hole forming method for a semiconductor device according to the second aspect, wherein the sputtered film is formed of a TiSix film, and the wet etching solution is H ₂ O: HF = 50: 1. Of hydrofluoric acid prepared at the ratio of

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[Action]

(Invention of Claim 1) Two first wirings are formed adjacently on the main surface of the semiconductor substrate. Then, a step occurs between the first wirings due to the contact between the inclined portion of the first wiring and the main surface of the semiconductor substrate. The oxide film covers the first wiring and between the first wirings. Therefore, a step occurs also in the oxide film between the first wirings. Sputtered film has step coverage,
That is, since the sputtered film is formed on the oxide film under the condition of poor coverage, the thickness of the sputtered film is larger at the upper part of the step than at the bottom of the step. Therefore, at the stage where the sputtered film is anisotropically etched to expose the oxide film at the bottom of the step, the sputtering on the first wiring and the upper part of the step of the first wiring, that is, the upper part of the slope of the first wiring, is performed. All of the film remains without being etched, and still covers the first wiring including its upper part and the inclined part. Therefore, a photoresist pattern is formed on the remaining sputtered film, and the exposed oxide film at the bottom between the first wirings is dry-etched using the photoresist pattern and the sputtered film on the inclined portion of the first wiring as a mask. If it is removed, the main surface of the semiconductor substrate is exposed at the bottom between the first wirings.

(Invention of Claim 2) The ashing process of the photoresist pattern leaves a sputtered film on the first wiring. Since the wet etchant has a high selectivity with respect to the oxide film on the first wiring and the semiconductor substrate, the chemical reaction between the wet etchant and the sputter film proceeds, and as a result, only the sputter film is selectively removed. A contact hole is formed.

(Invention of claim 3) TiN film or T
When the i-film is formed as a sputtered film, NH ₄ OH
/ H ₂ O ₂ functions as a wet etching solution for the sputtered film, and selectively removes the TiN film or the Ti film on the first wiring.

(Invention of Claim 4) When a TiSix film is formed as a sputtered film, H ₂ O: HF = 5
The hydrofluoric acid solution prepared at a ratio of 0: 1 functions as a wet etching solution for the sputtered film, and selectively removes the TiSix film on the first wiring.

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【Example】

(Example 1) Example 1 according to the present invention will be described with reference to the cross-sectional views of each step in FIGS. Incidentally, in these figures, reference numerals 1 to 7 are shown in FIGS.
Means the same as those shown in the above, and therefore, their description is omitted.

FIG. 1 is a sectional view of the first wiring formed on one surface (main surface) of the semiconductor substrate (1, 2) by the flow from FIG. 32 to FIG. Here, the term “first wiring” is a general term for both the wiring part composed of (4a, 6a, 6b, 5a) and the wiring part composed of (3, 4b, 6c, 6d, 5b). Each of the sidewall oxide films 6a, 6b, 6c, 6d forms an inclined portion of the first wiring, and due to the contact between the sidewall oxide films 6b, 6c and the semiconductor substrate (1, 2), A step occurs between the first wirings. Of these steps, portions along the outer shapes of the inclined portions 6b and 6c are called upper steps, and portions below the upper steps are called bottoms. The lowest part (flat part) of the step bottom is called the bottom between the first wirings.

Next, the oxide film 7 is formed by, for example, a low pressure CVD method.
Is deposited (FIG. 2).

Next, the sputtered film 11 is sputtered under conditions (poor coverage) where the step coverage is poor such that the film thickness above the step is thicker than the film thickness at the step bottom of the first wiring. Deposits (FIG. 3). As the sputtered film 11, a metal film such as TiN or Ti or a silicide film such as TiSix can be used. For example, when depositing a TiN film under the above conditions, plasma is generated in a state where the Ar / N ₂ -based gas is controlled at a pressure of 0.7 Pa, and ions are incident on the target with a DC bias of 5 kW. , 40 to 50 mm from target
mm for a wafer placed at a distance of mm. In general, the step coverage can be deteriorated by (1) increasing the gas pressure or (2) increasing the distance between the target and the wafer.

Next, the thickness of the sputtered film 11 at the bottom of the step between the first wirings is smaller than that at the top of the step.
Until the sputtered film 11 at the bottom of the step is completely removed, etch back is performed under anisotropic dry etching conditions (FIG. 4). In the first embodiment, in an ECR (Electron Cyclotron Resonance) etching apparatus having a high-density plasma source, a Cl ₂ -based gas is used to introduce a plasma of 1400 W while controlling the pressure to 0.1 Pa. And a rf of 60 W
The above-described etching is realized by applying a bias.

At this stage, the sputtered film 11 on the step and on the first wiring still remains so as to surround the first wiring.

Next, a photoresist pattern 1 is formed at a place where a contact hole is to be formed by ordinary photolithography.
0 is formed (FIG. 5), and the Si substrate 1 is formed by dry etching.
The oxide film 7 is etched until the main surface is exposed (FIG. 6). In this etching step, etching is performed using the photoresist pattern 10 as a mask in a direction parallel to the first wiring and using the sputtered film 11 as a mask in a direction perpendicular to the first wiring. 11a and 11b in FIG.
Is an inclined portion that covers the first wiring in the sputtered film 11.

Next, the photoresist pattern 10 is removed by ashing (FIG. 7), and the sputtered film 11 (with a wet etching solution capable of realizing a high selectivity with respect to the oxide film 7 and the Si substrate 1). 11a and 11b) are selectively removed. Thus, a contact hole is formed without etching both oxide films 7 (FIG. 8). And
As a result of the removal of the sputter films 11a and 11b as the stopper films, the sputter films 11a and 11b are removed as compared with the prior art in which the stopper film 8 is not finally removed as shown in FIG.
The absolute step of the device can be reduced by the thickness of the film.

Here, TiN or T
When i is adopted, NH _{4 is} used as a wet etching solution.
OH / H ₂ O ₂ is used, and TiSi
When an x film is used, H _{2 is} used as a wet etching solution.
By using hydrofluoric acid solution prepared at a ratio of O: HF = 50: 1, the sputtered film 11 can be selectively removed. For example, a TiSix film is adopted as the sputter film 11 and H
_When selective removal is performed using hydrofluoric acid solution prepared at a ratio of ₂ O: HF = 50: 1, the selectivity of the TiSix film to the oxide film 7 is 20 or more, and the selectivity of the TiSix film to the Si substrate 1 is ∞.

As described above, according to the first embodiment, the sputter condition of the sputtered film 11 is appropriately changed by increasing the gas pressure or moving the wafer away from the target, so that the inclined portion of the first wiring is formed. The cover margin (film thickness) of the upper sputtered film 11 (11a, 11b) as a stopper film can be arbitrarily set. Therefore, FIG.
It is possible to prevent the stopper film (sputter film 11) from penetrating through the inclined portion of the first wiring even if the dry etching condition for the oxide film 7 in the step (1) is not so high that the selectivity ratio to the stopper film is high. Becomes

In the dry etching of the oxide film 7 in the step of FIG. 6, a gas usually used for etching the oxide film, for example, a CHF ₃ / CF ₄ gas may be used, and the conventional SiN film is used as a stopper. Equivalent or higher selectivity to stopper can be realized without using a special gas system required at the time (8 in FIG. 37). Therefore, it is possible to reduce capital investment in developing a semiconductor device.

Embodiment 2 Embodiment 2 of the present invention is described with reference to FIG.
This will be described with reference to FIGS. In these drawings, reference numerals 1 to 7 are the same as those shown in FIGS. 32 to 37 of the conventional example, and the description thereof will be omitted.

FIG. 9 is a sectional view of the first wiring formed on the main surface of the semiconductor substrate (1, 2) by the flow from FIG. 32 to FIG. The concepts of the first wiring, the top of the step, and the bottom of the step are as described in the first embodiment.

Next, for example, by the low pressure CVD method, the SiN
The film 12 is deposited to be thicker than the thickness of the first wiring above the step (FIG. 10). Further, for example, after flattening by performing reflow at 800 ° C., first etching is performed by dry etching.
The above etch-back is performed until the oxide film 5 (5a, 5b) above the step of the wiring is exposed (FIG. 11).

Next, a first polycrystalline Si film 13 is deposited by, for example, a low pressure CVD method (FIG. 12). The first polycrystalline Si film 13 corresponds to a first stopper film.

Next, a photoresist pattern 10 (the pattern 10 has an opening above the first wiring) is formed at a place where a contact hole is to be formed by ordinary photolithography (FIG. 13), and FIG. Dry etching is performed until the SiN film 12 etched back in the step (2) is exposed (FIG. 14). Thereafter, the photoresist pattern 10 is removed by ashing (FIG. 15).

Next, a second polycrystalline Si film 14 is deposited by, for example, a low pressure CVD method (FIG. 16), and dry etching back is performed for the thickness of the deposited second polycrystalline Si film 14 (FIG. 17). ). In the figure, reference numerals 14a and 14b denote protective oxide films 5a and 5b and sidewall oxide films 6b of the first wiring.
6C is a frame of the second polycrystalline Si film 14 formed so as to cover the upper part of 6c. Here, the second polycrystalline Si film 1
4 corresponds to a second stopper film.

Next, using the first polycrystalline Si film 13 and the frames 14a and 14b of the second polycrystalline Si film as masks, the SiN film 1 is exposed under anisotropic conditions so that the Si substrate 1 is not exposed.
2 is performed halfway (FIG. 18). In the figure, the partial etching portion of the SiN film after the dry etching is denoted by 15. Here, the reason why the dry etching of the SiN film 12 is performed only halfway is that the first polycrystalline Si film 13 and the frames 14a and 14b of the second polycrystalline Si film are dry etched under isotropic conditions in the next step. This is to prevent the Si substrate 1 from being etched at the same time as the removal.

Next, the frames 14a and 14b of the first polycrystalline Si film 13 and the second polycrystalline Si film are removed by dry etching under isotropic conditions (FIG. 19). In the second embodiment, in the downflow etching apparatus, CF ₄ / O ₂
The etching is performed by plasma generated by introducing a microwave of 1400 W while controlling the pressure of the system gas to 53 Pa.

Finally, a phosphoric acid treatment (hot phosphoric acid treatment) maintained at, for example, 160 ° C. is performed until the SiN film 12 remaining between the first wirings (part 15 in FIG. 19) is completely removed. As a result, a contact hole is formed (FIG. 20).

As described above, according to the second embodiment, by changing the film thickness of the first polycrystalline Si film and the second polycrystalline Si film, the stopper film ( Here, the cover margin of the two polycrystalline Si films 13, 14a, and 14b) can be set arbitrarily, and thereby, a contact hole having a desired diameter can be formed. That is, the dimension of the opening diameter of the contact hole is
It is determined depending on the range between the two frames 14a and 14b. Moreover, at this time, there is no possibility that the gate electrodes 4a and 4b are exposed through the stopper films 13 and 14.

At the stage when the formation of the contact hole is completed, portions other than the contact hole opening are made of SiN.
Since the state is flattened by the film 12, the wiring resistance of the second wiring deposited in the next step can be reduced.

Further, in the second embodiment, since the contact hole can be formed without exposing the substrate portion which is the bottom of the contact hole to dry etching, the contact hole can be formed with low damage. is there.

Since the frames 14a and 14b of the first polycrystalline Si film 13 and the second polycrystalline Si film are removed, the absolute step of the semiconductor device is reduced by the thickness of these stopper films. You can also.

(Embodiment 3) Embodiment 3 according to the present invention is
Description will be made based on the cross-sectional views of the steps shown in FIGS. In these figures, 1 to 7 are the same as those shown in FIGS. 32 to 38 of the conventional example, and the description thereof is omitted.

FIG. 21 is a sectional view of the first wiring formed on the main surface of the semiconductor substrate (1, 2) according to the flow from FIG. 32 to FIG. Also in this case, the concepts of the first wiring, the top of the step, and the bottom of the step are the same as those in the first embodiment. Next, a SiN film 12 is deposited thickly by, for example, a low pressure CVD method (FIG. 22), flattened by performing, for example, reflow at 800 ° C., and then subjected to first etching by dry etching.
The etch back is performed until the oxide film 5 (5a, 5b) above the step of the wiring is exposed (FIG. 23).

Next, a first sputtered film 16 is deposited (FIG. 24). As the first sputtered film 16, TiN,
A metal film such as Ti or a silicide film such as TiSix can be used. The first sputtered film 16 corresponds to a first stopper film.

Next, a photoresist pattern 1 is formed at a place where a contact hole is to be formed by a usual photolithography method.
0 is formed (FIG. 25), and after dry etching is performed until the SiN film 12 etched back in the step of FIG. 23 is exposed (FIG. 26), the photoresist pattern 10 is removed by ashing (FIG. 27). ).

Next, a second sputtered film 17 is deposited (FIG. 28), and dry etching back is performed for the thickness of the deposited second sputtered film 17 (FIG. 29). Here, as the second sputtered film 17, the same metal film as TiN or Ti or the silicide film such as TiSix as the first sputtered film 16 deposited in FIG. 24 can be used. In FIG. 29, reference numerals 17a and 17b denote protective oxide films 5a and 5a of the first wiring.
This is a second sputtered film frame formed so as to cover the upper portions of 5b and sidewall oxide films 6b and 6c (inclined portions of the first wiring). The second sputtered film 17 corresponds to a second stopper film.

Next, using the first sputtered film 16 and the frames 17a and 17b of the second sputtered film as masks, as shown by reference numeral 18 in FIG. 30, the SiN film 12 is exposed until the main surface of the Si substrate 1 is exposed. Is dry-etched under anisotropic conditions (FIG. 30).

Finally, the first sputtered film 16 and the second sputtered film frame 17a are formed by a wet etching solution capable of realizing a high selectivity with respect to the oxide films 5, 6, the SiN film 12, and the Si substrate 1. , 17b (FIG. 3)
1). Thus, a contact hole can be formed without exposing the gate electrodes 4a and 4b, that is, without damaging the first wiring, and the first sputtered film 16 can be formed.
And the film thickness of the frames 17a and 17b of the second sputtered film,
It is possible to reduce the absolute step of the semiconductor device.

When a TiN film or a Ti film is used as the first sputtered film 16 and the second sputtered film 17, NH ₄ OH / H ₂ O ₂ is used as a wet etching solution, and the first sputtered film is used. 16 and the second sputtered film 17
When the iSix film is employed, the first and second sputtered films 16 and 17 are formed by employing a hydrofluoric acid solution prepared at a ratio of H ₂ O: HF = 50: 1 as a wet etching solution.
(17a, 17b) can be selectively removed. For example,
TiSix as the first and second sputtered films 16 and 17
When a film is used and selective removal is performed using hydrofluoric acid water prepared at a ratio of H ₂ O: HF = 50: 1, the selectivity of the TiSix film to the oxide films 5 and 6 is 20 or more, and S
The selectivity with the iN film 12 is 20 or more,
The selection ratio with respect to the substrate 1 is Δ.

As described above, according to the third embodiment, by changing both the thickness of the first sputtered film and the thickness of the second sputtered film, the stopper film (here, The cover margin of both sputtered films 16, 17a and 17b) can be set arbitrarily. Therefore, a contact hole having a desired diameter can be formed without causing the stopper film to penetrate.

In addition, in the case of the third embodiment, since dry etching under anisotropic conditions is adopted for the final opening of the contact hole, a desired formation of the contact hole can be performed more easily than the opening method of the second embodiment. Excellent dimensional control over diameter.

At the stage when the formation of the contact hole is completed, portions other than the contact hole opening are formed of SiN.
Since the state is flattened by the film 12, the wiring resistance of the second wiring deposited in the next step can be reduced. In addition, in the case of the third embodiment, the flatness as compared with the second embodiment is good because the SiN film is not thinned by the final phosphoric acid treatment as in the second embodiment.

Further, in the third embodiment, one less dry etching step is required as compared with the second embodiment.
This simplifies the flow and reduces the number of steps.

As described above, each of the embodiments relates to a semiconductor device. In particular, in the case where a wiring and a contact hole of a semiconductor substrate are formed, even if the overlay is shifted at the time of resist patterning of photolithography, the problems of the prior art are not solved. A good contact hole can be formed by the self-alignment method in which the above is improved.

[0072]

According to the first aspect of the present invention, the first contact hole is formed by the self-alignment method.
It is possible to prevent the stopper film (sputter film) from penetrating on the inclined portion of the wiring. For this reason, it is possible to form minute contact holes even in a state where the margin of photolithography is small.

In particular, since the cover margin (film thickness) of the stopper film can be arbitrarily set, even if the dry etching condition for the oxide film is a condition where the selectivity ratio of the stopper film to the stopper film is not so high, the stopper film can be used. Can be prevented.

In addition, in the dry etching of the oxide film, a versatile gas usually used in dry etching can be used, and a special gas required when a conventional SiN film is used as a stopper film is used. An equivalent or higher selectivity ratio of the stopper film can be realized without using the same. For this reason, there is also an advantage that equipment investment in developing a semiconductor device can be reduced.

According to the second aspect of the present invention, since the stopper film (sputter film) is selectively removed, a contact hole can be formed between the first wirings without damaging the first wirings by etching. As compared with the conventional case, there is an effect that the absolute step in the semiconductor device can be reduced by an amount corresponding to the removal of the stopper film.

According to the third aspect of the present invention, if NH ₄ OH / H ₂ O ₂ is used as the wet etching solution, a TiN film or a metal film such as a Ti film is used as a sputtered film and the first wiring is formed on the inclined portion. This has the effect of preventing the stopper film (sputter film) from penetrating.

In the invention according to claim 4, if a hydrofluoric acid solution prepared at a ratio of H ₂ O: HF = 50: 1 is used as the wet etching solution, a silicide film made of a TiSix film is used as a sputtering film. This has the effect of preventing penetration of a stopper film (sputtered film) on the inclined portion of the first wiring.

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[Brief description of the drawings]

FIG. 1 is a process flow sectional view according to a first embodiment of the present invention.

FIG. 2 is a process flow cross-sectional view related to Example 1 of the present invention.

FIG. 3 is a process flow cross-sectional view related to Example 1 of the present invention.

FIG. 4 is a process flow sectional view according to the first embodiment of the present invention.

FIG. 5 is a process flow sectional view according to the first embodiment of the present invention.

FIG. 6 is a process flow sectional view according to the first embodiment of the present invention.

FIG. 7 is a process flow sectional view according to the first embodiment of the present invention.

FIG. 8 is a process flow sectional view according to the first embodiment of the present invention.

FIG. 9 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 10 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 11 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 12 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 13 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 14 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 15 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 16 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 17 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 18 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 19 is a sectional view of a process flow according to the second embodiment of the present invention.

FIG. 20 is a process flow sectional view according to a second embodiment of the present invention.

FIG. 21 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 22 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 23 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 24 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 25 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 26 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 27 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 28 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 29 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 30 is a process flow sectional view relating to Example 3 of the present invention.

FIG. 31 is a process flow sectional view according to a third embodiment of the present invention.

FIG. 32 is a sectional view of a process flow relating to a conventional example.

FIG. 33 is a process flow sectional view of a conventional example.

FIG. 34 is a process flow sectional view of a conventional example.

FIG. 35 is a sectional view of a process flow relating to a conventional example.

FIG. 36 is a process flow sectional view of a conventional example.

FIG. 37 is a sectional view of a process flow relating to a conventional example.

FIG. 38 is a process flow sectional view of a conventional example.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 element isolation region, 3 gate oxide film, 4, 4a, 4b gate electrode, 5, 5a, 5b protective oxide film, 6, 6a, 6b, 6c, 6d sidewall oxide film, 7 oxide film, 8 Stopper film, 8a, 8b
Inclined portion, 8c flat portion, 9 interlayer oxide film, 10
Photoresist pattern, 11 sputtered film, 11a,
11b Inclined portion, 12 SiN film, 13 first polycrystalline Si film, 14 second polycrystalline Si film, 14a, 14b
Second polycrystalline Si film frame, 15SiN film partial etching portion, 16 first sputtered film, 17 second sputtered film, 17a, 17b second sputtered film frame, 1
8 Anisotropic dry etching part of SiN film.

Claims (4)

(57) [Claims] A step of forming two adjacent first wirings on a main surface of a semiconductor substrate; and forming a step on the first wiring and a step formed between the first wirings.
Depositing an oxide film on the oxide film; and forming a step on the oxide film on the step.
The film thickness on the step top is thicker than the film thickness on the bottom
Forming a sputtered film, dry etching back the sputtered film under anisotropic conditions until the oxide film on the bottom of the step is exposed, and forming a photoetching method on the sputtered film. Forming a photoresist pattern on, and performing dry etching of the exposed oxide film using the photoresist pattern and the sputtered film as a mask,
Exposing a main surface of the semiconductor substrate. 2. A contact hole forming method for a semiconductor device according to claim 1, and performing ashing of the photoresist pattern after dry etching of the oxide film, by the sputtering film dampening formula etchant A method of forming a contact hole in a semiconductor device, further comprising the step of selectively removing. 3. The method according to claim 2, wherein the sputtered film is made of a TiN film or a Ti film, and the wet etching solution is NH ₄ OH / H ₂ O _2. A method for forming a contact hole in a device. 4. The method according to claim 2, wherein the sputtered film is made of a TiSix film, and the wet etching solution is a fluorine compound prepared at a ratio of H ₂ O: HF = 50: 1. A method for forming a contact hole in a semiconductor device, which is an acid water.