JPH08274078A - Etching - Google Patents

Abstract

PURPOSE: To precisely mold a gate electrode with little unevenness by first performing etching under such a condition that a sidewall protection layer may be easily formed on the gate electrode and then under such a condition that a sidewall protection layer may not be easily formed on the gate electrode. CONSTITUTION: After a thick insulating film 2 made of a silicon oxide film as an element insolation region is formed on the surface of a P-type semiconductor substrate 1, a gate insulating film 3 made of a silicon oxide film is formed thereon. Subsequently, a polysilicon layer 4 300nm thick is deposited. Then, after a resist is deposited, the resist 5 is patterned by lithography. Etching is performed using mixed gas of HBr and Cl2 at a ratio of HBr:Cl2 =10:1, where a sidewall protection layer 6 may be easily formed on the lateral side of the polysilicon layer 4. Then, etching is performed using gas of HBr and Cl2 mixed at a ratio of HBr:Cl2 =5:1, where a sidewall protection layer may not be easily formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method for a semiconductor device having a gate electrode, and more particularly to an etching method capable of forming a good anisotropic shape in a gate electrode forming step.

[0002]

2. Description of the Related Art As semiconductor devices have become more highly integrated and have higher performance as seen in VLSI and the like in recent years, high anisotropy, high speed, especially in etching of gate electrodes,
A highly selective technique is desired.

At present, a polysilicon gate or a polycide gate is mainly used as a gate electrode. However, when impurities are contained in polysilicon, electrons in the polysilicon are generated when the gate electrode is formed by etching. By moving to the etchant, the etching reaction is promoted, and as a result, side etching occurs as shown in FIG. 3A, which makes it difficult to perform highly accurate anisotropic etching. In FIG. 3A, 21 is a semiconductor substrate, 22 is a thick insulating layer for element isolation, 23 is a gate insulating film, 24 is a polysilicon gate electrode, and 25 is a resist pattern. Here, especially when the gate electrode is a polycide gate, a difference in etching characteristics occurs between the refractory metal silicide 26 and the polysilicon 24 as shown in FIG. There is a problem in that the polycide element is etched deeper than 26, resulting in a defective shape such as film peeling. 27 is a silicon oxide film.

As a method of reducing the side etching of the gate electrode as described above, as described in JP-A-4-142736, an anisotropic shape is formed while forming a sidewall protective film for preventing the side etching. A method of forming the is proposed. This method uses a gas system capable of accumulating sulfur while cooling the substrate to be etched to 0 ° C. or lower to form an anisotropic shape while forming a sidewall protective film made of sulfur or the like. , To try to solve the problem of side etch. However, in the etching using the side wall protective film, the shape of the side wall protective film 29 formed on the polycide gate electrode 28 becomes tapered as shown in FIG. Since it varies depending on the type, it also causes variations in the line width. Furthermore, the substrate to be etched is
Since it is necessary to carry out the reaction while cooling to below 0 ° C, a cooling mechanism for that is required, and there is also a problem that the apparatus becomes large.

There is also a method of patterning a resist so as to be larger than the mask size in consideration of the amount of side etching. However, this method reduces the focus margin in lithography, so that miniaturization can be performed with high accuracy. It is difficult.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional techniques.
An object of the present invention is to provide an etching method capable of forming a gate electrode that can be formed with high precision and has less variation by performing etching in two steps (etching in which the amount of the sidewall protective film attached is in two steps). And

Another object of the present invention is to provide an etching method capable of obtaining a gate electrode which can be formed with high precision and has less variation by forming a side wall of an oxide film instead of a side wall protection film. To do.

[0008]

In order to achieve the above-mentioned object, in the etching method of the present invention, in the method of etching a gate electrode in a semiconductor device, etching is performed under the condition that a side wall protective film is easily formed on the gate electrode. The main feature is that it includes a first etching step to be performed and a second etching step to perform etching under conditions in which the sidewall protection film is difficult to form on the gate electrode.

Further, in the etching method of the present invention,
In a method of etching a gate electrode in a semiconductor device, a step of forming a polysilicon layer on a gate insulating film, a step of forming a silicon oxide film on the polysilicon layer, and a step of selectively removing and patterning the silicon oxide film A step of forming a CVD oxide film on the polysilicon layer and the patterned silicon oxide film, and CV
A step of selectively removing the D oxide film to leave a CVD oxide film above and to the side of the patterned silicon oxide film; and a step of etching the polysilicon layer using the patterned CVD oxide film as a mask The main feature is to have.

[0010]

According to the present invention, by performing the two-step etching in which the ease of forming the side wall protective film is different, it is possible to prevent the gate electrode from being formed into a taper shape and perform the etching with a reduced side etching amount. .

Further, according to the present invention, by forming the side wall instead of the side wall protective film, it is possible to prevent the gate electrode from being tapered and to reduce the side etch amount.

[0012]

EXAMPLES The present invention will now be described in more detail with reference to examples. FIG. 1 shows an N + polysilicon gate transistor according to the first embodiment of the present invention (where N + is + in the upper right corner of N).
Indicates a high concentration N type. It is sectional drawing which shows the manufacturing method of the following). Figure 1
In (a), for example, a thick insulating layer 2 made of a silicon oxide film to be an element isolation region is formed on the surface of a semiconductor substrate 1 having a conductivity type of P, and then a gate insulating film 3 made of a silicon oxide film is formed. Here, in this embodiment, the N + polysilicon gate transistor is obtained by using the P type semiconductor substrate, but it is of course possible to form the P + polysilicon gate transistor by using the N type substrate as the substrate. is there. Next, as shown in FIG. 1B, a polysilicon layer 4 is formed to a thickness of 350 nm, for example. Next, as shown in FIG. 1C, a resist is deposited, and then the resist 5 is patterned by a lithography method. Up to this point, formation is performed in the same manner as the conventional method. Next, as shown in FIG. 1D, the polysilicon layer 4 is formed, for example, from the surface by using an HBr / Cl ₂ mixed gas in which the mixing ratio of the etching gas is HBr: Cl ₂ = 10: 1.
nm etching to remove. At this time, HBr / Cl ₂
It is important to set the mixing ratio of the above as described above, and by setting such a mixing ratio, the side wall protective film 6 is formed on the side surface of the polysilicon layer 4 in the portion covered with the resist 5. Next, as shown in FIG. 1E, for example, HB: Cl ₂ = 5: 1 was used as the etching gas mixing ratio.
The polysilicon layer 4 is etched using a mixed gas of r / Cl ₂ . At this flow rate ratio of the HBr / Cl ₂ mixed gas, the side wall protective film is unlikely to adhere, and the etching shape of the side wall 7 of the polysilicon layer 4 is tapered as shown as the side wall protective film 6 in FIG. It does not become a shape. Finally, by removing the side wall protective film 6 and the resist 5,
The gate electrode 8 is formed as shown in FIG.

In the above-described embodiment, HBr: Cl ₂ = 1 as a condition for forming the side wall protective film.
0: 1 and subjected to etching using HBr / Cl ₂ mixture gas, and as difficult conditions sidewall protective film is formed, HBr: Cl ₂ = 5: etching with 1 and the HBr / Cl ₂ mixed gas I am doing it. However, the conditions for the etching so that the amount of deposition of the sidewall protective film is in two stages are not limited to these. That is,
HBr / Cl may be used without departing from the scope of the present invention.
The mixing ratio of ₂ may be changed, another etching gas may be used in consideration of the mixing ratio, or different etching gases may be used in the two-step etching process. Furthermore, in the present invention, the gate electrode is a polysilicon gate electrode, but it may be another gate electrode, for example, a gate electrode having a polycide structure. In this case, as a matter of course, it is necessary to consider the condition that the side wall protective film is easily formed and the condition that the side wall protective film is hard to be formed.

According to the above-mentioned embodiment, the CD loss is reduced as compared with the conventional method, and it is possible to prevent the gate electrode width from being varied due to the variation in the adhesion amount of the sidewall protection film.

FIG. 2 is a sectional view showing a method of manufacturing a polycide gate structure transistor according to the second embodiment of the present invention. First, in FIG. 2A, for example, a thick insulating layer 2 made of a silicon oxide film to be an element isolation region is formed on the surface of a semiconductor substrate 1 having a conductivity type of P, and then a gate insulating film 3 made of a silicon oxide film is formed. Form. Here, in the present embodiment, the N + polycide gate transistor is obtained by using the P type semiconductor substrate, but it is of course possible to form the P + polycide gate transistor by using the N type substrate as the substrate. is there. Next, as shown in FIG. 2B, a polysilicon layer 4 is formed to a thickness of, for example, 180 nm, and a refractory metal silicide layer, for example, a tungsten silicide (WSix) film 9 is formed to a thickness of 100 nm. Then, the silicon oxide film 10 is further formed to a thickness of 120 nm. Next, as shown in FIG. 2C, after depositing a resist, the resist 5 is patterned by a lithography method. Next, as shown in FIG. 2D, for example, the mixing ratio of the etching gas is set to HBr: Cl ₂
= 5: 1 HBr / Cl ₂ mixed gas is used to prevent the side wall protective film from adhering to the silicon oxide film 10 and WSi.
The x film 9 is sequentially etched to remove the lower part of the resist 5. Then, after removing the resist 5, FIG.
As shown in, the CVD oxide film 11 is formed with a thickness of, for example, 30 nm. Next, as shown in FIG.
The D oxide film 11 is etched back. At this time, C is formed only above and on the sides of the silicon oxide film 10 and the WSix film 9.
The VD oxide film 11 is left. Finally, as shown in FIG. 2G, the polysilicon layer 4 is etched so that the sidewall protection film is not attached, and the gate electrode 12 is obtained. At this time, in order to etch the polysilicon layer 4 so that the sidewall protective film is not attached, the flow rate ratio is set to HB.
A HBr / Cl ₂ mixed gas with r: Cl ₂ = 5: 1 may be used.

In the above-described embodiment, HBr / Cl ₂ is set to HBr: Cl ₂ = 5: 1 as an etching gas in the etching process of the silicon oxide film 10 and the WSix film 9 and the etching process of the polysilicon layer 4.
A mixed gas is used. However, the etching conditions are not limited to these. That is, within a range not departing from the gist of the present invention, that is, under the condition that the sidewall protective film is difficult to adhere, the HBr / Cl ₂ mixing ratio may be changed, or another etching gas may be used in consideration of the mixing ratio. Different etching gases may be used in the two etching processes.

Further, although the case of forming the gate electrode having the polycide structure has been described in the present embodiment, it is also possible to form the polysilicon gate electrode by a similar method. In that case, the step of forming the refractory metal silicide layer 9 described above may be omitted, and the other steps can be similarly formed.

Further, the CVD oxide film 11 is etched back to etch the silicon oxide film 10 and the refractory metal silicide layer 9.
In the step of patterning so that the CVD oxide film 11 remains only above and on the sides of the silicon oxide film 10,
And CV left on the side of the refractory metal silicide layer 9
The width (sidewall width) of the D oxide film 11 is a narrow width of the polysilicon as the gate electrode that is etched by the usual method in the subsequent etching step of the polysilicon layer 4 (that is, FIG. 3B). The width of the overetched portion of the polysilicon layer 24 with respect to the silicon oxide film 27 and the refractory metal silicide layer 26 by the conventional method shown in FIG. Becomes possible,
It is more suitable.

According to the present embodiment, the polysilicon layer is not etched deeper than the WSix layer as seen in the prior art. Furthermore, it is possible to prevent the gate electrode width from varying due to variations in the amount of the sidewall protective film attached.

[0020]

According to the present invention as set forth in claims 1 and 2, by performing two-step etching in which the ease of forming the side wall protective film is different, it is possible to prevent the gate electrode from being tapered and to prevent the side etching amount. Can be reduced.
In particular, etching of a gate electrode made of two or more kinds of materials such as polycide gate is effective in improving dimensional accuracy.

Further, according to the present invention as set forth in claim 3 or 4, it is possible to prevent the gate electrode from being tapered and to reduce the side etching amount by forming the side wall instead of the side wall protective film. Becomes Further, it is possible to reduce the variation in the gate electrode width due to the variation in the adhesion amount of the sidewall protection film.

Further, according to the invention of claim 5,
Accurately forming the gate electrode by controlling the side wall width so that it is side-etched by the usual method when the polysilicon layer is etched, which is over-etched with respect to the silicon oxide film or the like. Is possible. Particularly in the polycide gate, the effect of preventing the defective shape of the gate as shown in FIG.

[Brief description of drawings]

FIG. 1 is a sectional view showing an etching method according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an etching method according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a problem caused by a conventional etching method.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Layer 3 Gate Insulating Film 4 Polysilicon Layer 5 Resist 6 Sidewall Protective Film 7 Sidewall of Gate Electrode 8 and 12 Gate Electrode 9 WSix Film 10 Oxide Film 11 CVD Oxide Film

Claims (5)

[Claims] 1. A method of etching a gate electrode in a semiconductor device, comprising: a first etching step in which a sidewall protective film is easily formed on the gate electrode; and a condition in which a sidewall protective film is difficult to form on the gate electrode. An etching method comprising: a second etching step of performing etching according to. 2. The gate electrode is a polysilicon gate electrode, and in the first etching step, an HBr flow rate ratio of HBr: CL ₂ ≉10: 1 is used.
/ CL ₂ mixed gas etching, and the second etching step has an etching gas flow rate ratio of HBr: C.
The etching method according to claim 1, wherein the etching is performed by using a HBr / CL ₂ mixed gas such that L ₂ ≉5: 1. 3. A method of etching a polysilicon gate electrode in a semiconductor device, comprising the steps of forming a polysilicon layer on a gate insulating film, forming a silicon oxide film on the polysilicon layer, and forming the silicon oxide film. Selectively removing and patterning, a step of forming a CVD oxide film on the polysilicon layer and the patterned silicon oxide film, and a step of selectively removing the CVD oxide film and the patterned silicon An etching method comprising: a step of patterning so as to leave a CVD oxide film above and to the side of the oxide film; and a step of etching the polysilicon layer using the patterned CVD oxide film as a mask. 4. A method of etching a polycide gate electrode in a semiconductor device, comprising: forming a polysilicon layer on a gate insulating film; forming a refractory metal silicide layer on the polysilicon layer; Forming a silicon oxide film on the melting point metal silicide layer, selectively removing and patterning the silicon oxide film and the refractory metal silicide layer, and forming a silicon oxide film on the polysilicon layer and the patterned silicon oxide film. CV
A step of forming a D oxide film, and a step of selectively removing the CVD oxide film so as to leave a CVD oxide film above and on the sides of the patterned silicon oxide film and refractory metal silicide layer. An etching method comprising: etching the polysilicon layer using the patterned CVD oxide film as a mask. 5. In the step of patterning the CVD oxide film, the width (sidewall width) of the CVD oxide film left on the side of the patterned silicon oxide film and refractory metal silicide layer is the polysilicon layer. 5. The etching method according to claim 3 or 4, wherein the thinning width is substantially equal to that in the etching step.