KR100312655B1 - Method of forming gate electrode for semiconductor device - Google Patents
Method of forming gate electrode for semiconductor device Download PDFInfo
- Publication number
- KR100312655B1 KR100312655B1 KR1019990058396A KR19990058396A KR100312655B1 KR 100312655 B1 KR100312655 B1 KR 100312655B1 KR 1019990058396 A KR1019990058396 A KR 1019990058396A KR 19990058396 A KR19990058396 A KR 19990058396A KR 100312655 B1 KR100312655 B1 KR 100312655B1
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- film
- gas
- tungsten
- nitride film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 42
- 239000010937 tungsten Substances 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 37
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- -1 tungsten nitride Chemical class 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 abstract description 25
- 239000000203 mixture Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
Abstract
본 발명은 텅스텐막을 이용한 게이트 전극의 형성시 게이트 산화막 특성을 확보함과 더불어 기판의 리세스를 방지할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공한다.The present invention provides a method of forming a gate electrode of a semiconductor device capable of securing a gate oxide film characteristic when forming a gate electrode using a tungsten film and preventing the recess of the substrate.
본 발명에 따라, 필드 산화막이 형성된 반도체 기판 상에 게이트 산화막, 텅스텐 질화막, 티타늄 질화막, 텅스텐막 및 마스크층을 순차적으로 형성하고, 마스크층 및 텅스텐막을 제 1 식각으로 선택적으로 식각한다. 그런 다음, 티타늄 질화막을 제 2 식각으로 선택적으로 식각하고, 텅스텐 질화막을 게이트 산화막 및 기판과의 식각선택비가 우수한 개스를 이용한 제 3 식각으로 선택적으로 식각하여 게이트 전극을 형성한다. 또한, 제 1 식각은 SF6개스를 이용하여 건식식각으로 진행하고, 제 2 식각은 Cl2개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행하며, 제 3 식각은 NF3개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행한다.According to the present invention, a gate oxide film, a tungsten nitride film, a titanium nitride film, a tungsten film and a mask layer are sequentially formed on a semiconductor substrate on which a field oxide film is formed, and the mask layer and the tungsten film are selectively etched by the first etching. Then, the titanium nitride film is selectively etched by the second etching, and the tungsten nitride film is selectively etched by the third etching using a gas having an excellent etching selectivity with the gate oxide film and the substrate to form a gate electrode. In addition, the first etching proceeds to dry etching using SF 6 gas, the second etching proceeds to dry etching using a mixed gas of Cl 2 gas and O 2 gas, the third etching is NF 3 gas and O Proceed to dry etching using a mixture of two gases.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 텅스텐막과 같은 저저항 금속막을 이용한 반도체 소자의 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device using a low resistance metal film such as a tungsten film.
반도체 소자의 고집적화에 따른 RC 딜레이등을 고려하여, 저저항의 게이트 전극이 사용되고 있다. 또한, 고집적화에 따라 PMOS 트랜지스터의표면채널(surface channel)화가 요구되고 있다. 이러한 점을 감안하여 공정진행이 비교적 용이한 물질로서 텅스텐(W)막이 제시되었다. 이때, 텅스텐막은 물리기상증착(physical vapor deposition; PVD)에 의해 증착되고, SF6플라즈마를 이용한 건식식각에 의해 식각된다.In consideration of RC delay due to high integration of semiconductor devices, a low resistance gate electrode is used. In addition, the high integration requires a surface channel of a PMOS transistor. In view of this, a tungsten (W) film has been proposed as a material that is relatively easy to process. At this time, the tungsten film is deposited by physical vapor deposition (PVD) and etched by dry etching using SF 6 plasma.
그러나, 상기한 바와 같이 PVD를 이용하여 텅스텐막을 게이트 산화막에 증착하게 되면, 게이트 산화막의 재스퍼터링(re-sputtering)에 의해 게이트 산화막에 결함이 유발되어 일정한 게이트 산화막 두께를 얻기가 어려울 뿐만 아니라 게이트 산화막의 표면 거칠기(roughness)가 심해지게 된다. 또한, SF6는 실리콘 산화막 또는 실리콘과의 식각선택비가 우수하지 못하여, 텅스텐막의 식각시 기판이 과도식각 (over-etch)되어 기판에 리세스(recess)를 유발함으로써 이후 채널영역에서의 동작오류를 야기시킴으로써, 결국 소자의 특성 및 신뢰성을 저하시킨다.However, when the tungsten film is deposited on the gate oxide film using PVD as described above, defects are caused in the gate oxide film by re-sputtering of the gate oxide film, and it is difficult to obtain a constant gate oxide film thickness as well. The surface roughness of becomes severe. In addition, SF 6 does not have an excellent etching selectivity with silicon oxide film or silicon, and the substrate is over-etched during etching of the tungsten film, causing recesses in the substrate, thereby preventing operation errors in the channel region. By doing so, eventually deteriorates the characteristics and reliability of the device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 텅스텐막을 이용한 게이트 전극의 형성시 게이트 산화막 특성을 확보함과 더불어 기판의 리세스를 방지할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-described problems, and provides a method of forming a gate electrode of a semiconductor device that can secure the gate oxide film characteristics when forming the gate electrode using a tungsten film and can prevent the recess of the substrate. Has its purpose.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols on the main parts of drawing
10 : 반도체 기판 20 : 필드 산화막10 semiconductor substrate 20 field oxide film
30 : 게이트 산화막 40 : 텅스텐 질화막30 gate oxide film 40 tungsten nitride film
50 : 티타늄 질화막 60 : 텅스텐막50: titanium nitride film 60: tungsten film
70 : 마스크층 80 : 포토레지스트 패턴70 mask layer 80 photoresist pattern
100 : 게이트 전극100: gate electrode
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 필드 산화막이 형성된 반도체 기판 상에 게이트 산화막, 텅스텐 질화막, 티타늄 질화막, 텅스텐막및 마스크층을 순차적으로 형성하고, 마스크층 및 텅스텐막을 제 1 식각으로 선택적으로 식각한다. 그런 다음, 티타늄 질화막을 제 2 식각으로 선택적으로 식각하고, 텅스텐 질화막을 게이트 산화막 및 기판과의 식각선택비가 우수한 개스를 이용한 제 3 식각으로 선택적으로 식각하여 게이트 전극을 형성한다.In order to achieve the above object of the present invention, according to the present invention, a gate oxide film, a tungsten nitride film, a titanium nitride film, a tungsten film and a mask layer are sequentially formed on a semiconductor substrate on which a field oxide film is formed, and a mask layer and a tungsten film are formed. 1 Etch selectively by etching. Then, the titanium nitride film is selectively etched by the second etching, and the tungsten nitride film is selectively etched by the third etching using a gas having an excellent etching selectivity with the gate oxide film and the substrate to form a gate electrode.
또한, 제 1 식각은 SF6개스를 이용하여 건식식각으로 진행하고, 제 2 식각은 Cl2개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행하며, 제 3 식각은 NF3개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행한다.In addition, the first etching proceeds to dry etching using SF 6 gas, the second etching proceeds to dry etching using a mixed gas of Cl 2 gas and O 2 gas, the third etching is NF 3 gas and O Proceed to dry etching using a mixture of two gases.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(10) 상에 소자와 소자를 분리하기 위한 필드 산화막(20)을 형성하고, 필드 산화막(20)이 형성된 기판(10) 상에 게이트 산화막(30)을 형성한다. 그런 다음, 기판 전면에 텅스텐 질화막(WN; 40), 티타늄 질화막(TiN; 50) 및 텅스텐막(60)을 순차적으로 형성하고, 텅스텐막(60) 상부에 산화막 또는 질화막으로 마스크층(70)을 형성한다. 즉, 텅스텐막(60)과 게이트 산화막(30) 사이에 텅스텐 질화막(40) 및 티타늄 질화막(50)을 개재함으로써, 텅스텐막(60)의 형성시 발생되는 게이트 산화막(30)의 결함 및 두께변화가 방지되고 그의 표면 거칠기 특성이 향상된다. 바람직하게, 텅스텐 질화막(40) 및 티타늄 질화막(50)은 각각 100 내지 500Å의 두께로 형성하고, 텅스텐막(60)은 300 내지1,000Å의 두께로 형성한다.Referring to FIG. 1A, a field oxide film 20 for separating an element from an element is formed on a semiconductor substrate 10, and a gate oxide layer 30 is formed on a substrate 10 on which the field oxide film 20 is formed. . Then, a tungsten nitride film (WN) 40, a titanium nitride film (TiN) 50, and a tungsten film 60 are sequentially formed on the entire surface of the substrate, and the mask layer 70 is formed on the tungsten film 60 by an oxide film or a nitride film. Form. That is, by interposing the tungsten nitride film 40 and the titanium nitride film 50 between the tungsten film 60 and the gate oxide film 30, the defect and the thickness change of the gate oxide film 30 generated when the tungsten film 60 is formed. Is prevented and its surface roughness characteristics are improved. Preferably, the tungsten nitride film 40 and the titanium nitride film 50 are each formed to a thickness of 100 to 500 kPa, and the tungsten film 60 is formed to a thickness of 300 to 1,000 kPa.
도 1b를 참조하면, 마스크층(70) 상에 포토리소그라피로 포토레지스트 패턴(80)을 형성하고, 포토레지스트 패턴(80)을 식각 마스크로하여 먼저 제 1 식각으로 마스크층(70) 및 텅스텐막(60)을 선택적으로 식각하여, 티타늄 질화막(50)을 노출시킨다. 바람직하게, 제 1 식각은 텅스텐막(60)과 티타늄 질화막(50) 사이의 높은 식각선택비를 갖는 개스, 더욱 바람직하게 SF6개스를 이용하여 건식식각으로 진행한다.Referring to FIG. 1B, the photoresist pattern 80 is formed by photolithography on the mask layer 70, and the mask layer 70 and the tungsten film are firstly etched using the photoresist pattern 80 as an etch mask. The 60 is selectively etched to expose the titanium nitride film 50. Preferably, the first etching proceeds to dry etching using a gas having a high etching selectivity between the tungsten film 60 and the titanium nitride film 50, more preferably SF 6 gas.
도 1c를 참조하면, 제 2 식각으로 티타늄 질화막(50)을 선택적으로 식각하여 텅스텐 질화막(40)을 노출시킨다. 바람직하게, 제 2 식각은 티타늄 질화막(50)과 텅스텐 질화막(40) 사이의 높은 식각 선택비를 갖는 개스, 더욱 바람직하게 Cl2개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행한다.Referring to FIG. 1C, the titanium nitride film 50 is selectively etched by the second etching to expose the tungsten nitride film 40. Preferably, the second etching proceeds by dry etching using a gas having a high etching selectivity between the titanium nitride film 50 and the tungsten nitride film 40, more preferably a mixed gas of Cl 2 gas and O 2 gas.
도 1d를 참조하면, 제 3 식각으로 텅스텐 질화막(40)을 선택적으로 식각하여, 텅스텐 질화막(40)/티타늄 질화막(50)/텅스텐막(60)의 적층구조로 이루어진 게이트 전극(100)을 형성한다. 바람직하게, 제 3 식각은 텅스텐 질화막(40)과 게이트 산화막(30) 및 기판(10) 사이의 높는 식각 선택비를 갖는 개스, 더욱 바람직하게 NF3개스와 O2개스의 혼합개스를 이용하여 건식식각으로 진행하여, 기판(10)의 리세스 발생을 방지한다.Referring to FIG. 1D, the tungsten nitride film 40 is selectively etched by the third etching to form the gate electrode 100 having a stacked structure of tungsten nitride film 40 / titanium nitride film 50 / tungsten film 60. do. Preferably, the third etching method is dry using a gas having a high etching selectivity between the tungsten nitride film 40, the gate oxide film 30 and the substrate 10, more preferably a mixed gas of NF 3 gas and O 2 gas. The etching proceeds to prevent the recess of the substrate 10.
그리고 나서, 도시되지는 않았지만, 공지된 방법으로 포토레지스트 패턴(80)을 제거한다.Then, although not shown, the photoresist pattern 80 is removed in a known manner.
상기한 본 발명에 의하면, 텅스텐막과 게이트 산화막 사이에 텅스텐 질화막 및 티타늄 질화막을 개재함으로써, 텅스텐막의 형성시 발생되는 게이트 산화막의 결함 및 두께변화가 방지되고 그의 표면 거칠기 특성이 향상된다. 또한, 기판 및 게이트 산화막과의 높은 식각 선택비를 갖는 개스를 이용하여 게이트 전극 형성을 위한 식각을 진행하기 때문에 기판의 리세스가 방지됨으로써 이후 채널영역에서의 동작오류가 방지된다. 결과로서, 소자의 특성 및 신뢰성이 향상된다.According to the present invention described above, by interposing a tungsten nitride film and a titanium nitride film between the tungsten film and the gate oxide film, defects and changes in thickness of the gate oxide film generated during formation of the tungsten film are prevented and surface roughness characteristics thereof are improved. In addition, since etching is performed to form the gate electrode using a gas having a high etching selectivity between the substrate and the gate oxide layer, the recess of the substrate is prevented, thereby preventing an operation error in the channel region. As a result, the characteristics and reliability of the device are improved.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990058396A KR100312655B1 (en) | 1999-12-16 | 1999-12-16 | Method of forming gate electrode for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990058396A KR100312655B1 (en) | 1999-12-16 | 1999-12-16 | Method of forming gate electrode for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010056787A KR20010056787A (en) | 2001-07-04 |
| KR100312655B1 true KR100312655B1 (en) | 2001-11-03 |
Family
ID=19626442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990058396A KR100312655B1 (en) | 1999-12-16 | 1999-12-16 | Method of forming gate electrode for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100312655B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100823712B1 (en) | 2006-07-21 | 2008-04-21 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
-
1999
- 1999-12-16 KR KR1019990058396A patent/KR100312655B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010056787A (en) | 2001-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7256137B2 (en) | Method of forming contact plug on silicide structure | |
| US20060214237A1 (en) | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit | |
| JP2001156170A (en) | Manufacturing method for multilayer interconnection | |
| US20080303141A1 (en) | Method for etching a substrate and a device formed using the method | |
| US5872063A (en) | Self-aligned contact structures using high selectivity etching | |
| KR100451513B1 (en) | Method of manufacture contact hole in semiconduct device | |
| US20080085606A1 (en) | Method for Fabricating a Structure for a Semiconductor Component, and Semiconductor Component | |
| JP2000150641A (en) | Manufacture of semiconductor device | |
| KR100312655B1 (en) | Method of forming gate electrode for semiconductor device | |
| KR100505407B1 (en) | Method of etching hard mask layer in semiconductor device | |
| US20010051386A1 (en) | Method of manufacturing a semiconductor device | |
| US6716760B2 (en) | Method for forming a gate of a high integration semiconductor device including forming an etching prevention or etch stop layer and anti-reflection layer | |
| KR20010045401A (en) | Method of forming for semiconductor device | |
| JPH0697288A (en) | Manufacture of semiconductor device | |
| KR100403350B1 (en) | Method for forming borderless contact hole in a semiconductor device | |
| KR100552806B1 (en) | Fabrication method of thin film capacitor | |
| KR100325599B1 (en) | a manufacturing method of contact holes of semiconductor devices | |
| KR100370783B1 (en) | A method for forming a wordline spacer of semiconductor device | |
| JPH08274078A (en) | Etching | |
| KR100661237B1 (en) | Method of manufacturing semiconductor device | |
| KR100500936B1 (en) | Method for forming contact hole | |
| JPH09321141A (en) | Manufacture of semiconductor device | |
| KR20000040110A (en) | Fabrication method of semiconductor device | |
| JPH1041528A (en) | Manufacture of semiconductor device | |
| US20080090411A1 (en) | Method of manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |