DE69231803T2 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
DE69231803T2
DE69231803T2 DE69231803T DE69231803T DE69231803T2 DE 69231803 T2 DE69231803 T2 DE 69231803T2 DE 69231803 T DE69231803 T DE 69231803T DE 69231803 T DE69231803 T DE 69231803T DE 69231803 T2 DE69231803 T2 DE 69231803T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69231803T
Other languages
English (en)
Other versions
DE69231803D1 (de
Inventor
Shoji Miura
Takayuki Sugisaka
Atsushi Komura
Toshio Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP26504791A external-priority patent/JP2858383B2/ja
Priority claimed from JP3265057A external-priority patent/JP3021850B2/ja
Priority claimed from JP3265046A external-priority patent/JP2812013B2/ja
Application filed by Denso Corp filed Critical Denso Corp
Publication of DE69231803D1 publication Critical patent/DE69231803D1/de
Application granted granted Critical
Publication of DE69231803T2 publication Critical patent/DE69231803T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
DE69231803T 1991-10-14 1992-10-12 Verfahren zur Herstellung einer Halbleiteranordnung Expired - Lifetime DE69231803T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP26504791A JP2858383B2 (ja) 1991-10-14 1991-10-14 半導体装置の製造方法
JP3265057A JP3021850B2 (ja) 1991-10-14 1991-10-14 半導体装置の製造方法
JP3265046A JP2812013B2 (ja) 1991-10-14 1991-10-14 半導体装置の製造方法
PCT/JP1992/001326 WO1993008596A1 (en) 1991-10-14 1992-10-12 Method for fabrication of semiconductor device

Publications (2)

Publication Number Publication Date
DE69231803D1 DE69231803D1 (de) 2001-05-31
DE69231803T2 true DE69231803T2 (de) 2001-12-06

Family

ID=27335347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231803T Expired - Lifetime DE69231803T2 (de) 1991-10-14 1992-10-12 Verfahren zur Herstellung einer Halbleiteranordnung

Country Status (4)

Country Link
US (1) US5480832A (de)
EP (1) EP0562127B1 (de)
DE (1) DE69231803T2 (de)
WO (1) WO1993008596A1 (de)

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KR0162510B1 (ko) * 1993-07-12 1999-02-01 가네꼬 히사시 반도체 장치 및 그 제조방법
JP2773611B2 (ja) * 1993-11-17 1998-07-09 株式会社デンソー 絶縁物分離半導体装置
JP3033412B2 (ja) * 1993-11-26 2000-04-17 株式会社デンソー 半導体装置の製造方法
DE4341171C2 (de) * 1993-12-02 1997-04-17 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung
US5753529A (en) * 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
JPH07326659A (ja) 1994-06-02 1995-12-12 Hitachi Ltd 半導体集積回路装置の製造方法
US5691248A (en) * 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges
KR0161432B1 (ko) * 1995-09-13 1999-02-01 김광호 소자분리 영역의 면적을 감소시키기 위한 트랜지스터 제조방법
KR970052023A (ko) * 1995-12-30 1997-07-29 김주용 에스 오 아이 소자 및 그의 제조방법
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US6291315B1 (en) * 1996-07-11 2001-09-18 Denso Corporation Method for etching trench in manufacturing semiconductor devices
US5811315A (en) * 1997-03-13 1998-09-22 National Semiconductor Corporation Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure
US6013558A (en) * 1997-08-06 2000-01-11 Vlsi Technology, Inc. Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch
US6333274B2 (en) * 1998-03-31 2001-12-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a seamless shallow trench isolation step
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
KR100318467B1 (ko) * 1998-06-30 2002-02-19 박종섭 본딩형실리콘이중막웨이퍼제조방법
KR20000015663A (ko) 1998-08-31 2000-03-15 김영환 반도체 소자의 격리막 형성방법
US6353246B1 (en) 1998-11-23 2002-03-05 International Business Machines Corporation Semiconductor device including dislocation in merged SOI/DRAM chips
JP3546789B2 (ja) 1999-12-24 2004-07-28 株式会社デンソー 半導体装置の製造方法
FR2807568A1 (fr) * 2000-04-10 2001-10-12 St Microelectronics Sa Procede de formation de couches enterrees
US6486043B1 (en) 2000-08-31 2002-11-26 International Business Machines Corporation Method of forming dislocation filter in merged SOI and non-SOI chips
US6797591B1 (en) * 2000-09-14 2004-09-28 Analog Devices, Inc. Method for forming a semiconductor device and a semiconductor device formed by the method
EP1220312A1 (de) * 2000-12-29 2002-07-03 STMicroelectronics S.r.l. Verfahren zur Integration eines Halbleiterbauelements auf einem SOI Substrat mit mindestens einer dielektrisch isolierten Wanne
GB2372631B (en) * 2001-02-22 2005-08-03 Mitel Semiconductor Ltd Semiconductor-on-insulator structure
JP4852792B2 (ja) * 2001-03-30 2012-01-11 株式会社デンソー 半導体装置の製造方法
JP2003017704A (ja) 2001-06-29 2003-01-17 Denso Corp 半導体装置
JP4157718B2 (ja) * 2002-04-22 2008-10-01 キヤノンアネルバ株式会社 窒化シリコン膜作製方法及び窒化シリコン膜作製装置
US7358164B2 (en) * 2005-06-16 2008-04-15 International Business Machines Corporation Crystal imprinting methods for fabricating substrates with thin active silicon layers
US7488647B1 (en) 2005-08-11 2009-02-10 National Semiconductor Corporation System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device
US7399686B2 (en) * 2005-09-01 2008-07-15 International Business Machines Corporation Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate
JP2007317954A (ja) * 2006-05-26 2007-12-06 Nec Electronics Corp 半導体装置及びその製造方法
US20100117188A1 (en) * 2007-03-05 2010-05-13 General Electric Company Method for producing trench isolation in silicon carbide and gallium nitride and articles made thereby
US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
US8049297B2 (en) * 2007-12-11 2011-11-01 Hvvi Semiconductors, Inc. Semiconductor structure
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US10707330B2 (en) * 2018-02-15 2020-07-07 Globalfoundries Inc. Semiconductor device with interconnect to source/drain
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Also Published As

Publication number Publication date
EP0562127B1 (de) 2001-04-25
EP0562127A1 (de) 1993-09-29
DE69231803D1 (de) 2001-05-31
EP0562127A4 (en) 1994-11-23
US5480832A (en) 1996-01-02
WO1993008596A1 (en) 1993-04-29

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