DE69326908T2 - Verfahren zur Herstellung einer Halbleiter-Anordnung - Google Patents

Verfahren zur Herstellung einer Halbleiter-Anordnung

Info

Publication number
DE69326908T2
DE69326908T2 DE69326908T DE69326908T DE69326908T2 DE 69326908 T2 DE69326908 T2 DE 69326908T2 DE 69326908 T DE69326908 T DE 69326908T DE 69326908 T DE69326908 T DE 69326908T DE 69326908 T2 DE69326908 T2 DE 69326908T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69326908T
Other languages
English (en)
Other versions
DE69326908D1 (de
Inventor
Junzoh Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69326908D1 publication Critical patent/DE69326908D1/de
Application granted granted Critical
Publication of DE69326908T2 publication Critical patent/DE69326908T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
DE69326908T 1992-03-09 1993-03-09 Verfahren zur Herstellung einer Halbleiter-Anordnung Expired - Fee Related DE69326908T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4050218A JP2910382B2 (ja) 1992-03-09 1992-03-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69326908D1 DE69326908D1 (de) 1999-12-09
DE69326908T2 true DE69326908T2 (de) 2000-02-17

Family

ID=12852924

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326908T Expired - Fee Related DE69326908T2 (de) 1992-03-09 1993-03-09 Verfahren zur Herstellung einer Halbleiter-Anordnung

Country Status (4)

Country Link
US (1) US5593906A (de)
EP (2) EP0793265A3 (de)
JP (1) JP2910382B2 (de)
DE (1) DE69326908T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665203A (en) * 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
US5943579A (en) * 1997-02-14 1999-08-24 Micron Technology, Inc. Method for forming a diffusion region in a semiconductor device
US6309975B1 (en) 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
TW383427B (en) * 1998-04-03 2000-03-01 United Microelectronics Corp Method for etching tantalum oxide
GB2337361B (en) * 1998-05-06 2000-03-29 United Microelectronics Corp Method of etching tantalum oxide layer
US6197629B1 (en) * 1998-11-19 2001-03-06 United Microelectronics Corp. Method of fabricating a polysilicon-based load circuit for static random-access memory
JP3543968B1 (ja) 2003-01-31 2004-07-21 沖電気工業株式会社 半導体装置の製造方法
KR100800910B1 (ko) * 2006-12-28 2008-02-04 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
JP2010141079A (ja) * 2008-12-11 2010-06-24 Hitachi Kokusai Electric Inc 半導体装置の製造方法
JP5573306B2 (ja) * 2010-03-31 2014-08-20 凸版印刷株式会社 フォトマスクブランクの製造方法
JP5615311B2 (ja) * 2012-03-16 2014-10-29 株式会社東芝 テンプレートの製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
DE3315719A1 (de) * 1983-04-29 1984-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen
US4561907A (en) * 1984-07-12 1985-12-31 Bruha Raicu Process for forming low sheet resistance polysilicon having anisotropic etch characteristics
JPH01291446A (ja) * 1988-05-19 1989-11-24 Seiko Instr Inc 半導体装置の製造方法
JPH0812865B2 (ja) * 1989-06-06 1996-02-07 株式会社東芝 バイポーラトランジスタとその製造方法
US5126231A (en) * 1990-02-26 1992-06-30 Applied Materials, Inc. Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch
US5279990A (en) * 1990-03-02 1994-01-18 Motorola, Inc. Method of making a small geometry contact using sidewall spacers

Also Published As

Publication number Publication date
DE69326908D1 (de) 1999-12-09
EP0793265A2 (de) 1997-09-03
JPH05251407A (ja) 1993-09-28
JP2910382B2 (ja) 1999-06-23
EP0793265A3 (de) 1998-06-17
US5593906A (en) 1997-01-14
EP0560575B1 (de) 1999-11-03
EP0560575A1 (de) 1993-09-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee