DE69023558D1 - Verfahren zur Herstellung einer Halbleitervorrichtung. - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung.

Info

Publication number
DE69023558D1
DE69023558D1 DE69023558T DE69023558T DE69023558D1 DE 69023558 D1 DE69023558 D1 DE 69023558D1 DE 69023558 T DE69023558 T DE 69023558T DE 69023558 T DE69023558 T DE 69023558T DE 69023558 D1 DE69023558 D1 DE 69023558D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023558T
Other languages
English (en)
Other versions
DE69023558T2 (de
Inventor
Hitoshi Tsuji
Hiroshi Haraguchi
Osamu Hirata
Hidetsuna Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1169052A external-priority patent/JP2740008B2/ja
Priority claimed from JP1169053A external-priority patent/JP2778996B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69023558D1 publication Critical patent/DE69023558D1/de
Application granted granted Critical
Publication of DE69023558T2 publication Critical patent/DE69023558T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/137—Resists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
DE69023558T 1989-06-30 1990-06-29 Verfahren zur Herstellung einer Halbleitervorrichtung. Expired - Fee Related DE69023558T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1169052A JP2740008B2 (ja) 1989-06-30 1989-06-30 半導体素子用開口部の形成方法
JP1169053A JP2778996B2 (ja) 1989-06-30 1989-06-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69023558D1 true DE69023558D1 (de) 1995-12-21
DE69023558T2 DE69023558T2 (de) 1996-05-02

Family

ID=26492525

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023558T Expired - Fee Related DE69023558T2 (de) 1989-06-30 1990-06-29 Verfahren zur Herstellung einer Halbleitervorrichtung.

Country Status (4)

Country Link
US (1) US4985374A (de)
EP (1) EP0405585B1 (de)
KR (1) KR930010976B1 (de)
DE (1) DE69023558T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185812A (en) * 1990-02-14 1993-02-09 Kabushiki Kaisha Toshiba Optical pattern inspection system
JP2831847B2 (ja) * 1990-11-29 1998-12-02 株式会社東芝 半導体装置の製造方法
EP0489542B1 (de) * 1990-12-05 1998-10-21 AT&T Corp. Lithographische Verfahren
US5244759A (en) * 1991-02-27 1993-09-14 At&T Bell Laboratories Single-alignment-level lithographic technique for achieving self-aligned features
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
US5269880A (en) * 1992-04-03 1993-12-14 Northern Telecom Limited Tapering sidewalls of via holes
JP2565119B2 (ja) * 1993-11-30 1996-12-18 日本電気株式会社 パターン形成方法
JPH07254605A (ja) * 1994-03-16 1995-10-03 Toshiba Corp 配線形成方法
US5589423A (en) * 1994-10-03 1996-12-31 Motorola Inc. Process for fabricating a non-silicided region in an integrated circuit
US5652084A (en) * 1994-12-22 1997-07-29 Cypress Semiconductor Corporation Method for reduced pitch lithography
US5741624A (en) 1996-02-13 1998-04-21 Micron Technology, Inc. Method for reducing photolithographic steps in a semiconductor interconnect process
KR0184158B1 (ko) * 1996-07-13 1999-04-15 문정환 반도체장치의 자기 정합정 금속 배선 형성 방법
US5854140A (en) * 1996-12-13 1998-12-29 Siemens Aktiengesellschaft Method of making an aluminum contact
US6475704B1 (en) * 1997-09-12 2002-11-05 Canon Kabushiki Kaisha Method for forming fine structure
JP3193335B2 (ja) * 1997-12-12 2001-07-30 松下電器産業株式会社 半導体装置の製造方法
US6025276A (en) * 1998-09-03 2000-02-15 Micron Technology, Inc. Semiconductor processing methods of forming substrate features, including contact openings
JP2000098116A (ja) * 1998-09-18 2000-04-07 Canon Inc 素子又は素子作製用モールド型の作製方法
US6617098B1 (en) * 1999-07-13 2003-09-09 Input/Output, Inc. Merged-mask micro-machining process
US6653244B2 (en) * 2001-09-19 2003-11-25 Binoptics Corporation Monolithic three-dimensional structures
US6790743B1 (en) * 2003-08-07 2004-09-14 Macronix International Co., Ltd. [Method to relax alignment accuracy requirement in fabrication for integrated circuit]
ITTO20030730A1 (it) 2003-09-23 2005-03-24 Infm Istituto Naz Per La Fisi Ca Della Mater Procedimento per la fabbricazione di strutture tridimensionali complesse su scala sub-micrometrica mediante litografia combinata di due resist.
US7144797B2 (en) * 2004-09-24 2006-12-05 Rensselaer Polytechnic Institute Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same
KR100739964B1 (ko) * 2005-04-22 2007-07-16 주식회사 하이닉스반도체 반도체 소자의 제조방법
WO2015137226A1 (ja) * 2014-03-14 2015-09-17 株式会社村田製作所 積層コイル素子およびその製造方法
CN105762118A (zh) * 2014-12-16 2016-07-13 旺宏电子股份有限公司 半导体元件及其制造方法
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
CN111819497B (zh) 2018-03-06 2024-02-27 应用材料公司 构建3d功能性光学材料堆叠结构的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562654A (en) * 1979-06-21 1981-01-12 Nec Corp Semiconductor device
JPS5626450A (en) * 1979-08-13 1981-03-14 Hitachi Ltd Manufacture of semiconductor device
US4568631A (en) * 1984-04-30 1986-02-04 International Business Machines Corporation Process for delineating photoresist lines at pattern edges only using image reversal composition with diazoquinone
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
GB2171530B (en) * 1985-02-27 1989-06-28 Imtec Products Inc Method of producing reversed photoresist images by vapour diffusion
US4737468A (en) * 1987-04-13 1988-04-12 Motorola Inc. Process for developing implanted buried layer and/or key locators
US4775609A (en) * 1987-05-18 1988-10-04 Hoescht Celanese Corporation Image reversal
US4842991A (en) * 1987-07-31 1989-06-27 Texas Instruments Incorporated Self-aligned nonnested sloped via
JPS6484722A (en) * 1987-09-28 1989-03-30 Nec Corp Manufacture of semiconductor device
US4885231A (en) * 1988-05-06 1989-12-05 Bell Communications Research, Inc. Phase-shifted gratings by selective image reversal of photoresist
JPH0253918A (ja) * 1988-08-18 1990-02-22 Murata Mach Ltd 空気式紡績装置

Also Published As

Publication number Publication date
EP0405585A2 (de) 1991-01-02
EP0405585A3 (en) 1991-05-29
KR930010976B1 (ko) 1993-11-18
DE69023558T2 (de) 1996-05-02
EP0405585B1 (de) 1995-11-15
KR910001966A (ko) 1991-01-31
US4985374A (en) 1991-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee