DE3789567T2 - Verfahren zur Herstellung eines Halbleiterbauelementes. - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelementes.

Info

Publication number
DE3789567T2
DE3789567T2 DE3789567T DE3789567T DE3789567T2 DE 3789567 T2 DE3789567 T2 DE 3789567T2 DE 3789567 T DE3789567 T DE 3789567T DE 3789567 T DE3789567 T DE 3789567T DE 3789567 T2 DE3789567 T2 DE 3789567T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3789567T
Other languages
English (en)
Other versions
DE3789567D1 (de
Inventor
Takao C O Patent Division Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3789567D1 publication Critical patent/DE3789567D1/de
Publication of DE3789567T2 publication Critical patent/DE3789567T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE3789567T 1986-03-07 1987-02-19 Verfahren zur Herstellung eines Halbleiterbauelementes. Expired - Fee Related DE3789567T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61049910A JPS62208670A (ja) 1986-03-07 1986-03-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3789567D1 DE3789567D1 (de) 1994-05-19
DE3789567T2 true DE3789567T2 (de) 1994-08-25

Family

ID=12844165

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3789567T Expired - Fee Related DE3789567T2 (de) 1986-03-07 1987-02-19 Verfahren zur Herstellung eines Halbleiterbauelementes.

Country Status (4)

Country Link
EP (1) EP0236811B1 (de)
JP (1) JPS62208670A (de)
KR (1) KR900003616B1 (de)
DE (1) DE3789567T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2800515B1 (fr) * 1999-11-03 2002-03-29 St Microelectronics Sa Procede de fabrication de composants de puissance verticaux
EP1630863B1 (de) * 2004-08-31 2014-05-14 Infineon Technologies AG Verfahren zur Herstellung eines monolithisch integrierten vertikalen Halbleiterbauteils in einem SOI-Substrat
CN102088029B (zh) * 2009-12-08 2012-10-03 上海华虹Nec电子有限公司 SiGe BiCMOS工艺中的PNP双极晶体管

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357622A (en) * 1980-01-18 1982-11-02 International Business Machines Corporation Complementary transistor structure
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
JPS5961045A (ja) * 1982-09-29 1984-04-07 Fujitsu Ltd 半導体装置の製造方法
JPS59186367A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6098659A (ja) * 1983-11-02 1985-06-01 Hitachi Ltd 直列接続トランジスタを有する半導体集積回路
JPS60164336A (ja) * 1984-02-06 1985-08-27 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
KR900003616B1 (ko) 1990-05-26
EP0236811A3 (en) 1990-03-14
KR870009456A (ko) 1987-10-26
EP0236811B1 (de) 1994-04-13
EP0236811A2 (de) 1987-09-16
JPS62208670A (ja) 1987-09-12
DE3789567D1 (de) 1994-05-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee