DE3853778D1 - Verfahren zur Herstellung eines Halbleiterbauelements. - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements.

Info

Publication number
DE3853778D1
DE3853778D1 DE3853778T DE3853778T DE3853778D1 DE 3853778 D1 DE3853778 D1 DE 3853778D1 DE 3853778 T DE3853778 T DE 3853778T DE 3853778 T DE3853778 T DE 3853778T DE 3853778 D1 DE3853778 D1 DE 3853778D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3853778T
Other languages
English (en)
Other versions
DE3853778T2 (de
Inventor
Masana C O Mitsubishi D Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE3853778D1 publication Critical patent/DE3853778D1/de
Publication of DE3853778T2 publication Critical patent/DE3853778T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
DE3853778T 1988-06-08 1988-10-11 Verfahren zur Herstellung eines Halbleiterbauelements. Expired - Lifetime DE3853778T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63141008A JPH0783118B2 (ja) 1988-06-08 1988-06-08 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE3853778D1 true DE3853778D1 (de) 1995-06-14
DE3853778T2 DE3853778T2 (de) 1995-10-12

Family

ID=15282043

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853778T Expired - Lifetime DE3853778T2 (de) 1988-06-08 1988-10-11 Verfahren zur Herstellung eines Halbleiterbauelements.

Country Status (3)

Country Link
EP (1) EP0345380B1 (de)
JP (1) JPH0783118B2 (de)
DE (1) DE3853778T2 (de)

Families Citing this family (51)

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Publication number Priority date Publication date Assignee Title
JP2573736B2 (ja) * 1990-09-18 1997-01-22 三菱電機株式会社 高耐圧低抵抗半導体装置及びその製造方法
US5168331A (en) * 1991-01-31 1992-12-01 Siliconix Incorporated Power metal-oxide-semiconductor field effect transistor
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
DE69223128T2 (de) * 1991-07-26 1998-07-09 Denso Corp Verfahren zur herstellung vertikaler mosfets
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US5227653A (en) * 1991-08-07 1993-07-13 North American Philips Corp. Lateral trench-gate bipolar transistors
EP1209751A3 (de) * 1991-08-08 2002-07-31 Kabushiki Kaisha Toshiba Selbsabschaltende Leistungshalbleiteranordnung mit isoliertem Gate mit Transistoranordnung mit verbesserter Injektion
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5910669A (en) * 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US5316959A (en) * 1992-08-12 1994-05-31 Siliconix, Incorporated Trenched DMOS transistor fabrication using six masks
GB9306895D0 (en) * 1993-04-01 1993-05-26 Philips Electronics Uk Ltd A method of manufacturing a semiconductor device comprising an insulated gate field effect device
JP3334290B2 (ja) * 1993-11-12 2002-10-15 株式会社デンソー 半導体装置
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
DE69525003T2 (de) * 1994-08-15 2003-10-09 Siliconix Inc Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken
JP3307785B2 (ja) * 1994-12-13 2002-07-24 三菱電機株式会社 絶縁ゲート型半導体装置
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
GB2314206A (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Ltd Preventing voltage breakdown in semiconductor devices
JPH1098188A (ja) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The 絶縁ゲート半導体装置
WO1998026458A1 (fr) * 1996-12-11 1998-06-18 The Kansai Electric Power Co., Inc. Semi-conducteur a grille isolee
US6180958B1 (en) 1997-02-07 2001-01-30 James Albert Cooper, Jr. Structure for increasing the maximum voltage of silicon carbide power transistors
US6570185B1 (en) 1997-02-07 2003-05-27 Purdue Research Foundation Structure to reduce the on-resistance of power transistors
ES2236887T3 (es) * 1997-02-07 2005-07-16 James Albert Cooper, Jr. Estructura para aumentar la tension maxima de transistores de potencia de carburo de silicio.
US5923979A (en) * 1997-09-03 1999-07-13 Siliconix Incorporated Planar DMOS transistor fabricated by a three mask process
JP4363736B2 (ja) * 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
DE10038177A1 (de) * 2000-08-04 2002-02-21 Infineon Technologies Ag Mittels Feldeffekt steuerbares Halbleiterschaltelement mit zwei Steuerelektroden
JP4934903B2 (ja) * 2001-04-26 2012-05-23 株式会社デンソー 炭化珪素半導体装置及びその製造方法
US6537921B2 (en) * 2001-05-23 2003-03-25 Vram Technologies, Llc Vertical metal oxide silicon field effect semiconductor diodes
JP4865166B2 (ja) * 2001-08-30 2012-02-01 新電元工業株式会社 トランジスタの製造方法、ダイオードの製造方法
WO2005036650A2 (en) 2003-10-08 2005-04-21 Toyota Jidosha Kabushiki Kaisha Insulated gate type semiconductor device and manufacturing method thereof
JP4500530B2 (ja) * 2003-11-05 2010-07-14 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
JP4453671B2 (ja) * 2006-03-08 2010-04-21 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
JP4450241B2 (ja) 2007-03-20 2010-04-14 株式会社デンソー 炭化珪素半導体装置の製造方法
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
JP2009206268A (ja) 2008-02-27 2009-09-10 Seiko Instruments Inc 半導体装置及びその製造方法
CN103107193A (zh) * 2011-11-11 2013-05-15 上海华虹Nec电子有限公司 一种沟槽型绝缘栅场效应管
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
CN104106142B (zh) 2012-02-10 2016-03-09 松下知识产权经营株式会社 半导体装置及其制造方法
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
DE112013006638T5 (de) * 2013-02-25 2015-10-29 Hitachi, Ltd. Halbleitervorrichtung, Treibervorrichtung für eine Halbleiterschaltung und Leistungswandlungsvorrichtung
US9349856B2 (en) 2013-03-26 2016-05-24 Toyoda Gosei Co., Ltd. Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof
WO2014171048A1 (ja) 2013-04-16 2014-10-23 パナソニック株式会社 炭化珪素半導体装置およびその製造方法
JP6197995B2 (ja) * 2013-08-23 2017-09-20 富士電機株式会社 ワイドバンドギャップ絶縁ゲート型半導体装置
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
JP2016025177A (ja) * 2014-07-18 2016-02-08 トヨタ自動車株式会社 スイッチング素子
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
TWI663725B (zh) 2017-04-26 2019-06-21 國立清華大學 溝槽式閘極功率金氧半場效電晶體之結構
CN107478320B (zh) 2017-08-23 2019-11-05 京东方科技集团股份有限公司 晶体管声传感元件及其制备方法、声传感器和便携设备
CN113053747B (zh) * 2019-12-26 2022-09-09 株洲中车时代半导体有限公司 改善SiC晶圆翘曲的方法及SiC半导体器件的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583287A (ja) * 1981-06-30 1983-01-10 Fujitsu Ltd 縦型シリンドリカルｍｏｓ電界効果トランジスタ
EP0159663A3 (de) * 1984-04-26 1987-09-23 General Electric Company Thyristoren, Feldeffekttransistoren mit isoliertem Gate und MOSFETs hoher Dichte gesteuert durch eine in einer V-Nut angebrachte MOS-Struktur und Verfahren zur Herstellung
JPS61142775A (ja) * 1984-12-15 1986-06-30 Matsushita Electric Works Ltd Ｍｏｓトランジスタ
JPS63288057A (ja) * 1987-05-20 1988-11-25 Sanyo Electric Co Ltd Ｃｍｏｓ半導体装置

Also Published As

Publication number Publication date
DE3853778T2 (de) 1995-10-12
EP0345380A3 (en) 1990-07-11
JPH0783118B2 (ja) 1995-09-06
JPH01310576A (ja) 1989-12-14
EP0345380A2 (de) 1989-12-13
EP0345380B1 (de) 1995-05-10

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