TWI663725B - 溝槽式閘極功率金氧半場效電晶體之結構 - Google Patents

溝槽式閘極功率金氧半場效電晶體之結構 Download PDF

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TWI663725B
TWI663725B TW106113870A TW106113870A TWI663725B TW I663725 B TWI663725 B TW I663725B TW 106113870 A TW106113870 A TW 106113870A TW 106113870 A TW106113870 A TW 106113870A TW I663725 B TWI663725 B TW I663725B
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TW201839982A (zh
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黃智方
江政毅
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國立清華大學
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Abstract

本發明提供一種溝槽式閘極功率金氧半場效電晶體之結構(UMOSFET)之結構，結構包含：一金屬層分別設置於結構之一上表面與一底面，以分別形成一源極與一汲極，以做為結構與外界連結之電極；一N型半導體基板，設置於汲極上；一N型漂移區(N-drift region)，設置於N型半導體基板上；一N型電流分散層(N-current spread layer,N-CSL)，設置於N型漂移區上；一P型井(P-well)，設置於電流分散層上；一N型半導體層，設置於P型井上；一第一P型半導體層，相鄰於N型半導體層並設置於P型井上；一溝槽延伸通過N型半導體層、P型井以及N型電流分散層，溝槽之底部終止於N型漂移區；一絕緣層設置於溝槽內；一分離閘極(split gate)設置於溝槽之絕緣層中並被該絕緣層所包覆；一閘極設置於溝槽之絕緣層中且在分離閘極之上；以及一半導體保護層，設置於溝槽之底部以下，並相鄰於N型漂移區，且絕緣層設置於半導體保護層之上，用以在結構關斷偏壓時，保護絕緣層被電場所擊穿；其中，閘極與分離閘極係被絕緣層所區隔出一預設間距；以及，閘極之底部深度位置係深於 該P型井與該N型電流分散層之交界面。

Description

溝槽式閘極功率金氧半場效電晶體之結構
本發明係關於一種溝槽式閘極功率金氧半場效電晶體(U-metal-oxide-semiconductor field-effect transistor以下簡稱：UMOSFET)。
碳化矽(silicon carbide,SiC)由矽和碳原子的交替平面的六方晶格之結晶組成，具有比矽較寬的能帶和高得多的擊穿電場(critical electric field)，故碳化矽元件的崩潰電壓(breakdown voltage)比矽元件好得多。此外，一般碳化矽同時具有較低的電洞濃度以及較短的少數載子生命週期(minority carrier lifetimes)，而較短的少數載子生命週期允許碳化矽中的雙極裝置(bipolar devices)比可比矽更快地切換，然而不能有效改善碳化矽雙極晶體管的導通電阻，同時操作上需要驅動電流是其缺點。相較之下碳化矽金氧半場效電晶體具有電壓驅動且高頻操作的優點。
請參考第1圖，第1圖顯示習知技術UMOSFET結構100示意圖，結構100包含金屬層101S與101D、N型半導體基板102、N型漂移區(N-drift region)103、P型井(P-well)105、N型半導體層106、P型半導體層107、溝槽T、絕緣層I、閘極109。由於習知技術1的結構100設計缺陷，擊穿電場會在結構100之轉角B產生，故轉角B(如圓形虛線處所示)之絕緣層I在關斷偏壓狀態(off-state)時容易被擊穿電場所破壞；除此之外，第1圖之結構100之閘極/汲極電容Cgd如粗體虛線範圍所示。
請參考第2圖，第2圖顯示習知技術2之UMOSFET結構200示意圖，結構200包含金屬層201S與201D、N型半導體基板202、N型漂移區203、N型電流分散層(N-current spread layer,N-CSL)204、P型井205、N型半導體層206、P型半導體層207、溝槽T、絕緣層I、閘極209、半導體保護層210。雖然結構200利用半導體保護層210來改善第1圖之轉角B在關斷偏壓時容易被擊穿電場所破壞的缺點，但結構200由於閘極端與汲極端之電容值較大，故在切換順向導通(conducting)與阻絕關斷(blocking)狀態時，需要較多的時間進行充放電；再者，其閘極/汲極電容Cgd如粗體虛線範圍所示，其範圍在閘極209深入N型電流分散層204之部份。
本發明之目的之一，是在提供一種UMOSFET結構具有半導體保護層，係可用以保護UMOSFET結構免於被擊穿電場所破壞。
本發明之目的之是在提供一種UMOSFET結構 具有電流分散層，可降低UMOSFET結構之電阻值。
本發明之目的之一，是在提供一種UMOSFET結構具有閘極與分離閘極，用以減少UMOSFET結構之電容值，使元件在阻絕關斷與順向導通狀態之間可以快速切換。
本發明提供一種UMOSFET之結構，結構包含：一金屬層分別設置於結構之一上表面與一底面，以分別形成一源極與一汲極，以做為結構與外界連結之電極；一N型半導體基板，設置於汲極上；一N型漂移區(N-drift region)，設置於N型半導體基板上；一N型電流分散層(N-current spread layer,N-CSL)，設置於N型漂移區上；一P型井(P-well)，設置於電流分散層上；一N型半導體層，設置於P型井上；一第一P型半導體層，相鄰於N型半導體層並設置於P型井上；一溝槽延伸通過N型半導體層、P型井以及N型電流分散層，溝槽之底部終止於N型漂移區；一絕緣層設置於溝槽內；一分離閘極(split gate)設置於溝槽之絕緣層中並被該絕緣層所包覆；一閘極設置於溝槽之絕緣層中且在分離閘極之上；以及一半導體保護層，設置於溝槽之底部以下，並相鄰於N型漂移區，且絕緣層設置於半導體保護層之上，用以在結構關斷偏壓時，保護絕緣層避免被電場所擊穿；其中，閘極與分離閘極係被絕緣層所區隔出一預設間距；以及，閘極之底部深度位置係深於該P型井與該N型電流分散層之交界面。
100、200、300A、300B‧‧‧結構
101S、101D、201S、201D、301S、301D‧‧‧金屬層
102、202、302‧‧‧N型半導體基板
103、203、303‧‧‧N型漂移區
204、304‧‧‧N型電流分散層
105、205、305‧‧‧P型井
106、206、306‧‧‧N型半導體層
107、207、307‧‧‧P型半導體層
308‧‧‧分離閘極
109、209、309‧‧‧閘極
210、310‧‧‧半導體保護層
T‧‧‧溝槽
I‧‧‧絕緣層
D‧‧‧汲極
x‧‧‧軸
d‧‧‧預設間距
B‧‧‧轉角
第1圖顯示習知技術1之UMOSFET結構100示意圖。
第3圖顯示習知技術2之UMOSFET結構200示意圖。
第3A圖顯示本發明UMOSFET結構一實施例之側剖面示意圖。
第3B圖顯示本發明UMOSFET結構一實施例之側剖面示意圖。
第3C圖顯示本發明一實施例之結構開啟切換特性圖。
第3D圖顯示本發明一實施例之結構關閉切換特性圖。
第4圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之導通偏壓時之電壓電流圖比較圖。
第5圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之關斷偏壓時之電壓電流圖比較圖
接著請同時參考第6圖，第6圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之閘極與汲極之間電容值比較圖。
第7圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之絕緣層電場比較圖。
請參閱第3A圖，第3A圖顯示本發明UMOSFET結構一實施例之側剖面示意圖，結構300在一實施例中為使用於碳化矽的UMOSFET之結構。
結構300A包含：金屬層301S與301D、N型半導體基板302、N型漂移區(N-drift region)303、N型電流分散層(N-current spread layer,N-CSL)304、P型井(P-well)305、N型半導體層306、P型半導體層307、溝槽T、絕緣層I、分離閘極(split gate)308、閘極309、半導體保護層310。
金屬層301S與301D分別設置於結構300之上表面與底面分別形成一源極與一汲極，以做為結構300與外界連結之電極；N型半導體基板302設置於汲極D上；N型漂移區303設置於N型半導體基板302上；N型電流分散層304設置於N型漂移區303上；P型井305設置於N型電流分散層304上；一N型半導體層306設置於P型井305上；P型半導體層307相鄰於N型半導體層306並設置於P型井305上；溝槽T向下延伸通過N型半導體層306、P型井305、以及N型電流分散層304，最終溝槽T之底部終止於N型漂移區303。
請注意，在本實施例中，溝槽T之底部以下係離子佈值形成半導體保護層310，且半導體保護層310相鄰於N型漂移區303，在本實施例中，分離閘極308之底面係接觸半導體保護層310上緣，半導體保護層310用以在結構300關斷偏壓時，保護絕緣層I避免被擊穿電場所破壞。另外，半導體保護層310 與分離閘極308係接地，避免半導體保護層310與分離閘極308漏電流產生。
請注意，半導體保護層310在一實施例中為一P型半導體層，半導體保護層310與分離閘極308係接地，由於半導體保護層310與分離閘極308等電位可避免半導體保護層310與分離閘極308漏電流產生。
半導體保護層310用以在結構300關斷偏壓時，保護絕緣層I避免被擊穿電場所破壞。絕緣層I設置於溝槽T之內，且分別相鄰於N型半導體層306、P型井305、N型電流分散層304、N型漂移區303、以及半導體保護層310。分離閘極308設置於溝槽之絕緣層I中，以及閘極309設置於溝槽T之絕緣層中且在分離閘極308之上；其中，閘極309與分離閘極308係被絕緣層I所區隔出一預設間距d；以及，閘極309之底部深度位置係深於P型井305與N型電流分散層304之交界面。在一實施例中，閘極309與分離閘極308可視為被絕緣層I所包覆。其中，絕緣層I為一半導體氧化物或半導體氮化物，分離閘極308與閘極309為一多晶矽(poly-Si)所實現。
接著請參閱第3B圖，第3B圖顯示本發明UMOSFET結構一實施例之側剖面示意圖，結構300B在一實施例中為使用於碳化矽的UMOSFET之結構。
同前所述，結構300B與300A之差異在於，絕緣層I設置於半導體保護層310之上，分離閘極308之底面係與該 半導體保護層310之間具有絕緣層I，意即，分離閘極308之底面係不接觸半導體保護層310上緣。
在本實施例中，N型半導體基板302、N型漂移區303、N型電流分散層304與N型半導體層306中摻雜之一N型半導體且濃度大小為：N型漂移區303<N型電流分散層304；由於，結構300在關斷偏壓時，會在N型漂移區303與N型電流分散層304產生空乏區(Depletion region)，除此之外N型漂移區303為耐高壓元件，故N型漂移區303之N型半導體濃度為最低。
當結構300處於導通偏壓時，此時源極S接地，汲極D接正電壓，閘極309也接正電壓，電子流由N型半導體層306流向汲極D，並透過N型電流分散層304使電流均勻分散，換言之，N型電流分散層304使電流流量增加，並降低結構300的電阻值。
在此請注意，煩請同時參考第3C圖與第3D圖，第3C圖顯示本實施例之結構開啟切換特性圖，第3D圖顯示本實施例之結構關閉切換特性圖。由圖可以了解，除了閘極309與分離閘極308之間的電容值小於閘極309與N型電流分散層304之間的電容值；本結構300之電容值較習知技術比較，其電容值僅有閘極309超過P型井305與N型電流分散層304之部份，故結構300利用絕緣層I區隔閘極309與分離閘極308之方式，使結構300使用之電容值遠小於習知技術。如此一來，結構300 在順向導通與阻絕關斷切換時，其電容充電或放電速度會比習知技術來得快，此部份在第3C圖與第3D圖可以證明本發明之結構充放電速度均優於習知技術。
再者，由於分離閘極308為金屬層因接地隔絕閘極309與分離閘極308之間的閘極/汲極電容Cgd產生，故本發明的閘極/汲極電容Cgd僅有虛框處，遠小於先前技術。又因習知技術2之結構200之閘極209深入N型電流分散層204之深度大於結構300B，故其結構200之閘極/汲極電容Cgd遠大於結構300B。
閘極309與P型井305之間距離(如虛框處)小於預設間距d，預設間距d為閘極309與P型井305之間距離的二至十倍。
在關斷偏壓狀態(blocking state)時，此時源極S接地，汲極D接正電壓，但此時汲極D電壓值會遠大於導通偏壓(forward conducting voltage)時之汲極D電壓值，閘極309則由正電壓降低至接地；P型井305與N型電流分散層304之表面、以及半導體保護層310、N型漂移區303、N型電流分散層304之接面快速形成空乏區，擊穿電場不會在絕緣層I之表面形成，換言之，擊穿電場會相較於習知技術向下移動至半導體保護層310與N型漂移區303之交界面，但由於半導體保護層310相較於絕緣層I為耐高壓材料，故半導體保護層310不會被擊穿電場所破壞以達到保護絕緣層I之效果。
請參考第4圖，第4圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之導通偏壓時之電壓電流圖，由電壓電流可以了解本發明之導通偏壓是介於習知技術1與習知技術2之間。
接著請同時參考第5圖，第5圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之關斷偏壓時之電壓電流圖，承前所述，本發明結構之崩潰電壓值係高於習知技術1與習知技術2，意即，本發明之結構在關斷偏壓時，比習知技術更能承受高電壓。
接著請同時參考第6圖，第6圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之閘極與汲極之間電容值。由第6圖可以了解，本發明結構之閘極與汲極之間電容值遠小於習知技術1與習知技術2。
最後請參考第7圖，第7圖顯示第1圖之習知技術1、第2圖之習知技術2、以及本發明結構之絕緣層電場。其中，橫座標係以各結構圖之絕緣層與N型漂移區之交界處為原點，往x軸沿伸之距離。同前所述，習知技術2與本發明之絕緣層電場接近0，而習知技術1之絕緣層電場則遠大於本發明，故習知技術1之絕緣層會被擊穿電場所破壞。
請注意，本發明之結構在一實施例中係適用於碳化矽(SiC)、氮化鎵(GaN)、以及矽至少其一之材料。
綜上所述，本發明提供一個溝槽式閘極功率金氧半 場效電晶體之結構，具有在關斷偏壓時較習知技術更能耐高電壓；且電容值更小於習知技術，使得導通偏壓與關斷偏壓之間切換時更快速；最後又能有效保護絕緣層不被擊穿電場所破壞。故，本發明能解決習知技術的缺點。

Claims (11)

  1. 一種溝槽式閘極功率金氧半場效電晶體(UMOSFET)之結構，該結構包含：一金屬層，分別設置於該結構之一上表面與一底面，以分別形成一源極與一汲極，以做為該結構與外界連結之電極；一N型半導體基板，設置於該汲極上；一N型漂移區(N-drift region)，設置於該N型半導體基板上；一N型電流分散層(N-current spread layer,N-CSL)，設置於該N型漂移區上；一P型井(P-well)，設置於該N型電流分散層上；一N型半導體層，設置於該P型井上；一第一P型半導體層，相鄰於該N型半導體層並設置於該P型井上；一溝槽，延伸通過該N型半導體層、該P型井以及該N型電流分散層，該溝槽之底部終止於該N型漂移區；一絕緣層，設置於該溝槽內；一分離閘極(split gate)，設置於該溝槽之該絕緣層中並被該絕緣層所包覆；一閘極，設置於該溝槽之該絕緣層中，且在該分離閘極之上；且該閘極自該N型半導體層所在之水平面，向下延伸經過該P型井、以及該N型電流分散層之上緣等所在之水平面；以及一半導體保護層，設置於該溝槽之底部以下，並相鄰於該N型漂移區，且該絕緣層設置於該半導體保護層之上，用以在該結構關斷偏壓時，保護該絕緣層避免被電場所擊穿；其中，該閘極與該分離閘極係被該絕緣層所區隔出一預設間距；以及，該閘極之底部深度位置係深於該P型井與該N型電流分散層之交界面。
  2. 如申請專利範圍第1項所述之結構，其中，該分離閘極之底面係接觸該半導體保護層上緣，且該閘極不圍繞該分離閘極。
  3. 如申請專利範圍第1項所述之結構，其中，該分離閘極之底面與該半導體保護層之間具有該絕緣層，該閘極不圍繞該分離閘極，且該分離閘極之底面係不接觸該半導體保護層上緣。
  4. 如申請專利範圍第2項所述之結構，其中，該半導體保護層與分離閘極係接地，避免該半導體保護層與分離閘極間有漏電流產生。
  5. 如申請專利範圍第3項所述之結構，其中，該半導體保護層與分離閘極係接地，避免該半導體保護層與分離閘極漏電流產生。
  6. 如申請專利範圍第4項所述之結構，其中，該N型半導體基板、該N型電流分散層、該N型漂移區與該N型半導體層中摻雜之一N型半導體且濃度為：該N型漂移區<該N型電流分散層。
  7. 如申請專利範圍第5項所述之結構，其中，該N型半導體基板、該N型電流分散層、該N型漂移區與該N型半導體層中摻雜之一N型半導體且濃度為：該N型漂移區<該N型電流分散層。
  8. 如申請專利範圍第6項所述之結構，其中，該閘極與該分離閘極之間的電容值小於該閘極與該N型電流分散層之間的電容值；該閘極與該P型井之間距離小於該預設間距。
  9. 如申請專利範圍第7項所述之結構，其中，該閘極與該分離閘極之間的電容值小於該閘極與該N型電流分散層之間的電容值；該閘極與該P型井之間距離小於該預設間距。
  10. 如申請專利範圍第8項所述之結構，其中，該半導體保護層為一第二P型半導體層；該結構適用於碳化矽(SiC)、氮化鎵(GaN)、以及矽至少其一。
  11. 如申請專利範圍第9項所述之結構，其中，該半導體保護層為一第二P型半導體層；該結構適用於碳化矽(SiC)、氮化鎵(GaN)、以及矽至少其一。
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CN108807540B (zh) 2022-05-17
US20180315848A1 (en) 2018-11-01
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CN108807540A (zh) 2018-11-13
US20190355847A1 (en) 2019-11-21

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