US20190355847A1 - Structure of trench metal-oxide-semiconductor field-effect transistor - Google Patents
Structure of trench metal-oxide-semiconductor field-effect transistor Download PDFInfo
- Publication number
- US20190355847A1 US20190355847A1 US16/526,588 US201916526588A US2019355847A1 US 20190355847 A1 US20190355847 A1 US 20190355847A1 US 201916526588 A US201916526588 A US 201916526588A US 2019355847 A1 US2019355847 A1 US 2019355847A1
- Authority
- US
- United States
- Prior art keywords
- layer
- gate
- disposed
- type semiconductor
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 230000005669 field effect Effects 0.000 title claims abstract description 6
- 230000005684 electric field Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 11
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the invention relates to a trench metal-oxide-semiconductor field-effect transistor (UMOSFET).
- UMOSFET trench metal-oxide-semiconductor field-effect transistor
- Silicon carbide (SiC) consists of crystals of alternating planar hexagonal lattices of silicon and carbon atoms, and has a wider band than silicon and a much higher critical (or breakdown) electric field. So, the breakdown voltage of the SiC element is better than that of the silicon element.
- the typical SiC concurrently has the lower hole concentration and the shorter minority carrier lifetimes, and the shorter minority carrier lifetimes allow the bipolar devices in the SiC to switch more rapidly than the silicon.
- the on-resistance of SiC bipolar transistor cannot be effectively improved. Meanwhile, its drawback is the requirement of the drive current.
- MOSFET metal-oxide-semiconductor field-effect transistor
- FIG. 1 is a schematic view showing a UMOSFET structure 100 of a first prior art.
- the structure 100 includes metal layers 101 S and 101 D, an N-type semiconductor substrate 102 , an N-drift region 103 , a P-well 105 , an N-type semiconductor layer 106 , a P-type semiconductor layer 107 , a trench T, an insulating layer I and a gate 109 .
- the critical electric field is generated at a corner B of the structure 100 , the insulating layer I at the corner B (depicted by the circular dashed line) is easily damaged by the critical electric field in the off-state.
- the gate-drain capacitor Cgd of the structure 100 of FIG. 1 is as shown by the bold dashed line range.
- FIG. 2 is a schematic view showing a UMOSFET structure 200 of a second prior art.
- the structure 200 includes metal layers 201 S and 201 D, an N-type semiconductor substrate 202 , an N-drift region 203 , an N-current spread layer (N-CSL) 204 , a P-well 205 , an N-type semiconductor layer 206 , a P-type semiconductor layer 207 , a trench T, an insulating layer I, a gate 209 and a semiconductor protection layer 210 .
- N-CSL N-current spread layer
- the structure 200 adopts the semiconductor protection layer 210 to improve the drawback that the corner B of FIG. 1 is easily damaged by the critical electric field when the bias is turned off.
- the gate-drain capacitor Cgd thereof is shown by the bold dashed line range, and the range thereof is in the portion of the gate 209 going deeply into the N-CSL 204 .
- One of the objectives of the invention is to provide a UMOSFET structure having a semiconductor protection layer, which is used to protect the UMOSFET structure from being damaged by the critical electric field.
- One of the objectives of the invention is to provide a UMOSFET structure having a current spread layer, which can reduce the resistance value of the UMOSFET structure.
- One of the objectives of the invention is to provide a UMOSFET structure having a gate and a split gate to reduce the capacitance of the UMOSFET structure, so that the element between blocking and forward conducting states can be switched rapidly.
- the invention provides a structure of a UMOSFET, and the structure includes: a metal layer disposed on a top surface and a bottom surface of the structure to form a source and a drain, respectively, to function as electrodes of the structure connected to an external device; an N-type semiconductor substrate disposed on the drain; an N-drift region disposed on the N-type semiconductor substrate; an N-current spread layer (N-CSL) disposed on the N-drift region; a P-well disposed on the N-CSL; an N-type semiconductor layer disposed on the P-well; a first P-type semiconductor layer adjacent to the N-type semiconductor layer and disposed on the P-well; a trench extending through the N-type semiconductor layer, the P-well and the N-CSL, wherein a bottom of the trench terminates at the N-drift region; an insulating layer disposed in the trench; a split gate disposed in the insulating layer of the trench and covered by the insulating layer; a gate disposed in the insulating
- FIG. 1 is a schematic view showing a UMOSFET structure 100 of a first prior art.
- FIG. 2 is a schematic view showing a UMOSFET structure 200 of a second prior art.
- FIG. 3A is a schematically cross-sectional side view showing a UMOSFET structure according to an embodiment of the invention.
- FIG. 3B is a schematically cross-sectional side view showing the UMOSFET structure according to an embodiment of the invention.
- FIG. 3C is an on-switching characteristic chart showing the structure according to an embodiment of the invention.
- FIG. 3D is an off-switching characteristic chart showing the structure according to an embodiment of the invention.
- FIG. 4 is a voltage-current comparison chart showing the first prior art of FIG. 1 , the second prior art of FIG. 2 , and the structure of the invention at the forward conducting bias.
- FIG. 5 is a voltage-current comparison chart showing the first prior art of FIG. 1 , the second prior art of FIG. 2 , and the structure of the invention when the bias is turned off.
- FIG. 6 is a comparison chart showing the capacitances between the gates and the drains in the first prior art of FIG. 1 , the second prior art of FIG. 2 , and the structure of the invention.
- FIG. 7 is a comparison chart showing insulating-layer electric fields in the first prior art of FIG. 1 , the second prior art of FIG. 2 , and the structure of the invention.
- FIG. 3A is a schematically cross-sectional side view showing a UMOSFET structure according to an embodiment of the invention.
- a structure 300 A is a structure of a UMOSFET used in SiC in an embodiment.
- the structure 300 A includes: metal layers 301 S and 301 D, an N-type semiconductor substrate 302 , an N-drift region 303 , an N-current spread layer (N-CSL) 304 , a P-well 305 , an N-type semiconductor layer 306 , a P-type semiconductor layer 307 , a trench T, an insulating layer I, a split gate 308 , a gate 309 and a semiconductor protection layer 310 .
- the metal layers 301 S and 301 D are respectively disposed on a top surface and a bottom surface of the structure 300 A to form a source and a drain, respectively, to function as electrodes of the structure 300 A connected to an external device.
- the N-type semiconductor substrate 302 is disposed on the drain D.
- the N-drift region 303 is disposed on the N-type semiconductor substrate 302 .
- the N-current spread layer 304 is disposed on the N-drift region 303 .
- the P-well 305 is disposed on the current spread layer 304 .
- the N-type semiconductor layer 306 is disposed on the P-well 305 .
- the P-type semiconductor layer 307 is adjacent to the N-type semiconductor layer 306 and disposed on the P-well 305 .
- the trench T extends downwards through the N-type semiconductor layer 306 , the P-well 305 and the N-current spread layer 304 , and finally a bottom of the trench T terminates at the N-drift region
- the semiconductor protection layer 310 below the bottom of the trench T is formed by way of ion implantation, and the semiconductor protection layer 310 is adjacent to the N-drift region 303 .
- the bottom surface of the split gate 308 contacts an upper edge of the semiconductor protection layer 310 , the semiconductor protection layer 310 is used to protect the insulating layer I from being destroyed by the breakdown electric field when the structure 300 A turns off the bias.
- the semiconductor protection layer 310 and the split gate 308 are grounded to prevent a leakage current from being generated between the semiconductor protection layer 310 and the split gate 308 .
- the semiconductor protection layer 310 is a P-type semiconductor layer in an embodiment, and the semiconductor protection layer 310 and the split gate 308 are grounded. Because the semiconductor protection layer 310 and the split gate 308 have the equal potential, it is possible to prevent the leakage current from being generated between the semiconductor protection layer 310 and the split gate 308 .
- the semiconductor protection layer 310 is used to protect the insulating layer I from being destroyed by the breakdown electric field when the structure 300 A turns off the bias.
- the insulating layer I is disposed in the trench T, and is adjacent to the N-type semiconductor layer 306 , the P-well 305 , the N-current spread layer 304 , the N-drift region 303 and the semiconductor protection layer 310 , respectively.
- the split gate 308 is disposed in the insulating layer I of the trench, and the gate 309 is disposed in the insulating layer of the trench T and above the split gate 308 .
- the gate 309 and the split gate 308 are separated from each other by the insulating layer I to form a predetermined gap d.
- a depth position of a bottom of the gate 309 is deeper than an interface between the P-well 305 and the N-current spread layer 304 .
- the gate 309 and the split gate 308 may be considered as being covered by the insulating layer I.
- the insulating layer I is implemented by semiconductor oxide or semiconductor nitride, and the split gate 308 and the gate 309 are implemented by polysilicon (poly-Si).
- FIG. 3B is a schematically cross-sectional side view showing the UMOSFET structure according to an embodiment of the invention.
- a structure 300 B is a structure of a UMOSFET used in SiC in an embodiment.
- the difference between the structures 300 B and 300 A is that the insulating layer I is disposed on the semiconductor protection layer 310 , the insulating layer I is disposed between the bottom surface of the split gate 308 and the semiconductor protection layer 310 . That is, the bottom surface of the split gate 308 does not contact the upper edge of the semiconductor protection layer 310 .
- the N-type semiconductor substrate 302 , the N-drift region 303 , the N-current spread layer 304 and the N-type semiconductor layer 306 are doped with an N-type semiconductor with the concentrations satisfying: the N-drift region 303 ⁇ the N-current spread layer 304 . Because a depletion region is generated in the N-drift region 303 and the N-current spread layer 304 when the structure 300 B turns off a bias, and the N-drift region 303 is a high-voltage withstanding component, the N-drift region 303 has the lowest N-type semiconductor concentration.
- the source S When the structure 300 B is at the forward conducting bias, the source S is grounded, the drain D is connected to a positive voltage, and the gate 309 is also connected to a positive voltage.
- the electrons flow from the N-type semiconductor layer 306 to the drain D, and the current is uniformly spread through the N-current spread layer 304 .
- the N-current spread layer 304 increases the current flow and decreases the resistance value of the structure 300 B.
- FIG. 3C is an on-switching characteristic chart showing the structure according to an embodiment of the invention.
- FIG. 3D is an off-switching characteristic chart showing the structure according to an embodiment of the invention.
- the capacitance between the gate 309 and the split gate 308 is smaller than the capacitance between the gate 309 and the N-current spread layer 304 .
- the capacitance of the structure 300 B is compared with those of the prior arts, the capacitance thereof only corresponds to the gate 309 exceeding the portions of the P-well 305 and the N-current spread layer 304 .
- the structure 300 B uses the insulating layer I to separate the gate 309 from the split gate 308 to make the capacitance used in the structure 300 B be much smaller than those of the prior arts. Consequently, when the structure 300 B is switched between the forward conducting and blocking states, the capacitor charging or discharging is faster than those of the prior arts. Regarding this portion, FIGS. 3C and 3D can prove that the charge/discharge speed of the structure of the invention is higher than those of the prior arts.
- the split gate 308 is a metal layer, which is grounded to prevent the gate-drain capacitor Cgd between the gate 309 and the split gate 308 from being generated. So, the gate-drain capacitor Cgd of the invention is much smaller than that of the prior art at only the virtual frame portion. Furthermore, the gate 209 of the structure 200 of the second prior art going deeply into the N-current spread layer 204 by the depth greater than the structure 300 B, so the gate-drain capacitor Cgd of the structure 200 is much larger than that of the structure 300 B.
- a distance (such as the virtual frame) between the gate 309 and the P-well 305 is smaller than a predetermined gap d, and the predetermined gap d is two to ten times of the distance between the gate 309 and the P-well 305 .
- the source S is grounded, the drain D is connected to the positive voltage.
- the voltage value of the drain D is much higher than the voltage value of the drain D at the forward conducting bias; the voltage of the gate 309 is lowered from the positive voltage to the ground; and the surface of the P-well 305 and the N-current spread layer 304 , and the junction of the semiconductor protection layer 310 , the N-drift region 303 and the N-current spread layer 304 quickly form a depletion region, and the critical electric field is not formed on the surface of the insulating layer I.
- the critical electric field is moved downward to the interface between the semiconductor protection layer 310 and the N-drift region 303 .
- the semiconductor protection layer 310 is made of a high-voltage withstanding material, the semiconductor protection layer 310 is not damaged by the critical electric field to achieve the effect of protecting the insulating layer I.
- FIG. 4 is a voltage-current chart showing the first prior art of FIG. 1 , the second prior art of FIG. 2 and the structure of the invention at the forward conducting bias. Referring to the voltage-current chart of FIG. 4 , it is understood that the forward conducting bias of the invention ranges between the first and second prior arts.
- FIG. 5 is a voltage-current chart showing the first prior art of FIG. 1 , the second prior art of FIG. 2 , and the structure of the invention when the bias is turned off.
- the breakdown voltage value of the structure of the invention is higher than those of the first and second prior arts. That is, the structure of the invention can withstand higher voltages than the prior art when the bias is turned off.
- FIG. 6 shows the capacitances between the gates and the drains in the first prior art of FIG. 1 , the second prior art of FIG. 2 and the structure of the invention. As can be understood from FIG. 6 , the capacitance between the gate and the drain in the structure of the invention is much smaller than those of the first and second prior arts.
- FIG. 7 shows insulating-layer electric fields in the first prior art of FIG. 1 , the second prior art of FIG. 2 and the structure of the invention, wherein the abscissa denotes the distance extending from the original, which is the interface between the insulating layer and the N-drift region, to the x axis in each structure diagram.
- the insulating-layer electric fields of the second prior art and the invention are close to zero, and the insulating-layer electric field of the first prior art is much stronger than that of the invention, so the insulating layer of the first prior art will be damaged by the critical electric field.
- the structure of the invention is applicable to the material of at least one of silicon carbide (SiC), gallium nitride (GaN) and silicon in an embodiment.
- the invention provides a structure of a trench metal-oxide-semiconductor field-effect transistor, which can withstand the higher voltage than the prior art at the turn-off bias, and has the capacitance smaller than that of the prior art, so that the switching between the forward conducting bias and the turn-off bias becomes faster.
- the invention can eliminate the drawbacks of the prior art.
Abstract
A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.
Description
- This application is a Divisional of co-pending application Ser. No. 15/961,043, filed on Apr. 24, 2018, for which priority is claimed under 35 U.S.C. § 120, which claims priority of No. 106113870 filed in Taiwan R.O.C. on Apr. 26, 2017 under 35 USC 119, the entire content of which is hereby incorporated by reference.
- The invention relates to a trench metal-oxide-semiconductor field-effect transistor (UMOSFET).
- Silicon carbide (SiC) consists of crystals of alternating planar hexagonal lattices of silicon and carbon atoms, and has a wider band than silicon and a much higher critical (or breakdown) electric field. So, the breakdown voltage of the SiC element is better than that of the silicon element. In addition, the typical SiC concurrently has the lower hole concentration and the shorter minority carrier lifetimes, and the shorter minority carrier lifetimes allow the bipolar devices in the SiC to switch more rapidly than the silicon. However, the on-resistance of SiC bipolar transistor cannot be effectively improved. Meanwhile, its drawback is the requirement of the drive current. In contrast, the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) has the advantages of voltage-driving and high-frequency operation.
-
FIG. 1 is a schematic view showing aUMOSFET structure 100 of a first prior art. Referring toFIG. 1 , thestructure 100 includesmetal layers 101S and 101D, an N-type semiconductor substrate 102, an N-drift region 103, a P-well 105, an N-type semiconductor layer 106, a P-type semiconductor layer 107, a trench T, an insulating layer I and agate 109. Because thestructure 100 of the first prior art has design defects, the critical electric field is generated at a corner B of thestructure 100, the insulating layer I at the corner B (depicted by the circular dashed line) is easily damaged by the critical electric field in the off-state. In addition, the gate-drain capacitor Cgd of thestructure 100 ofFIG. 1 is as shown by the bold dashed line range. -
FIG. 2 is a schematic view showing aUMOSFET structure 200 of a second prior art. Referring toFIG. 2 , thestructure 200 includesmetal layers 201S and 201D, an N-type semiconductor substrate 202, an N-drift region 203, an N-current spread layer (N-CSL) 204, a P-well 205, an N-type semiconductor layer 206, a P-type semiconductor layer 207, a trench T, an insulating layer I, agate 209 and asemiconductor protection layer 210. Although thestructure 200 adopts thesemiconductor protection layer 210 to improve the drawback that the corner B ofFIG. 1 is easily damaged by the critical electric field when the bias is turned off. However, the because thestructure 200 has the higher capacitance between the gate terminal and the drain terminal, the longer time is required to charge/discharge when the element is switched between the forward conducting and blocking states. Furthermore, the gate-drain capacitor Cgd thereof is shown by the bold dashed line range, and the range thereof is in the portion of thegate 209 going deeply into the N-CSL 204. - One of the objectives of the invention is to provide a UMOSFET structure having a semiconductor protection layer, which is used to protect the UMOSFET structure from being damaged by the critical electric field.
- One of the objectives of the invention is to provide a UMOSFET structure having a current spread layer, which can reduce the resistance value of the UMOSFET structure.
- One of the objectives of the invention is to provide a UMOSFET structure having a gate and a split gate to reduce the capacitance of the UMOSFET structure, so that the element between blocking and forward conducting states can be switched rapidly.
- The invention provides a structure of a UMOSFET, and the structure includes: a metal layer disposed on a top surface and a bottom surface of the structure to form a source and a drain, respectively, to function as electrodes of the structure connected to an external device; an N-type semiconductor substrate disposed on the drain; an N-drift region disposed on the N-type semiconductor substrate; an N-current spread layer (N-CSL) disposed on the N-drift region; a P-well disposed on the N-CSL; an N-type semiconductor layer disposed on the P-well; a first P-type semiconductor layer adjacent to the N-type semiconductor layer and disposed on the P-well; a trench extending through the N-type semiconductor layer, the P-well and the N-CSL, wherein a bottom of the trench terminates at the N-drift region; an insulating layer disposed in the trench; a split gate disposed in the insulating layer of the trench and covered by the insulating layer; a gate disposed in the insulating layer of the trench and above the split gate; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, and the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the gate is deeper than an interface between the P-well and the N-CSL.
-
FIG. 1 is a schematic view showing aUMOSFET structure 100 of a first prior art. -
FIG. 2 is a schematic view showing aUMOSFET structure 200 of a second prior art. -
FIG. 3A is a schematically cross-sectional side view showing a UMOSFET structure according to an embodiment of the invention. -
FIG. 3B is a schematically cross-sectional side view showing the UMOSFET structure according to an embodiment of the invention. -
FIG. 3C is an on-switching characteristic chart showing the structure according to an embodiment of the invention. -
FIG. 3D is an off-switching characteristic chart showing the structure according to an embodiment of the invention. -
FIG. 4 is a voltage-current comparison chart showing the first prior art ofFIG. 1 , the second prior art ofFIG. 2 , and the structure of the invention at the forward conducting bias. -
FIG. 5 is a voltage-current comparison chart showing the first prior art ofFIG. 1 , the second prior art ofFIG. 2 , and the structure of the invention when the bias is turned off. -
FIG. 6 is a comparison chart showing the capacitances between the gates and the drains in the first prior art ofFIG. 1 , the second prior art ofFIG. 2 , and the structure of the invention. -
FIG. 7 is a comparison chart showing insulating-layer electric fields in the first prior art ofFIG. 1 , the second prior art ofFIG. 2 , and the structure of the invention. -
FIG. 3A is a schematically cross-sectional side view showing a UMOSFET structure according to an embodiment of the invention. As shown inFIG. 3A , astructure 300A is a structure of a UMOSFET used in SiC in an embodiment. - The
structure 300A includes:metal layers type semiconductor substrate 302, an N-drift region 303, an N-current spread layer (N-CSL) 304, a P-well 305, an N-type semiconductor layer 306, a P-type semiconductor layer 307, a trench T, an insulating layer I, asplit gate 308, agate 309 and asemiconductor protection layer 310. - The
metal layers structure 300A to form a source and a drain, respectively, to function as electrodes of thestructure 300A connected to an external device. The N-type semiconductor substrate 302 is disposed on the drain D. The N-drift region 303 is disposed on the N-type semiconductor substrate 302. The N-current spread layer 304 is disposed on the N-drift region 303. The P-well 305 is disposed on thecurrent spread layer 304. The N-type semiconductor layer 306 is disposed on the P-well 305. The P-type semiconductor layer 307 is adjacent to the N-type semiconductor layer 306 and disposed on the P-well 305. The trench T extends downwards through the N-type semiconductor layer 306, the P-well 305 and the N-current spread layer 304, and finally a bottom of the trench T terminates at the N-drift region 303. - It is to be noted that, in this embodiment, the
semiconductor protection layer 310 below the bottom of the trench T is formed by way of ion implantation, and thesemiconductor protection layer 310 is adjacent to the N-drift region 303. In this embodiment, the bottom surface of thesplit gate 308 contacts an upper edge of thesemiconductor protection layer 310, thesemiconductor protection layer 310 is used to protect the insulating layer I from being destroyed by the breakdown electric field when thestructure 300A turns off the bias. In addition, thesemiconductor protection layer 310 and thesplit gate 308 are grounded to prevent a leakage current from being generated between thesemiconductor protection layer 310 and thesplit gate 308. - Note that the
semiconductor protection layer 310 is a P-type semiconductor layer in an embodiment, and thesemiconductor protection layer 310 and thesplit gate 308 are grounded. Because thesemiconductor protection layer 310 and thesplit gate 308 have the equal potential, it is possible to prevent the leakage current from being generated between thesemiconductor protection layer 310 and thesplit gate 308. - The
semiconductor protection layer 310 is used to protect the insulating layer I from being destroyed by the breakdown electric field when thestructure 300A turns off the bias. The insulating layer I is disposed in the trench T, and is adjacent to the N-type semiconductor layer 306, the P-well 305, the N-current spread layer 304, the N-drift region 303 and thesemiconductor protection layer 310, respectively. Thesplit gate 308 is disposed in the insulating layer I of the trench, and thegate 309 is disposed in the insulating layer of the trench T and above thesplit gate 308. Thegate 309 and thesplit gate 308 are separated from each other by the insulating layer I to form a predetermined gap d. A depth position of a bottom of thegate 309 is deeper than an interface between the P-well 305 and the N-current spread layer 304. In an embodiment, thegate 309 and thesplit gate 308 may be considered as being covered by the insulating layer I. The insulating layer I is implemented by semiconductor oxide or semiconductor nitride, and thesplit gate 308 and thegate 309 are implemented by polysilicon (poly-Si). -
FIG. 3B is a schematically cross-sectional side view showing the UMOSFET structure according to an embodiment of the invention. As shown inFIG. 3B , astructure 300B is a structure of a UMOSFET used in SiC in an embodiment. - As previously mentioned, the difference between the
structures semiconductor protection layer 310, the insulating layer I is disposed between the bottom surface of thesplit gate 308 and thesemiconductor protection layer 310. That is, the bottom surface of thesplit gate 308 does not contact the upper edge of thesemiconductor protection layer 310. - In this embodiment, the N-
type semiconductor substrate 302, the N-drift region 303, the N-current spread layer 304 and the N-type semiconductor layer 306 are doped with an N-type semiconductor with the concentrations satisfying: the N-drift region 303<the N-current spread layer 304. Because a depletion region is generated in the N-drift region 303 and the N-current spread layer 304 when thestructure 300B turns off a bias, and the N-drift region 303 is a high-voltage withstanding component, the N-drift region 303 has the lowest N-type semiconductor concentration. - When the
structure 300B is at the forward conducting bias, the source S is grounded, the drain D is connected to a positive voltage, and thegate 309 is also connected to a positive voltage. The electrons flow from the N-type semiconductor layer 306 to the drain D, and the current is uniformly spread through the N-current spread layer 304. In other words, the N-current spread layer 304 increases the current flow and decreases the resistance value of thestructure 300B. -
FIG. 3C is an on-switching characteristic chart showing the structure according to an embodiment of the invention.FIG. 3D is an off-switching characteristic chart showing the structure according to an embodiment of the invention. Please note and also refer toFIGS. 3C and 3D , it is understood that the capacitance between thegate 309 and thesplit gate 308 is smaller than the capacitance between thegate 309 and the N-current spread layer 304. When the capacitance of thestructure 300B is compared with those of the prior arts, the capacitance thereof only corresponds to thegate 309 exceeding the portions of the P-well 305 and the N-current spread layer 304. So, thestructure 300B uses the insulating layer I to separate thegate 309 from thesplit gate 308 to make the capacitance used in thestructure 300B be much smaller than those of the prior arts. Consequently, when thestructure 300B is switched between the forward conducting and blocking states, the capacitor charging or discharging is faster than those of the prior arts. Regarding this portion,FIGS. 3C and 3D can prove that the charge/discharge speed of the structure of the invention is higher than those of the prior arts. - Furthermore, because the
split gate 308 is a metal layer, which is grounded to prevent the gate-drain capacitor Cgd between thegate 309 and thesplit gate 308 from being generated. So, the gate-drain capacitor Cgd of the invention is much smaller than that of the prior art at only the virtual frame portion. Furthermore, thegate 209 of thestructure 200 of the second prior art going deeply into the N-current spread layer 204 by the depth greater than thestructure 300B, so the gate-drain capacitor Cgd of thestructure 200 is much larger than that of thestructure 300B. - A distance (such as the virtual frame) between the
gate 309 and the P-well 305 is smaller than a predetermined gap d, and the predetermined gap d is two to ten times of the distance between thegate 309 and the P-well 305. - In the off-state (blocking state), the source S is grounded, the drain D is connected to the positive voltage. At this time, however, the voltage value of the drain D is much higher than the voltage value of the drain D at the forward conducting bias; the voltage of the
gate 309 is lowered from the positive voltage to the ground; and the surface of the P-well 305 and the N-current spread layer 304, and the junction of thesemiconductor protection layer 310, the N-drift region 303 and the N-current spread layer 304 quickly form a depletion region, and the critical electric field is not formed on the surface of the insulating layer I. In other words, compared with the prior art, the critical electric field is moved downward to the interface between thesemiconductor protection layer 310 and the N-drift region 303. Compared with the insulating layer I, because thesemiconductor protection layer 310 is made of a high-voltage withstanding material, thesemiconductor protection layer 310 is not damaged by the critical electric field to achieve the effect of protecting the insulating layer I. -
FIG. 4 is a voltage-current chart showing the first prior art ofFIG. 1 , the second prior art ofFIG. 2 and the structure of the invention at the forward conducting bias. Referring to the voltage-current chart ofFIG. 4 , it is understood that the forward conducting bias of the invention ranges between the first and second prior arts. -
FIG. 5 is a voltage-current chart showing the first prior art ofFIG. 1 , the second prior art ofFIG. 2 , and the structure of the invention when the bias is turned off. Referring next toFIG. 5 , as stated before, the breakdown voltage value of the structure of the invention is higher than those of the first and second prior arts. That is, the structure of the invention can withstand higher voltages than the prior art when the bias is turned off. -
FIG. 6 shows the capacitances between the gates and the drains in the first prior art ofFIG. 1 , the second prior art ofFIG. 2 and the structure of the invention. As can be understood fromFIG. 6 , the capacitance between the gate and the drain in the structure of the invention is much smaller than those of the first and second prior arts. -
FIG. 7 shows insulating-layer electric fields in the first prior art ofFIG. 1 , the second prior art ofFIG. 2 and the structure of the invention, wherein the abscissa denotes the distance extending from the original, which is the interface between the insulating layer and the N-drift region, to the x axis in each structure diagram. As previously mentioned, the insulating-layer electric fields of the second prior art and the invention are close to zero, and the insulating-layer electric field of the first prior art is much stronger than that of the invention, so the insulating layer of the first prior art will be damaged by the critical electric field. - Note that the structure of the invention is applicable to the material of at least one of silicon carbide (SiC), gallium nitride (GaN) and silicon in an embodiment.
- In summary, the invention provides a structure of a trench metal-oxide-semiconductor field-effect transistor, which can withstand the higher voltage than the prior art at the turn-off bias, and has the capacitance smaller than that of the prior art, so that the switching between the forward conducting bias and the turn-off bias becomes faster. Finally, it is possible to effectively protect the insulation layer from being damaged by the critical electric field. Therefore, the invention can eliminate the drawbacks of the prior art.
Claims (5)
1. A structure of a trench metal-oxide-semiconductor field-effect transistor (UMOSFET), the structure comprising:
a metal layer disposed on a top surface and a bottom surface of the structure to form a source and a drain, respectively, to function as electrodes of the structure connected to an external device;
an N-type semiconductor substrate disposed on the drain;
an N-drift region disposed on the N-type semiconductor substrate;
an N-current spread layer (N-CSL) disposed on the N-drift region;
a P-well disposed on the N-CSL;
an N-type semiconductor layer disposed on the P-well;
a first P-type semiconductor layer adjacent to the N-type semiconductor layer and disposed on the P-well;
a trench extending through the N-type semiconductor layer, the P-well and the N-CSL, wherein a bottom of the trench terminates at the N-drift region;
an insulating layer disposed in the trench;
a split gate disposed in the insulating layer of the trench and covered by the insulating layer;
a gate disposed in the insulating layer of the trench and above the split gate; and
a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias;
wherein the gate and the split gate are separated from each other by the insulating layer to form a predetermined gap; and a depth position of a bottom of the gate is deeper than an interface between the P-well and the N-CSL;
wherein the insulating layer is disposed between a bottom surface of the split gate and the semiconductor protection layer.
2. The structure of the UMOSFET according to claim 1 , wherein the semiconductor protection layer and the split gate are grounded to prevent a leakage current from being generated between the semiconductor protection layer and the split gate.
3. The structure of the UMOSFET according to claim 2 , wherein the N-type semiconductor substrate, the N-CSL, the N-drift region and the N-type semiconductor layer are doped with an N-type semiconductor with concentrations satisfying:
the N-drift region<the N-CSL.
the N-drift region<the N-CSL.
4. The structure of the UMOSFET according to claim 3 , wherein a capacitance between the gate and the split gate is smaller than a capacitance between the gate and the N-CSL; and a distance between the gate and the P-well is smaller than the predetermined gap.
5. The structure of the UMOSFET according to claim 4 , wherein the semiconductor protection layer is a second P-type semiconductor layer; and the structure is applicable to at least one of silicon carbide (SiC), gallium nitride (GaN) and silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/526,588 US20190355847A1 (en) | 2017-04-26 | 2019-07-30 | Structure of trench metal-oxide-semiconductor field-effect transistor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106113870 | 2017-04-26 | ||
TW106113870A TWI663725B (en) | 2017-04-26 | 2017-04-26 | Structure of u-metal-oxide-semiconductor field-effect transistor |
US15/961,043 US10468519B2 (en) | 2017-04-26 | 2018-04-24 | Structure of trench metal-oxide-semiconductor field-effect transistor |
US16/526,588 US20190355847A1 (en) | 2017-04-26 | 2019-07-30 | Structure of trench metal-oxide-semiconductor field-effect transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/961,043 Division US10468519B2 (en) | 2017-04-26 | 2018-04-24 | Structure of trench metal-oxide-semiconductor field-effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190355847A1 true US20190355847A1 (en) | 2019-11-21 |
Family
ID=63916828
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/961,043 Active US10468519B2 (en) | 2017-04-26 | 2018-04-24 | Structure of trench metal-oxide-semiconductor field-effect transistor |
US16/526,588 Abandoned US20190355847A1 (en) | 2017-04-26 | 2019-07-30 | Structure of trench metal-oxide-semiconductor field-effect transistor |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/961,043 Active US10468519B2 (en) | 2017-04-26 | 2018-04-24 | Structure of trench metal-oxide-semiconductor field-effect transistor |
Country Status (3)
Country | Link |
---|---|
US (2) | US10468519B2 (en) |
CN (1) | CN108807540B (en) |
TW (1) | TWI663725B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11189702B2 (en) * | 2019-01-30 | 2021-11-30 | Vishay SIliconix, LLC | Split gate semiconductor with non-uniform trench oxide |
TWI773029B (en) * | 2020-12-17 | 2022-08-01 | 國立清華大學 | Semiconductor structure with trench junction barrier schottky (tjbs) diode |
TWI823639B (en) * | 2022-10-20 | 2023-11-21 | 世界先進積體電路股份有限公司 | Semiconductor device and methods for forming the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080017920A1 (en) * | 2006-01-05 | 2008-01-24 | Steven Sapp | Structure and method for improving shielded gate field effect transistors |
US20110254010A1 (en) * | 2010-04-16 | 2011-10-20 | Cree, Inc. | Wide Band-Gap MOSFETs Having a Heterojunction Under Gate Trenches Thereof and Related Methods of Forming Such Devices |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4587712A (en) | 1981-11-23 | 1986-05-13 | General Electric Company | Method for making vertical channel field controlled device employing a recessed gate structure |
JPH0783118B2 (en) | 1988-06-08 | 1995-09-06 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5168331A (en) | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
US5488236A (en) | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
US5471075A (en) | 1994-05-26 | 1995-11-28 | North Carolina State University | Dual-channel emitter switched thyristor with trench gate |
JP3471509B2 (en) | 1996-01-23 | 2003-12-02 | 株式会社デンソー | Silicon carbide semiconductor device |
US5612232A (en) | 1996-03-29 | 1997-03-18 | Motorola | Method of fabricating semiconductor devices and the devices |
US5719409A (en) | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
US6180958B1 (en) | 1997-02-07 | 2001-01-30 | James Albert Cooper, Jr. | Structure for increasing the maximum voltage of silicon carbide power transistors |
US7405452B2 (en) * | 2004-02-02 | 2008-07-29 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
AT504289A2 (en) * | 2005-05-26 | 2008-04-15 | Fairchild Semiconductor | TRENCH-GATE FIELD EFFECT TRANSISTORS AND METHOD FOR MAKING THE SAME |
US7385248B2 (en) | 2005-08-09 | 2008-06-10 | Fairchild Semiconductor Corporation | Shielded gate field effect transistor with improved inter-poly dielectric |
US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
JP2008011205A (en) * | 2006-06-29 | 2008-01-17 | Toshiba Corp | Encoding device, decoding device, method, and information recording and reproducing device |
US7772668B2 (en) * | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US7750412B2 (en) * | 2008-08-06 | 2010-07-06 | Fairchild Semiconductor Corporation | Rectifier with PN clamp regions under trenches |
US7888970B1 (en) * | 2009-07-29 | 2011-02-15 | Faraday Technology Corp. | Switch controlling circuit, switch circuit utilizing the switch controlling circuit and methods thereof |
US20170125531A9 (en) * | 2009-08-31 | 2017-05-04 | Yeeheng Lee | Thicker bottom oxide for reduced miller capacitance in trench metal oxide semiconductor field effect transistor (mosfet) |
US8507978B2 (en) * | 2011-06-16 | 2013-08-13 | Alpha And Omega Semiconductor Incorporated | Split-gate structure in trench-based silicon carbide power device |
US20130113038A1 (en) | 2011-11-08 | 2013-05-09 | Feei Cherng Enterprise Co., Ltd. | Trench mosfet with split trenched gate structures in cell corners for gate charge reduction |
US9761702B2 (en) * | 2014-02-04 | 2017-09-12 | MaxPower Semiconductor | Power MOSFET having planar channel, vertical current path, and top drain electrode |
CN105702739B (en) * | 2016-05-04 | 2019-04-23 | 深圳尚阳通科技有限公司 | Shield grid groove MOSFET device and its manufacturing method |
CN106298939A (en) * | 2016-08-22 | 2017-01-04 | 电子科技大学 | A kind of accumulation type DMOS with complex media Rotating fields |
-
2017
- 2017-04-26 TW TW106113870A patent/TWI663725B/en active
-
2018
- 2018-04-19 CN CN201810352486.3A patent/CN108807540B/en active Active
- 2018-04-24 US US15/961,043 patent/US10468519B2/en active Active
-
2019
- 2019-07-30 US US16/526,588 patent/US20190355847A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080017920A1 (en) * | 2006-01-05 | 2008-01-24 | Steven Sapp | Structure and method for improving shielded gate field effect transistors |
US20110254010A1 (en) * | 2010-04-16 | 2011-10-20 | Cree, Inc. | Wide Band-Gap MOSFETs Having a Heterojunction Under Gate Trenches Thereof and Related Methods of Forming Such Devices |
Also Published As
Publication number | Publication date |
---|---|
CN108807540B (en) | 2022-05-17 |
TW201839982A (en) | 2018-11-01 |
CN108807540A (en) | 2018-11-13 |
US20180315848A1 (en) | 2018-11-01 |
US10468519B2 (en) | 2019-11-05 |
TWI663725B (en) | 2019-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10157983B2 (en) | Vertical power MOS-gated device with high dopant concentration N-well below P-well and with floating P-islands | |
US9324807B1 (en) | Silicon carbide MOSFET with integrated MOS diode | |
US10354992B2 (en) | Semiconductor devices and methods for forming a semiconductor device | |
US11682722B2 (en) | Vertical transistor structure with buried channel and resurf regions and method of manufacturing the same | |
JP2015526900A (en) | Semiconductor electronic components with built-in current limiters | |
US20190355847A1 (en) | Structure of trench metal-oxide-semiconductor field-effect transistor | |
JP2004095954A (en) | Semiconductor device | |
US9048215B2 (en) | Semiconductor device having a high breakdown voltage | |
CN114597257B (en) | Trench gate silicon carbide MOSFET device and process method thereof | |
GB2572442A (en) | Power semiconductor device with a double gate structure | |
KR20160079609A (en) | Silicon-carbide trench gate mosfets | |
US9324817B2 (en) | Method for forming a transistor device having a field electrode | |
KR20160029630A (en) | Semiconductor device | |
CN106992212B (en) | Transistor device with increased gate-drain capacitance | |
US10211331B2 (en) | Semiconductor device | |
US10355132B2 (en) | Power MOSFETs with superior high frequency figure-of-merit | |
US20070126057A1 (en) | Lateral DMOS device insensitive to oxide corner loss | |
WO2017174603A1 (en) | Short channel trench power mosfet | |
US10991812B2 (en) | Transistor device with a rectifier element between a field electrode and a source electrode | |
KR20200039235A (en) | Semiconductor device and method manufacturing the same | |
US20240145537A1 (en) | Semiconductor devices with additional mesa structures for reduced surface roughness | |
US20230275161A1 (en) | Semiconductor structure | |
KR102417362B1 (en) | Semiconductor device and method manufacturing the same | |
TW202335309A (en) | Semiconductor structure | |
JP2023090486A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |