TW202335309A - Semiconductor structure - Google Patents

Abstract

The present invention discloses a semiconductor structure, comprising: a Schottky diode structure, the Schottky diode structure comprises: a first N-type semiconductor layer, a first trench, a first insulating layer, at least two polysilicon layer (Poly-Si), a first P-type protective layer and a metal layer; the first trench extends through the first N-type semiconductor layer and is disposed in the first N-type semiconductor layer; the first insulating layer is disposed in the first trench; at least two polysilicon layers are disposed in the first trench, the upper polysilicon layer and the lower polysilicon layer are parallel, and the first insulating layer is located in the first trench; the first P-type protective layer is grounded and disposed on the bottom of the first trench, and the first p-type protective layer contacts the first insulating layer and the bottom surface of the lower polysilicon layer; the metal layer is respectively disposed on an upper surface and a lower bottom surface of the semiconductor structure, the metal layer respectively formed a source electrode and a drain electrode as electrodes for the external connection of the semiconductor structure; the metal layer covers the first trench, and has a Schottky junction at the junction of the metal layer and the top of the first N-type semiconductor layer; an accumulated electrons region is formed outside the first insulating layer; wherein, the interface between the bottom surface of the P-type protective layer and the first N-type semiconductor layer has a PN junction.

Description

semiconductor structure

The present invention relates to a semiconductor structure, in particular to a semiconductor structure having a Schottky diode.

The Schottky diode system is a diode element composed of a metal and semiconductor interface. Like a general PN junction diode, it has one-way conduction characteristics. In addition, because the Schottky diode moves in a unipolar manner, its starting voltage is lower than that of the PN diode element, and it responds faster when switching forward and reverse bias, so it is especially used for low power consumption. As well as increasing the switching speed, it is common in power conversion circuits, such as structures integrating MOSFET and Schottky diodes. In the conventional technology, a Schottky diode is connected in parallel externally to the MOSFET device as a rectifier; however, when the Schottky diode is connected in parallel to the MOSFET, the performance is reduced due to the increase in the parasitic inductance generated by the external connection, and the external Schottky diode The cost of diodes is higher.

The invention discloses a semiconductor structure, including: a Schottky diode structure. The Schottky diode structure includes: a first N-type semiconductor layer, a first trench, a first insulating layer, and at least two polycrystalline silicon layer (Poly-Si), a first P-type protective layer and a metal layer; the first trench extends through the first N-type semiconductor layer and is disposed in the first N-type semiconductor layer; the first insulating layer is disposed in the first In the trench; at least two polycrystalline silicon layers are arranged in the first trench, the upper polycrystalline silicon layer and the lower polycrystalline silicon layer are arranged in parallel, and the first insulating layer is located in the first trench; the first P-type protective layer is The first P-type protective layer is grounded and disposed at the bottom of the first trench, and the first P-type protective layer is in contact with the first insulating layer and the bottom surface of the lower polycrystalline silicon layer; the metal layer is respectively disposed on one of the upper surface and the lower bottom surface of the semiconductor structure to respectively A source electrode and a drain electrode are formed as electrodes for connecting the semiconductor structure to the outside world; the metal layer covers the first trench, and has a Xiao base junction at the interface between the metal layer and the top of the first N-type semiconductor layer, and An accumulated electrons region is formed outside the first insulating layer; the interface between the bottom surface of the first P-type protective layer and the first N-type semiconductor layer has a PN junction.

FIG. 1 shows a partial schematic diagram of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure 100 includes a Schottky diode structure 10 , and the Schottky diode structure 10 further includes a first N-type semiconductor layer 11 and a first trench 12 . , polycrystalline silicon layers (Poly-Si) 13a and 13b, the first P-type protective layer 14, the first insulating layer 15, and the metal layers M1 and M2.

Wherein, the first trench 12 extends through the first N-type semiconductor layer 11, and the first trench 12 is disposed in the first N-type semiconductor layer 11; in one embodiment, the first trench 12 can be regarded as the first N-type semiconductor layer 11. One of the semiconductor layers 11 is notched.

The first P-type protective layer 14 is used for grounding and is disposed at the bottom of the first trench 12; in one embodiment, the first P-type protective layer 14 covers the bottom of the first trench 12, and the first P-type protective layer 14 Part of the top surface contacts the bottom surface of the first insulating layer 15 and the underlying polycrystalline silicon layer 13b respectively; in other words, the first trench 12 is filled with the first P-type protective layer 14 and the polycrystalline silicon layers 13a and 13b in sequence. The remainder of trench 12 is filled with first insulating layer 15 .

In this embodiment, the upper crystalline silicon layer 13a and the lower polycrystalline silicon layer 13b are arranged parallel to each other, and there is a distance between them. That is, there is no contact between the upper polycrystalline silicon layer 13a and the lower polycrystalline silicon layer 13b.

Please note that different voltages can be applied to the polycrystalline silicon layers 13a and 13b respectively, thereby changing the conductive characteristics of the polycrystalline silicon layers 13a and 13b; in addition, the present invention does not limit the polycrystalline silicon layers 13a and 13b to be N-type semiconductors or P-type semiconductors. type semiconductor, the present invention should not be limited to this.

Metal layers M1 and M2 are respectively disposed on an upper surface and a lower surface of the semiconductor structure 100 to form a source S and a drain D respectively as electrodes connecting the semiconductor structure 100 to the outside world. The metal layer M1 covers the first N-type semiconductor. The layer 11 and the first trench 12 have a Schottky junction at the junction of the metal layer M1 and the top of the first N-type semiconductor layer 11, and an electron accumulation (Accumulated electrons) region is formed in the first In the first N-type semiconductor layer 11 outside the insulating layer 15 or outside the first trench 12; wherein, the interface between the bottom surface of the first P-type protective layer 14 and the first N-type semiconductor layer 11 has a PN junction.

The first P-type protective layer 14 is disposed on the bottom surface of the first insulating layer 15 or the first trench 12, and the first P-type protective layer 14 does not cover the sidewalls of the first insulating layer 15 or the sidewalls of the first trench 12, The width of the first P-type protection layer 14 is less than or equal to the width of the bottom surface of the first trench 12. As a result, the forward current value is increased due to the increased Schottky junction spacing of the Schottky diode structure.

Next, please refer to FIG. 2 at the same time. FIG. 2 shows a partial schematic diagram of a semiconductor structure according to an embodiment of the present invention. The difference between the Schottky diode structure 20 and the Schottky diode structure 10 is that part of the Schottky diode structure 20 The N-type semiconductor layer 11 is an N-type current spreading layer (CSL). The N-type current spreading layer CSL is disposed outside the first trench 12 . The N-type current spreading layer CSL contacts the first insulating layer 15 and the first P-type Protective layer 14, and the top surface of the N-type current diffusion layer CSL is covered by the metal layer M1.

In one embodiment, the first current diffusion layer CSL has a higher N-type semiconductor doping concentration than the first N-type semiconductor layer 11, so that the Schottky diode structure 20 reduces its resistance value.

Next, please refer to FIG. 3. FIG. 3 shows a partial schematic of a semiconductor structure according to an embodiment of the present invention. FIG. 3 shows the structure of a trench gate power metal oxide semiconductor field-effect transistor (U-metal-oxide-semiconductor field- effect transistor (UMOS for short) 30. The UMOS structure 30 includes: metal layers M1 and M2, a first N-type semiconductor layer 11, a P-well (P-well) 35, a second N-type semiconductor layer 36, and a P-type semiconductor layer 37. , the second trench T, the second insulating layer I, the split gate 38, the gate 39, and the second P-type semiconductor protection layer 31.

Metal layers M1 and M2 are respectively disposed on the upper surface and bottom surface of the structure 30 to form a source S and a drain D respectively, which serve as electrodes connecting the structure 30 to the outside world; the first N-type semiconductor layer 11 is disposed on the drain D; The P-type well 35 is disposed on the first N-type semiconductor layer 11; the second N-type semiconductor layer 36 is disposed on the P-type well 35; the P-type semiconductor layer 37 is adjacent to the second N-type semiconductor layer 36 and is disposed on the P-type well 35. On the well 35 , the trench T extends downward through the second N-type semiconductor layer 36 , the P-type well 305 , and the first N-type semiconductor layer 11 , and finally the bottom of the trench T terminates at the first N-type semiconductor layer 11 .

Please note that in this embodiment, ions are implanted below the bottom of the trench T to form the second P-type protective layer 31, and the second P-type protective layer 31 is adjacent to the first N-type semiconductor layer 11. In this embodiment In this example, the bottom surface of the separation gate 38 is in contact with the upper edge or the upper bottom surface of the second P-type protective layer 31. The second P-type protective layer 31 is used to protect the second insulating layer I when the UMOS structure 30 is turned off and biased. Destroyed by breakdown electric field. In addition, the second P-type protective layer 31 and the separation gate 38 are grounded to prevent leakage current from the second P-type protection layer 31 and the separation gate 38 .

The second P-type protective layer 31 and the separation gate 38 are grounded. Since the second P-type protective layer 31 and the separation gate 38 are at the same potential, leakage current from the second P-type protection layer 31 and the separation gate 38 can be avoided.

The second insulating layer I is disposed within the second trench T and is adjacent to the second N-type semiconductor layer 36, the P-type well 35, the first N-type semiconductor layer 11, and the second P-type protective layer 31 respectively. The separation gate 38 is disposed in the second insulation layer I of the second trench T, and the gate 39 is disposed in the second insulation layer I of the second trench T and above the separation gate 38; wherein, the gate 39 The separation gate 38 is separated by a predetermined distance d by the second insulating layer I; and the bottom depth of the gate 39 is deeper than the interface between the P-type well 35 and the first N-type semiconductor layer 11 . In one embodiment, the gate 39 and the separation gate 38 can be regarded as being covered by the second insulating layer I. Among them, the second insulating layer I is a semiconductor oxide or a semiconductor nitride, and the separation gate 38 and the gate 39 are realized by polycrystalline silicon.

In one embodiment, the UMOS structure 30 is a structure of a UMOSFET used in silicon carbide. The second insulating layer I is disposed on the second P-type protective layer 31, and the bottom surface of the separation gate 38 is in contact with the second P-type protective layer 31. surface.

In one embodiment, the first P-type protective layer 14 or the second P-type protective layer 31 is made of at least one of silicon carbide (SiC), gallium nitride (GaN), and silicon.

Next, please refer to FIG. 4A at the same time. FIG. 4A shows a schematic diagram of the semiconductor structure 100 after the Schottky diode structure 10 and the UMOS structure 30 are combined. The upper polysilicon layer 13a is used as a gate, and the polysilicon layer 13a and the gate 39 in the UMOS structure 30 are coupled to each other. The upper metal layer M1 extends to cover the P-type semiconductor layer 37 and the second N-type semiconductor layer 36. The upper polysilicon layer 13a and the gate electrode 39 are located on the same level, and the lower polysilicon layer 13b and the separation gate 38 are located on the same level.

In this embodiment, the Schottky junction SJ is located at the interface between the metal layer M1 and the top of the first N-type semiconductor layer 11, as shown by the dotted line. In addition, the position of the electron accumulation area AE is shown by the thick line segment. Please note that the electron accumulation area AE of the UMOS structure 30 is generated below the second N-type semiconductor layer 36 and is approximately at the same level as the gate 39; Xiao Ji The electron accumulation region AE of the diode structure 10 is formed in the first N-type semiconductor layer 11 outside the first insulating layer 15 or outside the first trench 12. The position of the electron accumulation region AE is approximately the same as that of the upper polycrystalline silicon layer 13a. horizontal plane, but the electron accumulation area AE is not formed inside the first trench 12 .

Please note that the electron accumulation area AE is induced by applying a positive voltage to the polysilicon layer 13 a and the gate 39 . Therefore, the electron accumulation area AE is generated outside the first insulating layer 15 or outside the first trench 12 in the first N-type The formation of the electron accumulation layer AE in the semiconductor layer 11 and below the second N-type semiconductor layer 36 and on the same level as the gate 39 can improve the conductivity of the semiconductor structure 100 .

Next, please refer to FIG. 4B at the same time. FIG. 4A shows a schematic diagram of the semiconductor structure 100 after the Schottky diode structure 20 and the UMOS structure 30 are combined. In this embodiment, the difference between FIG. 4B and FIG. 4A is that part of the N-type semiconductor layer 11 in the Schottky diode structure 20 is an N-type current diffusion layer CSL. The remaining principles are the same as mentioned above.

FIG. 5 shows a partial schematic diagram of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure 100 includes a Schottky diode structure 50 , and the Schottky diode structure 50 further includes a first N-type semiconductor layer 11 and a first trench 12 , polycrystalline silicon layers 13a and 13b, the first P-type protective layer 14, the first insulating layer 15, and the metal layers M1 and M2.

Please note that in this embodiment, the polycrystalline silicon layer 13a and the polycrystalline silicon layer 13b are closely integrated, and there is no gap between the polycrystalline silicon layer 13a and the polycrystalline silicon layer 13a. In other words, the Schottky diode structure 50 is in the first trench. 12 can be regarded as having only one polycrystalline silicon layer 13 .

In addition, the metal layer M1 above the first trench 12 extends into the first trench 12, and the metal layer M1 in the first trench 12 contacts the upper polycrystalline silicon layer 13a (or polycrystalline silicon layer 13). surface and the first insulating layer 15 .

In one embodiment, the sidewall W of the metal layer M1 in the first trench 12 and the bottom of the metal layer M1 above the first N-type semiconductor layer 11 form an L shape. In this way, the Schottky diode structure 50 Compared with the Schottky diode structure 10, the metal content of the metal layer M1 is increased, so the current spreading ability is also increased.

Next, please refer to FIG. 6 at the same time. FIG. 6 shows a partial schematic diagram of a semiconductor structure according to an embodiment of the present invention. The difference between the Schottky diode structure 60 and the Schottky diode structure 50 is that part of the Schottky diode structure 60 The N-type semiconductor layer 11 is an N-type current spreading layer (CSL). The N-type current spreading layer CSL is disposed outside the first trench 12 . The N-type current spreading layer CSL contacts the first insulating layer 15 and the first P-type Protective layer 14, and the top surface of the N-type current diffusion layer CSL is covered by the metal layer M1 and contacts the sidewall W of the metal layer M1.

In one embodiment, the adjacent Schottky junction SJ of the Schottky diode structure 50 has an included angle, and the included angle is close to 90 degrees; in other words, the adjacent Schottky junction SJ of the Schottky diode structure 50 SJ presents a step shape, and there is a Schottky junction SJ at the junction between the top of the metal layer M1 and the first N-type semiconductor layer 11 and the sidewall W. Therefore, the Schottky diode structure 60 and the Schottky diode structure 50 are improved The area of the Schottky junction SJ is determined, and the position of the Schottky junction SJ is shown in Figure 7A and Figure 7B.

Next, please refer to FIG. 7A at the same time. FIG. 7A shows a schematic diagram of the semiconductor structure 100 after the Schottky diode structure 50 and the UMOS structure 30 are combined. The metal layer M1 is as shown in Figure 5. The metal layer M1 extends into the first trench 12, and the metal layer M1 in the first trench 12 contacts the upper surface of the polycrystalline silicon layer 13. The polycrystalline silicon layer 13 is separated from the gate electrode. 38 are located on the same horizontal plane; in this embodiment, the Schottky diode structure 50 has no gate.

In this embodiment, the location of the Schottky junction SJ is at the junction between the top of the metal layer M1 and the first N-type semiconductor layer 11, and at the junction between the sidewall W of the metal layer M1 and the first N-type semiconductor layer 11, such as Shown in dashed box. In addition, the position of the electron accumulation area AE is shown by the thick line segment. Please note that the electron accumulation area AE of the UMOS structure 30 is generated below the second N-type semiconductor layer 36 and is approximately at the same level as the gate 39 .

Please note that the electron accumulation area AE is induced by applying a positive voltage to the gate 39 . Therefore, the electron accumulation area AE is generated below the second N-type semiconductor layer 36 and is approximately at the same level as the gate 39 .

Next, please refer to FIG. 7B at the same time. FIG. 7B shows a schematic diagram of the semiconductor structure 100 after the Schottky diode structure 60 and the UMOS structure 30 are combined. In this embodiment, the difference between FIGS. 7B and 7A is that part of the N-type semiconductor layer 11 in the Schottky diode structure 20 is an N-type current diffusion layer CSL, and the remaining principles are the same as mentioned above.

To sum up, the semiconductor structure of the present invention provides the following functions: 1. Schottky junction of the Schottky diode structure; 2. Grounding the P-type protective layer to the top metal or electrode; 3. Embedded PN (Embedded PN) has better surge current capability.

100:Semiconductor Structure 10, 20, 50, 60: Schottky diode structure 30:UMOS structure M1, M2: metal layer S: source D: drain 11: First N-type semiconductor layer 13, 13a, 13b: polycrystalline silicon layer 35:P type well 36: Second N-type semiconductor layer 37:P-type semiconductor layer 38: Separate gate 39: Gate AE: electronic accumulation area SJ: Xiao Ji’s interview W: side wall 31, 14: P-type protective layer CSL: current spreading layer 12. T: groove I, 15: Insulating layer d:Default spacing

[Figures 1 to 3] show partial schematic diagrams of a semiconductor structure according to an embodiment of the present invention. [ FIG. 4A ] shows a schematic diagram of the semiconductor structure 100 after combining the Schottky diode structure 10 and the UMOS structure 30 . [FIG. 4B] shows a schematic diagram of the semiconductor structure 100 after combining the Schottky diode structure 20 and the UMOS structure 30. [Figures 5~6] show a partial schematic diagram of a semiconductor structure according to an embodiment of the present invention. [FIG. 7A] shows a schematic diagram of the semiconductor structure 100 after combining the Schottky diode structure 50 and the UMOS structure 30. [FIG. 7B] shows a schematic diagram of the semiconductor structure 100 after combining the Schottky diode structure 60 and the UMOS structure 30.

100:Semiconductor Structure

10: Schottky diode structure

30:UMOS structure

M1, M2: metal layer

S: source

D: drain

11: First N-type semiconductor layer

12:First groove

13a, 13b: polycrystalline silicon layer

15: First insulation layer

35:P type well

36: Second N-type semiconductor layer

37:P-type semiconductor layer

39: Gate

AE: electronic accumulation area

SJ: Xiao Ji’s interview

Claims (13)

A semiconductor structure containing: A Schottky diode structure, the Schottky diode structure includes: a first N-type semiconductor layer; a first trench extending through the first N-type semiconductor layer and disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; At least two polycrystalline silicon layers are arranged in the first trench, the upper polycrystalline silicon layer and the lower polycrystalline silicon layer are arranged in parallel, and the first insulating layer is located in the first trench; A first P-type protective layer for grounding and disposed at the bottom of the first trench, and the first P-type protective layer contacts the bottom surface of the first insulating layer and the underlying polycrystalline silicon layer; and A metal layer is respectively disposed on an upper surface and a lower surface of the semiconductor structure to form a source and a drain respectively as electrodes for connecting the semiconductor structure to the outside world. The metal layer covers the first trench. , and have a Xiao base junction at the interface between the metal layer and the top of the first N-type semiconductor layer; Wherein, the interface between the bottom surface of the first P-type protective layer and the first N-type semiconductor layer has a PN junction. The semiconductor structure of claim 1, wherein the first P-type protective layer is disposed on the first insulating layer or the bottom surface of the first trench, and the first P-type protective layer does not cover the first insulating layer. The sidewall of the layer or the sidewall of the first trench, and the width of the first P-type protective layer is less than or equal to the width of the bottom surface of the first trench. The semiconductor structure of claim 2, wherein the two polycrystalline silicon layers in the Schottky diode structure are covered by the first insulating layer, and there is no contact between the two polycrystalline silicon layers; an electron accumulation region is formed Outside the first insulating layer, the electron accumulation region is substantially at the same level as the upper polycrystalline silicon layer, and the metal layer contacts the first N-type semiconductor layer and the upper surface of the first insulating layer in the first trench. . The semiconductor structure as described in claim 3, wherein the semiconductor structure includes: The structure of a trench gate power metal oxide semi-field effect transistor (UMOS). The first N-type semiconductor layer is disposed on the drain. The UMOS structure includes: A P-type well is provided on the first N-type semiconductor layer; a second N-type semiconductor layer disposed on the P-type well; a P-type semiconductor layer adjacent to the second N-type semiconductor layer and disposed on the P-type well; a second trench extending through the second N-type semiconductor layer, the P-type well and the first N-type semiconductor layer, the bottom of the second trench terminating at the first N-type semiconductor layer; a second insulating layer disposed in the second trench; A separation gate is disposed in the second insulation layer of the second trench, and the separation gate is covered by the second insulation layer; a gate disposed in the second insulating layer of the trench and above the separation gate; and A second P-type protective layer is provided at the bottom of the second trench and adjacent to the first N-type semiconductor layer, and the second insulating layer is provided on the second P-type protective layer for When the structure is turned off and biased, the second insulating layer is protected from breakdown by the electric field; Wherein, the gate and the separation gate are separated by a predetermined distance by the second insulating layer; and the bottom depth of the gate is deeper than the gap between the P-type well and the N-type current diffusion layer. Interface; the bottom surface of the separation gate is in contact with the upper surface of the second P-type protective layer. The semiconductor structure of claim 4, wherein part of the first N-type semiconductor layer is an N-type current spreading layer (CSL), and the N-type current spreading layer is disposed outside the first trench or Outside the second trench, the N-type current diffusion layer contacts the first insulating layer and the first P-type protective layer, and the top surface of the second N-type current diffusion layer is covered by the metal layer. The semiconductor structure of claim 5, wherein the upper metal layer extends to cover the P-type semiconductor layer and the second N-type semiconductor layer, the upper polysilicon layer and the gate are located on the same level, and the lower layer The polycrystalline silicon layer is on the same level as the separation gate. The semiconductor structure of claim 1, wherein the two polycrystalline silicon layers are closely integrated and there is no gap between the two polycrystalline silicon layers; the metal layer above the first trench extends into the third trench. In a trench, the metal layer in the first trench contacts the upper surface of the polycrystalline silicon layer of the upper layer and the first insulating layer. The semiconductor structure of claim 7, wherein the sidewalls of the metal layer in the first trench and the bottom of the metal layer above the first N-type semiconductor layer form an L shape. The semiconductor structure as claimed in claim 7, wherein the adjacent Schottky junctions of the Schottky diode structure have an included angle. The semiconductor structure according to claim 9, wherein the adjacent Schottky junction of the Schottky diode structure presents a step shape. The semiconductor structure of claim 10, wherein the Schottky junction is formed at the junction between the metal layer and the top and sidewalls of the first N-type semiconductor layer. The semiconductor structure as claimed in claim 11, wherein the semiconductor structure includes: The structure of a trench gate power metal oxide semi-field effect transistor. The first N-type semiconductor layer is disposed on the drain. The UMOS structure includes: A P-type well is provided on the first N-type semiconductor layer; a second N-type semiconductor layer disposed on the P-type well; a P-type semiconductor layer adjacent to the second N-type semiconductor layer and disposed on the P-type well; a second trench extending through the second N-type semiconductor layer, the P-type well and the first N-type semiconductor layer, the bottom of the second trench terminating at the first N-type semiconductor layer; a second insulating layer disposed in the second trench; A separation gate is disposed in the second insulation layer of the second trench, and the separation gate is covered by the second insulation layer; a gate disposed in the second insulating layer of the trench and above the separation gate; and A second P-type protective layer is provided at the bottom of the second trench and adjacent to the first N-type semiconductor layer, and the second insulating layer is provided on the second P-type protective layer for When the structure is turned off and biased, the second insulating layer is protected from breakdown by the electric field; Wherein, the gate and the separation gate are separated by a predetermined distance by the second insulating layer; and the bottom depth of the gate is deeper than the P-type well and the first N-type semiconductor layer The interface; the bottom surface of the separation gate is in contact with the upper surface of the second P-type protective layer. The semiconductor structure as claimed in claim 4 or 12, wherein the first P-type protective layer or the second P-type protective layer is made of at least one of silicon carbide, gallium nitride, and silicon.

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