TWI823639B - Semiconductor device and methods for forming the same - Google Patents

Abstract

A semiconductor device includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a well region extending from a top surface of the epitaxial layer into the epitaxial layer, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductive type, the well region has the second conductive type, and the drift region has the first conductive type. The gate structure that extends from the top surface of the epitaxial layer penetrates the well region and is in contact with the drift region. The conductive structure is formed in the drift region and disposed below the gate structure. A gate electrode of the gate structure is separated from the undelying conductive structure by a gate dielectric layer of the gate structure.

Description

Semiconductor device and method of forming same

The present invention relates to a semiconductor device and a method of forming the same, and in particular to a semiconductor device having a Schottky diode and a method of forming the same.

The semiconductor industry continues to improve the integration density of different electronic components by continuing to reduce the minimum component size, allowing more components to be integrated in a given area. For example, the trench gate metal-oxide-semiconductor field effect transistor (MOSFET), which is widely used in power switch components, uses a vertical structure design to reduce the cost. The cell pitch (cell pitch) is used to increase functional density. It uses the back side of the chip as the drain, and makes the sources and gates of multiple transistors on the front side of the chip. Therefore, the driving current develops from the flow in the plane direction to the vertical direction. The flow can also enable the semiconductor device to achieve high reverse withstand voltage and low on-resistance.

However, as the functional density requirements for semiconductor devices continue to increase, the complexity of the components integrated in the semiconductor devices and their formation methods also increases, and there are some performance trade-off electronic characteristics that need to be considered. Therefore, while existing semiconductor devices are generally suitable and sufficient for their intended purposes, they are not entirely satisfactory in all respects.

Some embodiments of the present disclosure provide a semiconductor device, including a substrate having a first conductivity type, an epitaxial layer formed on the substrate, and a well extending from a top surface of the epitaxial layer into the epitaxial layer. region, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductivity type, the well region has a second conductivity type, and the drift region has the first conductivity type. The gate structure extends from the top surface of the epitaxial layer through the well region and contacts the drift region. The conductive structure is formed in the drift region and is located below the gate structure, wherein a gate dielectric layer of the gate structure separates the conductive structure and a gate electrode of the gate structure.

Some embodiments of the present disclosure provide a method for forming a semiconductor device, including providing a substrate with a first conductivity type; forming an epitaxial layer with the first conductivity type on the substrate; The surface is doped to form a well region in the epitaxial layer, and the well region has a second conductivity type, wherein below the well region is a drift region, the drift region has the first conductivity type and is connected to The bottom surface of the aforementioned well region is in contact; a plurality of conductive structures are formed in the aforementioned drift region; gate structures are respectively formed above the aforementioned conductive structures, wherein the aforementioned gate electrode structures extend from the aforementioned top surface of the aforementioned epitaxial layer through the aforementioned wells region, the bottom portions of the gate structures are located in the aforementioned drift region, and the aforementioned gate structures each include a gate dielectric layer covering a gate electrode. Wherein, the gate dielectric layer separates the corresponding conductive structure and the gate structure.

The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor devices. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements. , so that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numbers and/or letters in different examples. This repetition is for the sake of brevity and clarity and is not intended to indicate the relationship between the various embodiments discussed.

Furthermore, spatially related expressions may be used in the following descriptions, such as "under", "under", "below", "above", "above" and other similar terms A term used to simplify the statement of the relationship between one element or component and other elements or other components as shown in the figure. Such spatially relative terms include, in addition to the directions depicted in the drawings, various orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Some variations of the embodiments are described below. Similar reference numbers are used to identify similar elements in the various drawings and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, and after the method, and some of the recited steps may be replaced or deleted for other embodiments of the method.

Embodiments of the present disclosure provide a semiconductor device and a method for forming the same, which can produce a semiconductor device including a Schottky diode so as to disable the body diode and thereby reduce the energy consumption of the body diode. On-resistance and power loss are reduced, and the switching characteristics of semiconductor devices are improved. Moreover, the embodiment proposes to arrange the conductive structure that can form the Schottky diode under the gate structure, which can not only reduce the gate-drain capacitance (Cgd), but also does not require additional mesa (mesa) of the epitaxial layer. ) area. In other words, there is no need to provide additional lateral space on the surface of the epitaxial layer to form a Schottky diode. Therefore, the semiconductor device proposed in the embodiment can reduce the cell pitch between adjacent units in the device, such as two adjacent units. The spacing of the gate structure thereby reduces the channel area resistance. The contents of the embodiments may be applied to metal-oxide-semiconductor (MOS) devices, such as metal-oxide-semiconductor field effect transistors (MOSFET). In some of the following embodiments, a trench gate metal oxide semiconductor field effect transistor (trench gate MOSFET) is used as an example of a semiconductor structure.

1 to 18 are schematic cross-sectional views of a semiconductor device including a gate structure and a conductive structure at various intermediate manufacturing stages according to some embodiments of the present disclosure. The conductive structure is formed under the gate structure, and each conductive structure is electrically connected to the source electrode in the subsequent process to form a Schottky diode integrally with the drift region, so that the base diode is lost. can, thereby reducing on-resistance and power loss.

Referring to FIG. 1 , according to some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 can be a piece of semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, or the substrate 100 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, substrate 100 may include a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 100 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 100 may also include a silicon on insulator (SOI) or other suitable substrate. The SOI substrate can be formed using an oxygen implant isolation (SIMOX) process, a wafer bonding process, other applicable methods, or a combination of the foregoing. In some embodiments, the substrate 100 may be composed of different semiconductor materials, such as silicon, silicon germanium, silicon carbide, etc. In this example, the substrate 100 is, for example, a silicon wafer doped with a dopant of the first conductivity type. In the application of a vertical trench-gate metal oxide semiconductor field effect transistor (vertical trench-gate MOSFET), the substrate 100 having the first conductivity type can be used as a drain region of the semiconductor device. Furthermore, in this example, the first conductivity type is n-type, but the present disclosure is not limited thereto. In some other examples, the first conductivity type may also be p-type.

In some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on the substrate 100 . During the epitaxial process, for example, the epitaxial layer 102 is formed by growing in the first direction D1 (eg, the Z direction). In this example, the epitaxial layer 102 is formed in two stages to form a doped region inside the epitaxial layer 102 . These doped regions can serve as shielding regions for subsequently formed conductive structures.

Referring to FIG. 1 , according to some embodiments, an epitaxial growth process is performed on the top surface 100 a of the substrate 100 to form a first epitaxial portion 1021 of the epitaxial layer 102 . Thereafter, implantation is performed in the first epitaxial portion 1021 of the epitaxial layer 102 to form doped regions 104 (eg, 1041 and 1042). In an example, the doping region 1041 and the doping region 1042 are separated from each other by a distance in the second direction D2 (for example, the X direction). Furthermore, the doped regions 1041 and 1042 may be (but are not limited to) adjacent to the top surface 1021a of the first epitaxial portion 1021 of the epitaxial layer 102 . The formation of the doped regions 1041 and 1042 in the appropriate depth of the first epitaxial portion 1021 of the epitaxial layer 102 can be controlled by adjusting the implantation energy or other appropriate methods.

In some embodiments, the substrate 100 and the first epitaxial portion 1021 of the epitaxial layer 102 have the same conductivity type, such as a first conductivity type. In this example, the substrate 100 and the first epitaxial portion 1021 of the epitaxial layer 102 are n-type. Furthermore, the doping concentration of the first epitaxial portion 1021 of the epitaxial layer 102 is smaller than the doping concentration of the substrate 100 .

In some embodiments, the doped regions 1041 and 1042 have a different conductivity type than the epitaxial layer 102, such as a second conductivity type. In this example, doped regions 1041 and 1042 are p-type. In some embodiments, the dopant of the doped region 1041 and the doped region 1042 may be aluminum (Al), or other suitable dopants. In some embodiments, the doping concentration of the doped regions 1041 and 1042 ranges from about 1E16 atoms/cm ³ to about 1E18 atoms/cm ³ .

2, according to some embodiments, epitaxial growth continues on the top surface 1021a of the first epitaxial portion 1021 toward the first direction D1 (eg, the Z direction) to form the second epitaxial portion 1022. The second epitaxial portion 1022 also has a first conductivity type, such as n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together form an epitaxial layer 102 .

In some embodiments, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) can be used. ), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods or a combination of the aforementioned methods to perform the above epitaxy growth process to form epitaxial crystals Layer 102. In the application of a semiconductor device such as a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET), after completing the fabrication of the transistor, the epitaxial layer 102 has a first conductivity type (eg, n-type). It can be used as the drift region of a semiconductor device.

Referring to FIG. 3 , according to some embodiments, a well region 106 is formed in the epitaxial layer 102 , and the well region 106 has a conductivity type different from that of the epitaxial layer 102 , such as a second conductivity type. In this example, well region 106 is p-type (also called a p-body region). The well region 106, the doped region 1041 and the doped region 1042 have the same conductivity type. In some embodiments, the doping concentration of well region 106 is less than the doping concentrations of doping regions 1041 and 1042 . In some embodiments, the doping concentration of well region 106 ranges from about 1E16 atoms/cm ³ to about 1E18 atoms/cm ³ . According to some embodiments, the well region 106 may serve as a channel region of a semiconductor device.

In some embodiments, the well region 106 may be formed in the epitaxial layer 102 through, for example, an ion implantation process IP-1. In one example, doping may be performed from the top surface 102 a of the epitaxial layer 102 to form a well region 106 in the epitaxial layer 102 . Therefore, the well region 106 is doped from the top surface 102 a of the epitaxial layer 102 downward to a specific depth of the epitaxial layer 102 . The well region 106 is a doped region extending in the first direction D1, the second direction D2, and the third direction D3. Furthermore, the epitaxial portion under the well region 106 is a drift region _RD . The drift region _RD has a first conductivity type (for example, n-type), and the drift region _RD contacts the well region. The bottom surface 106b of 106, as shown in Figure 3.

According to some embodiments, the above-mentioned well region 106 can be formed through a deposition process, a photolithographic patterning process, an etching process, and an implantation process. For example, in one example, an oxide hardmask material layer (not shown) may be deposited over the top surface 102a (FIG. 2) of the epitaxial layer 102, and then the oxide hardmask material layer may be A patterned photoresist (patterned PR) corresponding to the position of the well region 106 is formed on the mask material layer. The oxide hard mask material layer is etched according to the patterned photoresist to form an oxide hard mask. The patterned PR is removed. The epitaxial layer 102 is doped according to the formed oxide hard mask to form a well region 106 in the epitaxial layer 102, and then the oxide hard mask is removed.

Next, according to some embodiments, as shown in Figures 4 to 6, first heavily doped portions 1110 and second heavily doped portions 1120 of different conductivity types are alternately formed in the well region 106. heavily doped portions). The formation method of the first heavily doped portion 1110 and the second heavily doped portion 1120 is, for example, similar to the formation method of the well region 106 .

Referring to FIG. 4 , according to some embodiments, for example, the top surface 106 a of the well region 106 (ie, the top surface 102 a of the epitaxial layer 102 ) is doped in the well region 106 to form a plurality of first first elements in the well region 106 . Heavily doped portion 1110. And the first heavily doped portions 1110 are arranged apart (for example, in the second direction D2). In one example, the first heavily doped portions 1110 have the same second conductivity type as the well region 106 , such as p-type. In some embodiments, the doping concentration of the first heavily doped portion 1110 is greater than the doping concentration of the well region 106 . In some embodiments, the doping concentration of the first heavily doped portion 1110 ranges from about 1E18 atoms/cm ³ to about 1E21 atoms/cm ³ .

According to some embodiments, the above-mentioned first heavily doped portion 1110 can be formed through a deposition process, a photolithographic patterning process, an etching process, and an implantation process. In one example, a hardmask material layer (not shown) (eg, an oxide hardmask material layer) may be deposited over top surface 106a of well region 106 and then the hardmask material layer A patterned photoresist (not shown) is formed on the layer, and the hard mask material layer is etched according to the patterned photoresist to form a patterned hard mask 108 (eg, an oxide hard mask). The plurality of openings 108H of the patterned hard mask 108 correspond to the locations of the first heavily doped portions 1110 to be formed. Afterwards, the patterned photoresist is removed, leaving the patterned hard mask 108, as shown in Figure 4. An ion implantation process IP-2 is performed on the well region 106 according to the formed patterned hard mask 108 to form the first heavily doped portion 1110 in the well region 106 . Therefore, the first heavily doped portion 1110 extends downwardly from the top surface 106a of the well region 106 (ie, the top surface 102a of the epitaxial layer 102) into the well region 106. Afterwards, the patterned hard mask 108 is removed.

Referring to FIG. 5 , according to some embodiments, for example, top surface 106 a of well region 106 (ie, top surface 102 a of epitaxial layer 102 ) is doped in well region 106 to form a plurality of second Heavily doped portion 1120. And these second heavily doped portions 1120 are arranged apart (for example, in the second direction D2). In one example, the second heavily doped portions 1120 have the same first conductivity type as the epitaxial layer 102 , such as n-type. In some embodiments, the doping concentration of the second heavily doped portion 1120 is greater than the doping concentration of the epitaxial layer 102 . In some embodiments, the doping concentration of the second heavily doped portion 1120 ranges from about 1E18 atoms/cm ³ to about 1E21 atoms/cm ³ .

According to some embodiments, the above-mentioned second heavily doped portion 1120 can be formed through a deposition process, a photolithographic patterning process, an etching process, and an implantation process. In one example, another hardmask material layer (not shown) (eg, an oxide hardmask material layer) may be deposited over top surface 106a of well region 106 and then hardmask Another patterned photoresist (not shown) is formed on the material layer, and the hard mask material layer is etched according to the patterned photoresist to form a patterned hard mask 109 (eg, an oxide hard mask). The plurality of openings 109H of the patterned hard mask 109 correspond to the locations of the second heavily doped portions 1120 to be formed. Afterwards, the patterned photoresist is removed, leaving the patterned hard mask 109, as shown in Figure 5. An ion implantation process IP-3 is performed on the well region 106 according to the formed patterned hard mask 109 to form the second heavily doped portion 1120 in the well region 106 . Therefore, the second heavily doped portion 1120 extends downwardly from the top surface 106a of the well region 106 (ie, the top surface 102a of the epitaxial layer 102) into the well region 106. Afterwards, the patterned hard mask 109 is removed.

Referring to Figure 6, according to some embodiments, after removing the patterned hard mask 109 (Figure 5), a high temperature activation process can be used to activate the first heavily doped portion 1110 and the second heavily doped portion. Dopants in part 1120. As shown in FIG. 6 , the first heavily doped portions 1110 and the second heavily doped portions 1120 are alternately provided at the top surface 106a of the well region 106 (ie, the top surface 102a of the epitaxial layer 102).

Furthermore, in some embodiments in which the epitaxial layer 102 includes silicon carbide (SiC), a high-temperature activation process may be performed after covering the top surface 102 a of the epitaxial layer 102 with a graphite cap (not shown). The graphite layer can protect the silicon carbide surface from out-diffusion of Si during the high-temperature activation process. After completing the high-temperature activation process, the graphite layer is removed.

7 , according to some embodiments, portions of the first heavily doped portion 1110 , portions of the second heavily doped portion 1120 , portions of the well region 106 and portions of the epitaxial layer 102 are removed to form a plurality of First trench 121. In some embodiments, the positions of these first trenches 121 correspond to positions of shielding regions 104' that can later serve as subsequently formed conductive structures, such as the first trench 121-1 and the first trench 121-1. The positions of the grooves 121-2 respectively correspond to the doped regions 1041 and 1042 having the second conductivity type (eg, p-type) below.

In some embodiments, the first trenches 121, such as the two first trenches 121-1 and 121-2 disposed apart in FIG. 7, extend from the top surface 102a of the epitaxial layer 102 through the wells. area 106, and reaches the drift area _RD , where the lower portion of the side surface 121s and the bottom surface 121b of the first trench 121 expose the drift area _RD .

Furthermore, after the first trench 121 is formed, the remaining portion of the first heavily doped portion 1110 becomes the first heavily doped region 111, which allows the subsequent contact plug 172 to be formed above the first heavily doped region 111 ( Figure 20) has good ohmic contact with the well area 106. The remaining portion of the second heavily doped portion 1120 becomes the second heavily doped region 112, which can later be used as source regions. The first heavily doped region 111 has a second conductivity type, such as p-type. The second heavily doped region 112 has a first conductivity type, such as n-type. In some embodiments, as shown in FIG. 7 , opposite sides of each first trench 121 contact one of the first heavily doped regions 111 and one of the second heavily doped regions 112 respectively. The upper portion of the side surface 121s of the first trench 121 exposes the well region 106, the first heavily doped region 111 and the second heavily doped region 112.

According to some embodiments, the above-mentioned first trench 121 can be formed through a deposition process, a photolithographic patterning process, and an etching process. In one example, a pad oxide material layer (not shown) and a nitride hard mask material may be deposited over the first heavily doped portion 1110 and the second heavily doped portion 1120 A nitride hardmask material layer (not shown) is formed, and a patterned photoresist layer 117 is formed on the nitride hardmask material layer. The arrangement of the liner oxide material layer can avoid excessive stress caused by direct contact between the nitride hard mask material layer and the epitaxial layer (for example, containing silicon carbide). Then, according to the patterned photoresist layer 117, the nitride hard mask material layer, the pad oxide material layer and the heavily doped part below (including part of the first heavily doped part 1110, part of the second heavily doped part portion 1120) and the well region 106 are sequentially etched, and a portion of the drift region _RD is removed to form the above-mentioned first trench 121. In some embodiments, the etching process includes a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes. In addition, it can be understood that the size, shape, and position of the first groove 121 are only for illustrative purposes and are not intended to limit the embodiments of the present invention.

In some embodiments, after forming the first trench 121, the patterned photoresist layer 117 is removed, leaving the pad oxide layer 114 and nitrogen above the first heavily doped region 111 and the second heavily doped region 112. Chemical hard mask 116. And a cleaning process is performed on the structure.

8, according to some embodiments, an insulating layer 123 is formed on the side surface 121s and the bottom surface 121b of the first trench 121. In some embodiments, the insulating layer 123 may be silicon oxide, or other suitable semiconductor oxide materials, or a combination of the foregoing materials. In some examples, the insulating layer 123 may be conformably formed on the side surface 121s and the bottom surface 121b of the insulating layer 123 through an oxidation process. In some embodiments, the oxidation process may be thermal oxidation, radical oxidation, or other suitable processes. In an example in which the epitaxial layer 102 includes silicon carbide (SiC), the silicon carbide on the side surface 121s and the bottom surface 121b of the first trench 121 is oxidized through a high-temperature process (for example, using a high-temperature furnace tube) to form silicon oxide. , as the insulating layer 123.

After that, the conductive structure 130 (FIG. 14) is fabricated below the first trench 121. According to some embodiments of the present disclosure, some intermediate stages of fabricating the conductive structure 130 are, for example, but not limited to, as shown in Figures 9-14.

Referring to FIG. 9 , according to some embodiments, a spacer layer 124 is formed in the first trench 121 . In some embodiments, a deposition process may be performed on the top and side surfaces of the nitride hard mask 116 , the side surfaces of the pad oxide layer 114 , and the insulating layer 123 in the first trench 121 . The spacer layer 124 is deposited. In this example, the spacer layer 124 may cover all exposed surfaces of the insulating layer 123 in the first trench 121 . The spacer layer 124 also reduces the width of the first trench 121 in the second direction D2 (eg, X direction).

In some embodiments, spacer layer 124 includes silicon nitride, silicon oxynitride, other suitable spacer materials, or combinations of the foregoing materials. The material of the spacer layer 124 may be the same as the material of the nitride hard mask 116 , or may be different from the material of the nitride hard mask 116 . In this example, spacer layer 124 and nitride hard mask 116 include silicon nitride. Furthermore, the deposition process of the spacer layer 124 is, for example, a conformal deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or atomic layer deposition (ALD). ALD) process, other suitable deposition processes, or a combination of the foregoing processes.

Referring to FIG. 10 , according to some embodiments, a portion of the spacer layer 124 and a portion of the insulating layer 123 may be removed through an etching process to expose the epitaxial material of the drift region _RD . This etching process is an anisotropic etching process, which allows the first trench 121 to continue extending toward the direction of the substrate 100 , for example, along the first direction D1 (eg, the Z direction). Specifically, for the material layer to be etched, the aforementioned etching process etches in the first direction D1, but does not substantially etch in the second direction D2.

In some embodiments, the above-mentioned etching process includes a blanket etching process, without using any photoresist, to etch the spacers along the sidewalls 124s of the spacer layer 124 in the first trench 121. The bottom of the layer 124 and the bottom of the insulating layer 123 are anisotropically etched to remove part of the spacer layer 124 and part of the insulating layer 123, and the epitaxial layer 102 (the epitaxial material layer of the drift region _RD ) is An etch stop layer for this blanket etching process. In this example, the blanket etching process is a dry etching process.

Furthermore, in this example, the nitride hard mask 116 left above the pad oxide layer 114 can block the aforementioned blanket etching process to prevent the anisotropic etching along the first direction D1 from damaging the pad. The pad oxide layer 114 and the first heavily doped region 111 and the second heavily doped region 112 below.

Referring to Figure 11, according to some embodiments, a portion of the epitaxial layer 102 (the epitaxial material layer of the drift region _RD ), a portion of the doped region 1041 and a portion of the doped region are removed from the bottom surface of the extended first trench 121. The impurity region 1042 is formed to form a plurality of second trenches 126. The second trenches 126 are connected to the corresponding first trenches 121 respectively, and the bottom surfaces 126b of the second trenches 126 stop in the doped regions 1041 and 1042 . Furthermore, in some embodiments, the side surfaces 126s of the second trench 126 are self-aligned with the sidewalls 124s of the spacer layer 124 in the first trench 121.

Specifically, in this example, the position of the second trench 126-1 is, for example, to continue the first trench 121-1 to extend in the epitaxial layer 102, and remove part of the doped region 1041, so that the second trench 126-1 is Bottom surface 126b of trench 126-1 stops in doped region 1041. After the second trench 126-1 is formed, the remaining portion of the doped region 1041 can be used as a shielding region 1041' for the subsequently formed conductive structure 130 (FIG. 14). Similarly, the position of the second trench 126-2 is, for example, to continue the first trench 121-2 to extend in the epitaxial layer 102, and remove part of the doped region 1042, so that the bottom of the second trench 126-2 Surface 126b stops in doped region 1042. After the second trench 126-2 is formed, the remaining portion of the doped region 1042 can be used as a shielding region 1042' for the subsequently formed conductive structure 130 (FIG. 14).

In some embodiments, these second trenches 126, such as the two second trenches 126-1 and 126-2 disposed apart in FIG. 11, are connected to the first trench 121 in the epitaxial layer 102. Extend and reach the shielding area 1041' and the shielding area 1042'. In other words, in this example, the upper portion of the side surface 126s of the second trench 126-1 exposes the drift region _RD , and the lower portion of the side surface 126s and the bottom surface 126b of the second trench 126-1 expose the shielding Area 1041'. The upper portion of the side surface 126s of the second trench 126-2 exposes the drift region _RD , and the lower portion of the side surface 126s and the bottom surface 126b of the second trench 126-2 exposes the shielding area 1042'.

In some embodiments, a suitable etching process may be used to remove part of the epitaxial layer 102 (the epitaxial material layer of the drift region _RD ), part of the doped region 1041 and part of the doped region 1042 to form a second Groove 126. The aforementioned etching process includes a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes. In addition, it can be understood that the size, shape, and position of the second groove 126 are only for illustrative purposes and are not intended to limit the embodiments of the present invention.

After the second trench 126 is formed, the spacer layer 124 and the nitride hard mask 116 are removed, thereby exposing the pad oxide layer 114 above the first and second heavily doped regions 111 and 112 and the pad oxide layer 114 and the nitride hard mask 116 . The remaining portion of the insulating layer 123 in the first trench 121 . In some embodiments, the spacer layer 124 and the nitride hard mask 116 are formed by, for example, an isotropic etch process, a wet etching process (such as acid etching), or other acceptable processes. Remove.

Furthermore, in some embodiments, after the spacer layer 124 and the nitride hard mask 116 are removed, the width W1 of each first trench 121 (eg, the width in the second direction D2) is larger than that of each second trench. The width of the groove 126 (eg, the width in the second direction D2) W2.

According to the above, the formed second trench 126 will be filled with a suitable conductive material in subsequent processes to form the conductive structure 130 .

Referring to FIG. 12, according to some embodiments, a metal silicide liner 131 is formed on the side surface 126s and the bottom surface 126b of each second trench 126. In some embodiments, the metal silicide liner 131 in each second trench 126 is connected to the epitaxial layer 102 (the epitaxial material layer of the drift region _RD ) and the shielding area (eg, the shielding area 1041' or the shielding area 1042 ') direct contact.

In an example in which the epitaxial layer 102 includes silicon carbide (SiC), the metal silicide lining layer 131 includes, for example, metal silicide produced by reacting a metal material that can react with silicon carbide. In some embodiments, the silicide liner 131 includes titanium silicide (TiSi ₂ ), nickel silicide (NiSi), platinum silicide (PtSi), or other suitable silicide materials.

According to some embodiments, the epitaxial layer 102 includes silicon carbide (SiC), and a metal material layer that can react with silicon carbide can be deposited on the entire surface first. This metal material layer is, for example, conformally deposited on the pad oxide layer 114, The remaining portion of the insulating layer 123 in the first trench 121 and above the side surface 126s and the bottom surface 126b of the second trench 126. In some embodiments, the metal material can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the foregoing processes. layer. Then, for example, through rapid thermal processing (RTP), the metal material layer deposited in the second trench 126 can react with silicon carbide (SiC) to form silicidation, such as silicide. Titanium, nickel silicide, platinum silicide or other metal silicides. The metal material layer deposited on the remaining portion of the pad oxide layer 114 and the insulating layer (for example, including oxide) 123 does not react with the pad oxide layer 114 and the insulating layer 123 and remains a metal material layer. Thereafter, the unreacted metal material layer is removed (for example, using a suitable acid etchant) to expose the pad oxide layer 114 and the remaining portion of the insulating layer 123 in the first trench 121, while in each second trench A metal silicide liner 131 is formed on the side surface 126s and the bottom surface 126b of 126, as shown in Figure 12. In some embodiments, the topmost portion of the metal silicide liner 131 in each second trench 126 is adjacent to, or in direct contact with, the bottommost portion of the remaining portion of the insulating layer 123 in the first trench 121 .

After forming the metal silicide liner 131 in each second trench 126 , a conductive portion 132 is formed in each second trench 126 to form a conductive structure 130 in the second trench 126 . Some example recipes are shown below.

Referring to Figure 13, according to some embodiments, a first conductive material 1320 is deposited over the structure shown in Figure 12, and the first conductive material 1320 fills the second trench 126 and the first trench 121, and is excessively The ground is higher than the top surface 114a of the pad oxide layer 114. As shown in Figure 13.

In some embodiments, the first conductive material 1320 may be formed of metal, alloy, polysilicon, other suitable conductive materials, or a combination of the foregoing materials. In some embodiments, the first conductive material 1320 may be a single layer or a multi-layer structure. In this example, first conductive material 1320 includes a single layer of polysilicon. Portions of the first conductive material 1320 in the second trench 126 are separated from the epitaxial layer 102 by a metal silicide liner 131 .

In some examples, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing processes to deposit the first conductive material. 1320.

Then, referring to FIG. 14 , according to some embodiments, a portion of the first conductive material 1320 is removed, so that the remaining portion of the first conductive material 1320 fills the second trench 126 to form the conductive portion 132 .

In some embodiments, the metal silicide liner 131 and the conductive portion 132 in each second trench 126 jointly form a conductive structure 130 . Among them, the metal silicide lining layer 131 covers the side walls 132s and the bottom surface 132b of the conductive part 132, as shown in Figure 14.

In some examples, the step of removing a portion of the first conductive material 1320 may (but is not limited to) include: forming a patterned photoresist above the first conductive material 1320, and applying the patterned photoresist to the first conductive material. Etch 1320 is performed to remove part of the first conductive material 1320 to a specific depth, and form a conductive portion 132 as shown in FIG. 14 in the second trench 126 .

In some other examples, the step of removing a portion of the first conductive material 1320 may (but is not limited to) include: first removing an excess portion of the first conductive material 1320 through a planarization process, such as above the pad oxide layer 114 portion of the first conductive material 1320 to expose the pad oxide layer 114 . The above-mentioned planarization process is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes. After that, the portion of the first conductive material 1320 in the first trench 126 is etched back, so that the first conductive material 1320 is recessed to a specific depth into the second trench 126 to form a structure as shown in FIG. 14 The conductive portion 132 is shown.

According to some embodiments, the metal silicide liner 131 of the conductive structure 130 in the second trench 126 can serve as a junction between the drift region _RD and the conductive portion 132 having a second conductivity type (eg, n-type). Schottky barrier. Moreover, each conductive structure 130 is electrically connected to the source electrode (such as the metal layer 182 in FIG. 20) in subsequent processes, so as to form a Schottky diode (Schottky diode) with the drift region _RD as a whole. The intrinsic parasitic diode at the interface between the well region 106 and the drift region _RD of different conductivity types is called a body diode. The Schottky diode of the embodiment will be different from the body diode. bodies in parallel. Since the energy barrier of the Schottky diode is lower than that of the base diode, that is, the on-resistance (Von) is lower, when operating a semiconductor device, carriers will pass through the Schottky diode instead of the base diode. Polar body flow. Therefore, after the conductive structure 130 proposed according to the embodiment is subsequently electrically connected to the source electrode, it can form the above-mentioned Schottky diode, thereby disabling the base diode, thereby enabling the semiconductor device to reduce the on-resistance and Benefits of reduced power loss.

Furthermore, according to some embodiments of the present disclosure, the conductive structure 130 is located in the underlying drift region _RD rather than occupying the mesa region of the epitaxial layer 102 adjacent to the top surface 102 a of the epitaxial layer 102 . Therefore, the conductive structure 130 proposed in the embodiment does not need to occupy additional mesa area of the epitaxial layer 102, so it can reduce the cell pitch between adjacent cells in the device, thereby reducing the channel area resistance.

In some embodiments, as shown in FIG. 14 , the top surface 130 a of the conductive structure 130 (ie, the top surface 132 a of the conductive portion 132 ) is lower than the top surface of the epitaxial layer 102 (ie, the top surface of the well region 106 Top surface 106a).

In some embodiments, as shown in FIG. 14, the top surface 130a of the conductive structure 130 (ie, the top surface 132a of the conductive portion 132) is lower than the top surface 111a of the first heavily doped region 111 and is also lower than the top surface 111a of the first heavily doped region 111. The bottom surface 111b of the first heavily doped region 111. Similarly, the top surface 130a of the conductive structure 130 is lower than the top surface 112a of the second heavily doped region 112 and is also lower than the bottom surface 112b of the second heavily doped region 112.

In some embodiments, as shown in FIG. 14 , the top surface 130 a of the conductive structure 130 is lower than the bottom surface 106 b of the well region 106 . Therefore, according to some embodiments, the conductive structure 130 is buried in the drift region _RD , and the top surface 130a of the conductive structure 130 and the bottom surface 106b of the well region 106 are separated by a distance in the first direction D1 (eg, Z direction) .

Afterwards, the gate structure GS (FIG. 18) is fabricated above the conductive structure 130. According to some embodiments of the present disclosure, some intermediate stages of fabricating the gate structure GS are, for example, but not limited to, as shown in Figures 15 to 18.

Referring to FIG. 15, according to some embodiments, a dielectric layer 134 is formed on at least the side surface 121s and the bottom surface 121b of the first trench 121. In this example, forming a dielectric material on the structure shown in FIG. 14 includes forming the dielectric material on the pad oxide layer 114 and on the remaining portion of the insulating layer 123 in the first trench 121 . electrical material to form the dielectric layer 134 as shown in FIG. 15 . Specifically, in the first trench 121 , the dielectric material formed above the conductive structure 130 and corresponding to the portion deposited below the first trench 121 is the bottom portion 135 of the dielectric layer 134 . In the first trench 121 , the dielectric material formed on the remaining portion of the insulating layer 123 ( FIG. 14 ) is collectively referred to as sidewall portions 136 of the dielectric layer 134 together with the insulating layer 123 . The dielectric material formed on pad oxide layer 114 (FIG. 14), together with pad oxide layer 114, is referred to as top portions 137 of dielectric layer 134. That is, the dielectric layer 134 includes the aforementioned bottom portion 135, sidewall portions 136, and top portion 137.

In some embodiments, as shown in FIG. 15 , the thickness _TB of the bottom portion 135 of the dielectric layer 134 is greater than the thickness _TS of the sidewall portion 136 of the dielectric layer 134 . The thickness _TB is, for example, the thickness in the first direction D1 (eg, the Z direction), and the thickness _TS is, for example, the thickness in the second direction D2 (eg, the Z direction). In some embodiments, the bottom portion 135 of the dielectric layer 134 in the first trench 121 can be used to electrically isolate the subsequently formed gate electrode 142' from the underlying conductive structure 130. Therefore, the bottom portion 135 of the dielectric layer 134 with sufficient thickness _TB can well electrically isolate the gate electrode 142' from the conductive structure 130.

In some embodiments, the insulating layer 123 and the dielectric layer 134 may include the same material, or different materials. In some embodiments, pad oxide layer 114 may include the same material as dielectric layer 134 , or a different material. To simplify the drawings, the pad oxide layer 114 and/or the insulating layer 123 are omitted in Figures 15 to 20.

In some embodiments, the dielectric layer 134 may include an oxide such as silicon oxide, other suitable dielectric materials, or a combination of the foregoing materials. In some embodiments, dielectric layer 134 may be a single layer or multiple layers of dielectric material.

In some embodiments, the dielectric layer 134 may be formed on the first heavily doped region 111, the second heavily doped region 112, and the side surface 121s and the bottom surface 121b of the first trench 121 through a deposition process. The aforementioned deposition process is, for example, a conformal deposition process, and may be a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable deposition processes, or a combination of the foregoing processes.

In this example, a high density plasma chemical vapor deposition (HDP CVD) process may be used to deposit the dielectric material to form the dielectric layer 134 as shown in FIG. 15 . In the high-density plasma chemical vapor deposition process, the deposition speed of the dielectric material in the vertical direction (such as the first direction D1) is greater than the deposition speed in the horizontal direction (such as the second direction D2). Therefore, in some embodiments, as shown in FIG. 15, the thickness _TB of the bottom portion 135 of the dielectric layer 134 is greater than the thickness _TS of the sidewall portion 136 of the dielectric layer 134. Furthermore, the top portion 137 of the dielectric layer 134 also forms a tapered cross-section due to the difference in deposition speed in the vertical direction and the horizontal direction, as shown in FIG. 15 . However, it can be understood that the size, shape and formation method of the dielectric layer 134 as shown in FIG. 15 are only for illustrative purposes and are not intended to limit the embodiments of the present invention.

According to some embodiments, after a subsequent process to remove part of the dielectric layer 134, the remaining portion of the dielectric layer 134 in each first trench 121 can be used as a gate dielectric layer of the gate structure. dielectric layer) 134' (Figure 18), the manufacturing process of which is detailed below.

Referring to FIG. 16 , according to some embodiments, a second conductive material 1420 is deposited on the top surface 102 a of the epitaxial layer 102 , and the second conductive material 1420 is located on the dielectric layer 134 and fills the first trench 121 . Furthermore, in some embodiments, if the dielectric layer 134 has an undulating surface, the second conductive material 1420 may be excessively deposited to a specific thickness such that the top surface 1420a of the second conductive material 1420 is not only higher than the dielectric The topmost portion of layer 134 also presents a flat surface.

In some embodiments, the second conductive material 1420 may be formed of metal, alloy, polysilicon, other suitable conductive materials, or a combination of the foregoing materials. In some embodiments, the second conductive material 1420 may be a single layer or a multi-layer structure. To simplify the diagram, a single layer of second conductive material 1420 is drawn in this example.

Furthermore, the conductive structure 130 (including the conductive portion 132 made of the first conductive material 1320) in the second trench 126 is separated from the second conductive material 1420 by the bottom portion 135 of the dielectric layer 134. Come. In some embodiments, first conductive material 1320 and second conductive material 1420 comprise the same conductive material. In some other embodiments, first conductive material 1320 and second conductive material 1420 include different conductive materials. In this example, first conductive material 1320 and second conductive material 1420 include polysilicon.

In some examples, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing processes to deposit the second conductive material. 1420.

Afterwards, according to some embodiments, a portion of the second conductive material 1420 is removed, so that the remaining portion of the second conductive material 1420 fills the first trench 121 to form the conductive portion 142' (FIG. 18). The conductive portion 142' may be formed through a planarization process and an etching process, as described below.

As shown in FIG. 16, according to some embodiments, a planarization process is first used to remove a portion of the excess second conductive material 1420. For example, the portion of the second conductive material 1420 above the plane represented by the line L _C - L _C is first removed. After the planarization process, the remaining portion of the second conductive material 1420 has a flat top surface, as shown by the line L _C - L _C , and this flat top surface is close to the top of the dielectric layer 134 but still covers the dielectric layer 134 . Layer 134.

The above-mentioned planarization process is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes.

Then, referring to FIG. 17 , according to some embodiments, a portion of the second conductive material 1420 is removed to recess the second conductive material 1420 to expose the top portion 137 of the dielectric layer 134 . The remaining portion 142 of the second conductive material 1420 fills the first trench 121 and covers the sidewall portion 136 of the dielectric layer 134 and the top portion 137 of the dielectric layer 134 . In some examples, the top surface 142a of the remaining portion 142 of the second conductive material 1420 is slightly higher than the top surface 102a of the epitaxial layer 102 . In some examples, the top surface 142 a of the remaining portion 142 of the second conductive material 1420 is generally coplanar with the top surface 102 a of the epitaxial layer 102 .

In some embodiments, a portion of the second conductive material 1420 may be removed through a blanket etching process to form a remaining portion 142 of the second conductive material. In the blanket etching process, without using any photoresist, the second conductive material 1420 is selectively etched along the dielectric layer 134 to remove part of the second conductive material 1420 to a specific depth. In this example, the blanket etching process is a dry etching process. In this example, after the blanket etching process, the top surface 142a of the remaining portion 142 of the second conductive material 1420 is substantially coplanar with the top surface 102a of the epitaxial layer 102.

Thereafter, referring to FIG. 18 , according to some embodiments, a portion of the dielectric layer 143 is removed to expose the first heavily doped region 111 and the second heavily doped region 112 . The remaining portion of the dielectric layer 143 forms a gate dielectric layer 134' in each first trench 121. In this example, gate dielectric layer 134' includes sidewall portions 136' and bottom portion 135.

In some embodiments, the top portion 137 (FIG. 17) of the dielectric layer 134 and a portion of the sidewall portion 136 may be removed through a planarization process. And the remaining portion 142 of the second conductive material 1420 can also be planarized through this process. The above-mentioned planarization process is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes. In this example, a CMP process is used to polish the dielectric layer 134 (or the remaining portion 142 of the second conductive material 1420).

As shown in FIG. 18, after performing the above removal steps, the remaining portion of the dielectric layer 143 forms a gate dielectric layer 134' in each first trench 121, and the remaining portion of the second conductive material 1420 is A conductive portion 142' is formed in each first trench 121. The gate dielectric layer 134' and the conductive portion 142' together form a gate structure GS, in which the gate dielectric layer 134' covers the sidewalls 142s and the bottom surface 142b of the conductive portion 142'.

In this example, adjacent gate structures GS are spaced apart in the second direction D2, and each gate structure GS extends in the third direction D3, and a part (such as the bottom part) of the gate structure GS is located at the drift District R _D. Similarly, the conductive structures 130 below the gate structure GS are spaced apart in the second direction D2, and each conductive structure 130 extends in the third direction D3.

Furthermore, in some embodiments, the top surface 134a of the gate dielectric layer 134' and the top surface 142a of the conductive portion 142' are substantially coplanar. In some embodiments, the top surface 134a of the gate dielectric layer 134', the top surface 142a of the conductive portion 142', the top surface 111a of the first heavily doped region 111, and the top surface 112a of the second heavily doped region 112 Roughly coplanar.

In some embodiments, the gate structure GS in each first trench 121 is physically and electrically isolated from the conductive structure 130 in the second trench 121 below. For example, the conductive portion 142' of the gate structure GS and the conductive portion 132 of the underlying conductive structure 130 are separated by the gate dielectric layer 134' (especially the bottom portion 135 thereof), and are physically and electrically separated from each other. Ground isolation. As shown in FIG. 18, the conductive portion 132 (the top surface 132a) of the conductive structure 130 and the metal silicide liner 131 (the top surface 131a) directly contact the gate dielectric layer 134' of the gate structure GS.

Furthermore, according to some embodiments, for one gate structure GS, its opposite sides are respectively in contact with heavily doped regions of different conductivity types. Specifically, as shown in FIG. 18, one of the first heavily doped regions 111 (eg, p-type) is located on the first side 1341 of a gate structure GS, and the second heavily doped region 112 (eg, n-type) is located on the first side 1341 of a gate structure GS. One of the two types) is located on the second side 1342 of the gate structure GS. The second side 1342 is opposite to the first side 1341, where the first heavily doped region 111 directly contacts the gate dielectric layer adjacent to the first side 1341. 134 ′, the first heavily doped region 112 directly contacts the portion of the gate dielectric layer 134 ′ adjacent to the second side 1342 .

Furthermore, according to some embodiments, the formation method of the conductive structure 130 and the gate structure GS is to form successive trenches (including the first trench 121 penetrating the well region 106 and the first trench 121 located in the drift region R) in the epitaxial layer 102 The second trench 126 in _D ), then the conductive structure 130 is formed in the second trench 126, and then the gate structure GS is formed in the first trench 121 above the conductive structure 130. Therefore, the conductive structure 130 proposed in the embodiment will not additionally occupy the mesa area of the epitaxial layer 102 . In some embodiments, there is a first distance h1 along the first direction D1 between the bottom surface of the gate structure GS (ie, the bottom surface 135b of the bottom portion 135 of the dielectric layer 134) and the bottom surface 106b of the well region 106. There is a second distance h2 along the first direction D1 between the bottom surface of the conductive structure 130 (that is, the bottom surface 131b of the metal silicide liner 131) and the bottom surface 106b of the well region 106, and the second distance h2 is greater than the first distance h1. .

Furthermore, according to some embodiments, if viewed from above the well region 106 , the gate structure GS and the underlying conductive structure 130 overlap within the projection range of the substrate 100 . According to some embodiments, when viewed from above the well region 106, the projection range of the gate structure GS and the shielding region 1042' (or 1041') below the substrate 100 also overlaps.

Specifically, as shown in FIG. 18, in some embodiments, for example, the width W _G of the gate structure GS is used to represent the width of its projection range A _G on the substrate 100, and the width W _S of the conductive structure 130 is represented. Based on the width of the projection range A _S of the substrate 100 , the width W _G of the gate structure GS is greater than the width W _S of the conductive structure 130 below. Therefore, the projection range A _G of the gate structure GS on the substrate 100 covers the conductive structure on the substrate 100 The projection range of A _S . Furthermore, in some embodiments, the width W _P of the shielding area 1042 ′ (or 1041 ′) represents the width of its projection range _AP on the substrate 100 , and the width W _G of the gate structure GS may be greater than, less than, or approximately is equal to the width W _P of the shielding area 1042' (or 1041'), and the projection range AP of the shielding area 1042' (or 1041') covering a part of the bottom of the conductive structure ₁₃₀ will be consistent with the gate structure GS on the substrate. Projection ranges of 100 A _S overlap.

As in the above embodiment, since the conductive structure 130 is disposed under the gate structure GS, for example, the gate structure GS, the first heavily doped region 111 and the second heavily doped region 112 shown in Figure 18 are in the epitaxial layer. The top surfaces 102a of the epitaxial layer 102 are alternately arranged, so between the two adjacent gate structures GS, the top surface 102a of the epitaxial layer 102 only forms a first heavily doped region 111 and a second heavily doped region 112. Therefore, the conductive structure 130 formed by the embodiment can significantly reduce the pitch P of the gate structure GS.

After completing the epitaxial layer 102, the well region 106, the first heavily doped region 111, the second heavily doped region 112, the conductive structure 130 and the gate structure GS as described above, the contact plug 172 is formed (FIG. 20 ) to be electrically connected to the first heavily doped region 111, the second heavily doped region 112 and the well region 106, and form a source metal layer 182 (FIG. 20) and a drain metal layer (not shown). 19 and 20 are schematic cross-sectional views of intermediate manufacturing stages of forming contact plugs and source metal layers according to some embodiments of the present disclosure.

Referring to Figure 19, according to some embodiments, an interlayer dielectric (ILD) layer 160 is formed above the epitaxial layer 102, and the interlayer dielectric layer 160 covers the gate structure GS and part of the first heavily doped region 111 and part of the second heavily doped region 112 . In some examples, the interlayer dielectric layer 160 has a plurality of contact holes 162 . These contact holes 162 are located between two adjacent gate structures GS. And each contact hole 162 exposes a portion of the first heavily doped region 111 and a portion of the second heavily doped region 112 . As shown in FIG. 19 , each contact hole 162 exposes a portion of the top surface 111 a of the first heavily doped region 111 and a portion of the top surface 112 a of the second heavily doped region 112 .

In some embodiments, the interlayer dielectric layer 160 may be silicon oxide, or other suitable dielectric materials, or a combination of the foregoing materials. In some embodiments, the material of the interlayer dielectric layer 160 is different from the material of the gate dielectric layer 134'. In some other embodiments, the material of the interlayer dielectric layer 160 is the same as the material of the gate dielectric layer 134'.

According to some embodiments, the interlayer dielectric layer 160 having the contact hole 162 may be formed through a deposition process, a photolithographic patterning process, and an etching process. In one example, a deposition process is first used to deposit a layer of interlayer dielectric material (not shown) on the first heavily doped region 111 , the second heavily doped region 112 and the gate structure GS. A photolithographic patterning process is then performed to remove part of the interlayer dielectric material to form contact holes 162 .

In some embodiments, the above-mentioned deposition process may be a chemical vapor deposition process, or other suitable processes, or a combination of the foregoing. In some embodiments, the above-mentioned photolithography patterning process includes photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying (eg, , hard bake), other suitable processes, or a combination of the aforementioned processes. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes.

Next, referring to FIG. 20 , according to some embodiments, a contact plug 172 is formed in the contact hole 162 . The contact plug 172 is located on the epitaxial layer 102 and directly contacts the first heavily doped region 111 and the second heavily doped region 112 .

In some embodiments, the second heavily doped regions 112 having a first conductivity type (eg n-type) are source regions; and the first heavily doped regions 112 having a second conductivity type (eg p-type) The doped region 111 is in direct contact with the lower well region 106, so that the formed contact plug 172 can have good ohmic contact with the well region 106 through the first heavily doped region 111.

In some embodiments, the contact plug 172 includes a contact barrier layer 1721 and a contact conductive layer 1722. The contact barrier layer 1721 is formed on the sidewalls and bottom of the contact hole 162 (FIG. 19) as a barrier liner, and the contact conductive layer 1722 fills the remaining space in the contact hole 162. In this example, as shown in FIG. 20 , the top surface 1721 a of the contact barrier layer 1721 and the top surface 1722 a of the contact conductive layer 1722 are coplanar with the top surface 160 a of the interlayer dielectric layer 160 .

In some examples, a barrier material (not shown) may be formed on the interlayer dielectric layer 160 through a deposition process, and the barrier material is conformably deposited in the contact hole 162 (FIG. 19). ; Then deposit a conductive material (not shown) on top of the barrier material layer, and the conductive material fills the remaining space in the contact hole 162. Next, excess portions of the conductive material and barrier material above the interlayer dielectric layer 160 are removed (eg, etched) to form a contact barrier layer 1721 and a contact conductive layer 1722 in the contact hole 162 .

In some embodiments, the material of the contact barrier layer 1721 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), and other suitable barrier materials. , or a combination of the aforementioned materials. In some embodiments, the contact barrier may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the foregoing processes. Layer 1721.

In some embodiments, the contact conductive layer 1722 may be a one- or multi-layer structure, and its conductive materials may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (titanium nitride; TiN), tantalum nitride (tantalum nitride; TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or a combination of the aforementioned materials. Furthermore, in some embodiments, the conductive material can be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or a combination of the foregoing processes.

According to some embodiments of the present disclosure, the first heavily doped region 111 (eg, p+ region) and the second heavily doped region 112 (eg, n+ region) corresponding to each contact plug 172 are electrically connected to each other. If there is charge accumulation (making the voltage non-zero) between the source region (i.e., the second heavily doped region 112) and the substrate (i.e., the well region 106), it will affect the critical voltage of the semiconductor device and cause instability. Critical voltage, this is called the body effect. According to some embodiments of the present disclosure, since the second heavily doped region 112 (ie, the source region) is grounded, and the first heavily doped region 111 and the second heavily doped region 112 are in physical contact and electrical connection with each other, Therefore, the charges accumulated in the well region 106 when operating the semiconductor device can flow to the grounded second heavily doped region 112 through the first heavily doped region 111 and be eliminated, thereby avoiding the above-mentioned matrix effect and allowing the semiconductor device to have a stable critical voltage.

Referring again to FIG. 20 , according to some embodiments, after the contact plugs 172 are formed, a metal layer 182 is formed over the interlayer dielectric layer 160 and the contact plugs 172 . The metal layer 182 covers the contact plug 172 and is in physical and electrical contact with the contact plug 172 . Therefore, the metal layer 182 is electrically connected to the first heavily doped region 111 , the second heavily doped region 112 and the well region 106 through the contact plug 172 .

According to some embodiments, this metal layer 182 can be used as the top metal of a semiconductor device to be electrically connected to the second heavily doped region 112 serving as the source region, and therefore can also be called a source metal layer. layer)182. In some embodiments, the conductive structure 130 is electrically connected to the source metal layer 182 via other interconnects (not shown).

In some embodiments, metal layer 182 may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations of the foregoing materials. In some embodiments, the material of metal layer 182 is the same as the material of contact plug 172 . In some other embodiments, the material of metal layer 182 is different from the material of contact plug 172 . According to some embodiments, the metal layer 182 may be formed on the contact plug 172 through a deposition process. In some embodiments, the deposition process may be a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination of the foregoing.

Furthermore, according to some embodiments, the substrate 100 having the first conductivity type can be used as a drain region of the semiconductor device. In addition to the above-mentioned source metal layer 182, a drain metal layer (not shown) is also formed on the back side of the substrate 100 having a first conductivity type (eg, n-type) to complete the process of a semiconductor device. In some examples, the thickness of the wafer can be reduced through a backside grounding process, and then a backside metal can be formed on the backside of the wafer, such as the bottom surface 100b of the substrate 100, to form the drain electrode. metal layer.

In summary, the semiconductor device and the method for forming the same provided in some embodiments of the present disclosure have many benefits. According to some embodiments, the conductive structure 130 of the semiconductor device may be electrically connected to the source metal layer 182 via other interconnects (not shown). Since the second heavily doped region 112 (i.e., the source region) and the source metal layer 182 are grounded when operating the semiconductor device, the conductive structure 130 electrically connected to the source can be connected to the drift region _RD (having the second conductive region). type, such as n-type) constitutes a Schottky diode. The body diode generated at the interface of the well region 106 (having a first conductivity type, such as p-type) and the drift region _RD is connected in parallel with the Schottky diode of the embodiment. When operating the semiconductor device of the embodiment, carriers flow through the Schottky diode with a lower on-resistance (Von) rather than through the body diode. Therefore, according to the conductive structure 130 proposed in the embodiment, it is electrically connected to the Schottky diode composed of the source electrode (including the source metal layer 182 and the source region (ie, the second heavily doped region 112)). body, which can disable the base diode and reduce the on-resistance of the semiconductor device, thereby reducing power loss.

Furthermore, according to some embodiments of the present disclosure, the conductive structure 130 that can constitute the Schottky diode is disposed below the gate structure GS, for example, in the drift region _RD below the gate structure GS. In addition to Reducing the gate-drain capacitance (Cgd) does not occupy additional mesa area of the epitaxial layer, so the cell pitch between adjacent cells in the device can be reduced, thereby reducing the resistance of the channel area and reducing the size of the epitaxial layer. horizontal dimensions. In some embodiments, only a first heavily doped region 111 and a second heavily doped region 112 are included between two adjacent gate structures GS (FIG. 20). Therefore, the thickness of the gate structure GS can be greatly reduced. spacing, thereby reducing the lateral size of the epitaxial layer and the area of the semiconductor device.

Furthermore, according to some embodiments, the formation method of the conductive structure 130 and the gate structure GS is to form successive trenches in the epitaxial layer 102, such as the first trench 121 that runs through the well region 106 and extends to the drift. The second trench 126 in the region _RD is formed to form the conductive structure 130 in the second trench 126 and the gate structure GS in the first trench 121. Therefore, the formation method proposed in this disclosure can control the formation positions of the conductive structure 130 and the gate structure GS through the extending direction of the trench in the epitaxial layer 102, so that the conductive structure 130 and the gate structure GS can be accurately aligned. Therefore, based on the above, the semiconductor device and its formation method proposed in the embodiment can be used through a process that is compatible with the existing manufacturing process, that is, the conductive structure 130 can be accurately aligned with the gate structure GS located above, and the resulting semiconductor device When Schottky diodes can be formed to reduce on-resistance and power loss, the spacing between adjacent units (such as adjacent gate structures GS) can be reduced at the same time, thereby reducing the area of the semiconductor device. etc. benefits.

100: Substrate 102: Epitaxial layer 1021: First epitaxial part 1022: Second epitaxial part 104, 1041, 1042: Doping area 104', 1041', 1042': Shielding area 106: Well area R _D : Drift region 1110: first heavily doped region 1120: second heavily doped region 108, 109: patterned hard mask 108H, 109H: opening 111: first heavily doped region 112: second heavily doped region 114: liner Oxide layer 116: Nitride hard mask 117: Patterned photoresist layer 121, 121-1, 121-2: First trench 123: Insulating layer 124: Spacer layer 126, 126-1, 126-2: Second trench 130: Conductive structure 131 : metal silicide lining layer 1320: first conductive material 132, 142': conductive part GS: gate structure 134: dielectric layer 134': gate dielectric layer 135: bottom part 136, 136': side wall part 137: top part 1420, 142: second conductive material 142': gate electrode 100a, 1021a, 102a, 106a, 111a, 112a, 114a, 130a, 132a, 134a, 1420a, 142a, 1721a, 1722a: top surface 100b, 106b, 111b, 112b, 121b, 126b, 131b, 132b, 135b, 142b: bottom surface 121s, 126s: side surface 124s, 132s, 142s: side wall 1341: first side 1342: second side 160: interlayer dielectric layer 162: contact hole 172: contact Plug 1721: Contact barrier layer 1722: Contact conductive layer 182: Metal layer (source metal layer) IP-1, IP-2, IP-3: Ion implantation process W1, W2, W _G , W _S , W _P : Width T _B , T _S : Thickness L _C - L _C : Line h1: First distance h2: Second distance A _G , A _S , A _P : Projection range P: Spacing D1: First direction D2: Second Direction D3: The third direction

1 to 18 are schematic cross-sectional views of a semiconductor device including a gate structure and a conductive structure at various intermediate manufacturing stages according to some embodiments of the present disclosure. 19 and 20 are schematic cross-sectional views of intermediate manufacturing stages of forming contact plugs and source metal layers after forming the gate structure according to some embodiments of the present disclosure.

100:Base

102: Epitaxial layer

104’,1041’,1042’: shielded area

106:Well area

R _D : Drift area

111: The first heavily doped region

112: The second heavily doped region

114: Pad oxide layer

121,121-1,121-2: First trench

123:Insulation layer

130:Conductive structure

131: Metal silicide lining

132: Conductive Department

100a, 102a, 106a, 111a, 112a, 130a, 132a: top surface

106b,111b,112b,131b,132b: bottom surface

132s: Sidewall

D1: first direction

D2: second direction

D3: Third direction

Claims (23)

A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer formed on the substrate, and the epitaxial layer having the first conductivity type; a well region from the top of the epitaxial layer The surface extends into the epitaxial layer, and the well region has a second conductivity type; a drift region is formed in the epitaxial layer and contacts the bottom surface of the well region, and the drift region has the first conductivity type Type; a gate structure extending from the top surface of the epitaxial layer through the well region and contacting the drift region; and a conductive structure formed in the drift region and located below the gate structure, wherein the The conductive structure includes a conductive part and a metal silicide liner covering the sidewalls and bottom surface of the conductive part, and the conductive structure is electrically connected to a source electrode; wherein a gate of the gate structure A dielectric layer separates the conductive structure and a gate electrode of the gate structure. The semiconductor device of claim 1, wherein the top surface of the conductive structure is lower than the bottom surface of the well region. The semiconductor device of claim 1, wherein there is a first distance between the bottom surface of the gate structure and the bottom surface of the well area, and there is a second distance between the bottom surface of the conductive structure and the bottom surface of the well area, and the third The second distance is greater than the first distance. The semiconductor device of claim 1, wherein the width of the gate structure is greater than the width of the conductive structure. The semiconductor device of claim 1, wherein when viewed from above the well region, the projection range of the gate structure on the substrate covers the projection range of the conductive structure on the substrate. The semiconductor device of claim 1, wherein the gate dielectric layer includes a bottom portion and a sidewall portion, and the thickness of the bottom portion is greater than the thickness of the sidewall portion; wherein the bottom portion makes the The conductive structure is electrically isolated from the gate electrode. The semiconductor device of claim 1, further comprising a shielding region formed in the drift region and covering the bottom surface and part of the side surface of the conductive structure; wherein the shielding region has the second conductivity type ; When viewed from above the well area, the projection range of the gate structure on the base overlaps with the projection range of the shielding area on the base. The semiconductor device of claim 1, wherein the conductive portion and the metal silicide liner are in direct contact with the gate dielectric layer of the gate structure. The semiconductor device of claim 1, further comprising: a first heavily doped region formed in the well region and located on a first side of the gate structure; wherein the first heavily doped region has the second conductive type; and a second heavily doped region formed in the well region and located on a second side of the gate structure relative to the first side; wherein the second heavily doped region has the first conductivity type , the first conductivity type is different from the second conductivity type. The semiconductor device of claim 9, wherein the first heavily doped region directly contacts a portion of the gate dielectric layer adjacent to the first side of the gate structure, and the second heavily doped region directly contacts the portion adjacent to the gate structure. The portion of the gate dielectric layer on the second side of the gate structure point. The semiconductor device of claim 10, wherein the top surface of the conductive structure is lower than the bottom surface of the first heavily doped region and lower than the bottom surface of the second heavily doped region. The semiconductor device of claim 10, further comprising: another first heavily doped region formed in the well region, and the other first heavily doped region is adjacent to and directly contacts the second heavily doped region; wherein, The second heavily doped region is located between the other first heavily doped region and the gate structure. The semiconductor device of claim 12, further comprising: another gate structure adjacent to the gate structure, and the other gate structure extends from the top surface of the epitaxial layer through the well region and contacts the drift region; Wherein, the other first heavily doped region is located between the other gate structure and the second heavily doped region, and the other first heavily doped region directly contacts the other gate structure. A method of forming a semiconductor device, including: providing a substrate with a first conductivity type; forming an epitaxial layer with the first conductivity type on the substrate; doping from the top surface of the epitaxial layer to A well region is formed in the epitaxial layer, and the well region has a second conductivity type; below the well region is a drift region, the drift region has the first conductivity type and is connected to the bottom surface of the well region Contact; forming a plurality of conductive structures in the drift region, wherein each of the conductive structures includes a conductive part and a metal silicide liner covering the side walls and bottom surface of the conductive part, and the The conductive structure is electrically connected to a source electrode and gate structures are respectively formed above the conductive structures; wherein the gate structures extend from the top surface of the epitaxial layer through the well area, and the bottom portions of the gate structures are located in the drift area , and each of the gate structures includes a gate dielectric layer covering a gate electrode; wherein the gate dielectric layer separates the corresponding conductive structure and the gate structure. The method of forming a semiconductor device according to claim 14, wherein after forming the well region and before forming the conductive structures, it further includes: doping in the well region from the top surface of the epitaxial layer to form an alternating arrangement. A plurality of first heavily doped portions (first heavily doped portions) and a plurality of second heavily doped portions (second heavily doped portions); wherein the first heavily doped portions have the second conductivity type, and the third heavily doped portions The double doped portion has the first conductivity type; and removing some portions of each of the first heavily doped portions and the second heavily doped portions, and removing portions of the well region and portions of the epitaxial layer to form a plurality of first trenches; wherein the first trenches extend from the top surface of the epitaxial layer through the well region, and the bottom surfaces of the first trenches are exposed the drift zone. The method of forming a semiconductor device as claimed in claim 15, wherein the drift region includes a plurality of shielding regions, and the shielding regions respectively correspond to below the first trenches, and the shielding regions have the second Conductive type. The method of forming a semiconductor device according to claim 16, further comprising: removing a portion of the drift region and a portion of the drift region from the bottom surfaces of the first trenches. some shielding areas to form a plurality of second trenches; wherein the second trenches are respectively connected to the corresponding first trenches, and the bottom surfaces of the second trenches expose the shielding areas area. The method of forming a semiconductor device according to claim 17, wherein the width of each of the first trenches is greater than the width of each of the second trenches. The method of forming a semiconductor device as claimed in claim 17, wherein forming the conductive structures includes: forming a metal silicide liner in each of the second trenches; and forming a metal silicide liner on the top surface of the epitaxial layer. A first conductive material is deposited above, and the first conductive material fills the second trenches and the first trenches; and a portion of the first conductive material is removed, and the first conductive material is filled in the second trenches. The remaining portions of the first conductive material form the conductive portions as the first conductive portions; wherein in each of the second trenches, the metal silicide liner covers the first conductive portions. side walls and bottom surface. The method of forming a semiconductor device as claimed in claim 19, wherein forming the gate structures includes: forming a dielectric layer on the sidewalls and bottom surfaces of the first trenches; depositing on the top surface of the epitaxial layer a second conductive material, the second conductive material is located on the dielectric layer, and the second conductive material fills the first trenches; and removing part of the second conductive material and part of the dielectric layer ; wherein in each of the first trenches, the remaining portion of the second conductive material forms a second conductive portion, and the remaining portion of the dielectric layer forms the gate dielectric layer; Wherein, in each of the first trenches, the gate dielectric layer covers the sidewalls and bottom surface of the second conductive portion, and the second conductive portion is in contact with the first conductive portion below. The parts are separated by the gate dielectric layer. The method of forming a semiconductor device according to claim 15, wherein the remaining portions of the first heavily doped portions and the remaining portions of the second heavily doped portions are the first heavily doped regions and the second heavily doped portions respectively. doped regions, and opposite sides of each of the first trenches respectively contact one of the first heavily doped regions and one of the second heavily doped regions. The method of forming a semiconductor device according to claim 14, further comprising: forming a plurality of first heavily doped regions in the well region, the first heavily doped regions being arranged apart; wherein the first heavily doped regions having the second conductivity type; and forming a plurality of second heavily doped regions in the well region, the second heavily doped regions being spaced apart; wherein the second heavily doped regions have the first conductivity type , the first conductivity type is different from the second conductivity type. The method of forming a semiconductor device according to claim 22, wherein one of the first heavily doped regions and one of the second heavily doped regions are included between two adjacent gate structures. .

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