CN115966599A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115966599A CN115966599A CN202111172658.7A CN202111172658A CN115966599A CN 115966599 A CN115966599 A CN 115966599A CN 202111172658 A CN202111172658 A CN 202111172658A CN 115966599 A CN115966599 A CN 115966599A
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Abstract
A semiconductor structure and method of forming the same, the semiconductor structure comprising: a device gate structure located on the isolation layer and crossing the channel structure; the source-drain doped region is positioned in the channel structures at two sides of the grid structure of the device; and the source-drain contact structure is positioned on two sides of the device grid structure and is contacted with the source-drain doped regions of the adjacent device regions along the second direction, the source-drain contact structure comprises a first part positioned on the source-drain doped regions and a second part which is positioned on the isolation layer between the adjacent first parts along the second direction and is connected with the adjacent first parts, and the top surface of the second part is lower than that of the first part, so that the reduction of parasitic capacitance between the device grid structure and the source-drain contact structure is facilitated, and the performance of the semiconductor structure is optimized.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
A MOS transistor generally includes an active region, a gate structure on the active region, and source and drain doped regions in the active region on both sides of the gate structure. A source-drain contact structure contacting the source-drain doped region is usually formed on the source-drain doped region for electrically connecting the source-drain doped region with an external circuit.
The capacitance between the gate structure and the source-drain doped region and between the gate structure and the source-drain contact structure is an important component of the parasitic capacitance of the transistor. When the source-drain contact structure is connected with the source-drain doped regions of the transistors, the source-drain contact structure is located on two sides of the gate structure, and the area of the parallel front surface between the source-drain contact structure and the gate structure is large, so that the parasitic capacitance between the gate structure and the source-drain contact structure is large.
A gate sidewall is usually formed on the sidewall of the gate structure, and the conventional method for reducing the parasitic capacitance between the gate structure and the source-drain contact structure usually reduces the k value of the gate sidewall material.
However, the performance of semiconductor structures remains to be improved.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate and a plurality of protruding structures which are separated from the substrate, wherein the protruding structures extend along a first direction and are arranged at intervals along a second direction, and each protruding structure comprises a protruding part and a channel structure positioned on the protruding part; the substrate comprises a plurality of device regions arranged along a second direction; the isolation layer is positioned on the substrate, surrounds the bulge part and exposes the channel structure; a device gate structure located on the isolation layer and crossing the channel structure; the source-drain doped region is positioned in the channel structures at two sides of the grid structure of the device; and the source-drain contact structure is positioned on two sides of the device grid structure and is in contact with a plurality of source-drain doped regions adjacent to the device region along the second direction, the source-drain contact structure comprises first parts positioned on the source-drain doped regions and second parts which are positioned on the isolation layers between the adjacent first parts along the second direction and are connected with the adjacent first parts, and the top surfaces of the second parts are lower than the top surfaces of the first parts.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate and a plurality of raised structures separated on the substrate, wherein the raised structures extend along a first direction and are arranged at intervals along a second direction, and each raised structure comprises a raised part and a channel structure positioned on the raised part; the substrate comprises a plurality of device regions arranged along a second direction; an isolation layer surrounding the protruding portion is formed on the substrate, and the isolation layer exposes the channel structure; forming a device grid structure which is positioned on the isolation layer and crosses the channel structure, and source-drain doped regions which are positioned in the channel structures at two sides of the device grid structure; and forming source-drain contact structures on two sides of the device grid structure, wherein the source-drain contact structures are contacted with a plurality of source-drain doped regions adjacent to the device region along the second direction, each source-drain contact structure comprises a first part and a second part, the first parts are positioned on the source-drain doped regions, the second parts are positioned on the isolation layers between the adjacent first parts along the second direction and are connected with the adjacent first parts, and the top surfaces of the second parts are lower than the top surfaces of the first parts.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, along the second direction, the source-drain contact structure is in contact with the source-drain doped regions of a plurality of adjacent device regions, the source-drain contact structure comprises a first part and a second part, the first part is positioned on the source-drain doped regions, the second part is positioned on the isolation layer between the adjacent first parts along the second direction and is connected with the adjacent first parts, and the top surface of the second part is lower than that of the first part, so that the parallel dead-against area between the source-drain contact structure and the device gate structure is reduced, the parasitic capacitance between the source-drain contact structure and the device gate structure is further reduced, and the performance of the semiconductor structure is optimized.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the source-drain contact structures are formed on two sides of the device gate structure, and are contacted with the source-drain doped regions of a plurality of adjacent device regions along the second direction, each source-drain contact structure comprises a first part and a second part, the first part is positioned on the source-drain doped regions, the second part is positioned on the isolation layer between the adjacent first parts along the second direction and is connected with the adjacent first parts, and the top surfaces of the second parts are lower than the top surfaces of the first parts, so that the parallel opposite area between the source-drain contact structures and the device gate structure is reduced, the parasitic capacitance between the source-drain contact structures and the device gate structure is further reduced, and the performance of the semiconductor structure is optimized.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of another semiconductor structure;
FIGS. 3-4 are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 5 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the performance of semiconductor structures is still to be improved.
Referring to fig. 1 in combination, taking a finfet as an example, the parasitic capacitance of the transistor includes: a first parasitic capacitance C1 between the first metal layers 1; a second parasitic capacitance C2 between the source-drain contact plug 2 and the gate structure 3; a third parasitic capacitance C3 between the gate structure 3 and the source-drain doped region 4; and a source-drain contact plug 2 that contacts the source region 4 (S) in the source-drain doped region 4, and a parasitic capacitance C4 between the drain region 4 (D).
The capacitances C3 and C2 between the gate structure 3 and the source-drain doped region 4 and between the source-drain contact plug 2 are important components of the parasitic capacitance of the transistor.
The transistor further includes a gate sidewall spacer (not shown) on the sidewall of the gate structure 3 according to the capacitance formula
Correspondingly, the grid side wall is arranged between the grid structure 3 and the source-drain contact plug 2, and when the dielectric constant epsilon of the material of the grid side wall is smaller than the dielectric constant epsilon of the material of the grid side wall r The lower the parasitic capacitance C2 between the gate structure 3 and the source-drain contact plug 2 is, the smaller.
Therefore, with reference to fig. 2, a semiconductor structure is proposed at present, in which a gate sidewall 7 with an air gap 6 is formed on a sidewall of a gate structure 5, so as to reduce a dielectric constant of a material of the gate sidewall 7, thereby achieving a purpose of reducing a parasitic capacitance between a source-drain contact structure 8 and the gate structure 5.
However, the current process for forming the gate sidewall 7 with the air gap 6 is complex, and the air gap 6 has a limited effect of reducing the parasitic capacitance between the source-drain contact structure 8 and the gate structure 5.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, where, along the second direction, the source-drain contact structure is in contact with a plurality of source-drain doped regions adjacent to the device region, the source-drain contact structure includes a first portion located on the source-drain doped region, and a second portion located on an isolation layer between adjacent first portions along the second direction and connected to the adjacent first portions, and a top surface of the second portion is lower than a top surface of the first portion, so as to reduce a parallel facing area between the source-drain contact structure and the device gate structure, further reduce a parasitic capacitance between the source-drain contact structure and the device gate structure, and optimize performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention further provides a method for forming a semiconductor structure, where a source-drain contact structure is formed on two sides of the device gate structure, and the source-drain contact structure is in contact with a plurality of source-drain doped regions adjacent to the device region along the second direction, the source-drain contact structure includes a first portion located on the source-drain doped region and a second portion located on the isolation layer between the adjacent first portions along the second direction and connected to the adjacent first portions, and a top surface of the second portion is lower than a top surface of the first portion, so as to reduce a parallel facing area between the source-drain contact structure and the device gate structure, further reduce a parasitic capacitance between the source-drain contact structure and the device gate structure, and optimize performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 3 to 4, fig. 3 is a schematic perspective view of a semiconductor structure according to an embodiment of the present invention, and fig. 4 is a cross-sectional view taken along a direction d-d2 of fig. 3.
As shown in fig. 3 to 4, in the present embodiment, the semiconductor structure includes: the substrate 100 and a plurality of protruding structures 200 separated from the substrate 100, wherein the protruding structures 200 extend along a first direction D1 and are arranged at intervals along a second direction D2, and the protruding structures 200 include a protruding portion 110 and a channel structure 120 located on the protruding portion 110; the substrate 100 includes a plurality of device regions 100a arranged along a second direction D2; an isolation layer 130 on the substrate 100 and surrounding the protrusion 110 and exposing the channel structure 120; a device gate structure 140 on the isolation layer 130 and crossing the channel structure 120; the source-drain doped region 160 is located in the channel structure 120 on two sides of the device gate structure 140; the source-drain contact structure 300 is located on both sides of the device gate structure 140, and along the second direction D2, the source-drain contact structure 300 contacts with the plurality of source-drain doped regions 160 adjacent to the device region 100a, the source-drain contact structure 300 includes a first portion 310 located on the source-drain doped region 160, a second portion 320 located on the isolation layer 130 between the adjacent first portions 310 along the second direction D2 and connected to the adjacent first portion 310, and a top surface of the second portion 320 is lower than a top surface of the first portion 310.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
The device region 100a is used to form a transistor.
In this embodiment, the material of the substrate 100 includes: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. As an example, the substrate 100 is a silicon substrate, i.e. the material of the substrate 100 is monocrystalline silicon.
The bump structure 200 includes a bump 110 and a channel structure 120 on the bump 110.
The boss 110 is used to support the channel structure 120. The protrusion 110 is also used to form an isolation layer 130 to provide a space so that the isolation layer 130 can surround the protrusion 110 and expose the channel structure 120, and the isolation layer 130 can isolate the substrate 100 from a device gate structure formed later.
In this embodiment, the protrusion 110 and the substrate 100 are of an integral structure, and the material of the protrusion 110 and the material of the substrate 100 are the same and are both silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
The channel structure 120 is used to provide a conduction channel of a field effect transistor.
In this embodiment, the material of the channel structure 120 includes: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. As an example, the material of the channel structure 120 is monocrystalline silicon.
In this embodiment, a fin field effect transistor is formed as an example, the protruding structures 200 are fins, and the channel structures 120 are correspondingly effective fins for providing a conductive channel of the fin field effect transistor. Accordingly, the channel structure 120 and the protrusion 110 are of an integral structure.
In other embodiments, when other types of field effect transistors are formed, the channel structure is correspondingly other types of channel structures.
For example: when a fully-enclosed Gate (GAA) transistor or a nanosheet field effect transistor (NSFET) is formed, the channel structure is arranged on the protruding portion at intervals in a suspended manner, the channel structure comprises one or more channel layers which are sequentially arranged at intervals in a suspended manner, and the stacking direction of the channel layers is perpendicular to the surface of the substrate. The channel layer is used for providing a conductive channel of a fully-enclosed gate transistor or a nanosheet field effect transistor.
The top surface of the isolation layer 130 is lower than the top surface of the bump structure 200.
The isolation layer 130 is used to isolate the adjacent protruding portions 110, and is also used to isolate the substrate 100 from the subsequent device gate structure.
In this embodiment, the material of the isolation layer 130 is silicon oxide. The material of the isolation layer 130 may also be other insulating materials, such as: one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon germanium oxide, boron nitride, boron carbonitride, and silicon germanium oxide.
The device gate structure 140 is used to control the turn-on and turn-off of the conductive channel of the device during device operation. In this embodiment, the device gate structure 140 is used to control the conduction channel of the finfet to be turned on and off, and the device gate structure 140 covers part of the top and part of the sidewall of the fin.
In other embodiments, the device gate structure surrounds the channel layer when forming a fully-wrapped-around gate transistor or a nanosheet field effect transistor.
In this embodiment, the device gate structure 140 is a metal gate structure.
In this embodiment, the device gate structure 140 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used for realizing electric insulation between the gate electrode layer and the conducting channel.
The gate dielectric layer is made of silicon oxide, nitrogen-doped silicon oxide and HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 And Al 2 O 3 One or more of (a).
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the high-k gate dielectric layer is made of a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO 2 、HfSiO、HfSiON, hfTaO, hfTiO, hfZrO, or Al 2 O 3 . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.
The gate electrode layer is used as an external electrode for electrically connecting the device gate structure 140 to an external circuit. The material of the gate electrode layer includes: one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.
In a specific embodiment, the gate electrode layer may include: a capping layer (not shown), a work function layer (not shown), a blocking layer (not shown), and a metal electrode layer sequentially stacked on the gate dielectric layer.
A gate sidewall 150 is further formed on the sidewall of the device gate structure 140.
The gate sidewall 150 is used to define the formation position of the source-drain doped region 160, and the gate sidewall 150 is also used to protect the sidewall of the gate structure of the device.
In this embodiment, the gate sidewall 150 is made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials, and the gate sidewall 150 has a single-layer or stacked-layer structure. As an example, the gate sidewall spacers 150 have a single-layer structure, and the material of the gate sidewall spacers 150 is silicon nitride.
The source-drain doped region 160 is used as a source or a drain of the field effect transistor, and when the field effect transistor works, the source-drain doped region 160 is used for providing a current carrier source for the PMOS device.
In this embodiment, the source-drain doped region 160 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, so as to improve the mobility of carriers.
Specifically, when an NMOS transistor is formed, the source-drain doped region 160 is made of a stress layer doped with N-type ions, the stress layer is made of Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so that carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, as ions or Sb ions.
When a PMOS transistor is formed, the source-drain doped region 160 is made of a stress layer doped with P-type ions, the stress layer is made of Si or SiGe and provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, and the P-type ions are B ions, ga ions or In ions.
It should be noted that the shape of the source/drain doped region 160 is shown as an example. In other embodiments, the source and drain doped regions may also have other shapes.
Along the second direction D2, the source-drain contact structure 300 is in contact with the source-drain doped regions 160 of the plurality of adjacent device regions 100a, and the top surface of the second portion 320 is lower than the top surface of the first portion 310, so that the parallel facing area between the source-drain contact structure 300 and the device gate structure 140 is reduced, the parasitic capacitance between the source-drain contact structure 300 and the device gate structure 140 is reduced, and the performance of the semiconductor structure is optimized.
The source-drain contact structure 300 is used to realize the electrical connection between the source-drain doped region 160 and an external circuit or other interconnect structures.
In this embodiment, the source-drain contact structure 300 is located at two sides of the device gate structure 140 and the gate sidewall 150, so that the source-drain contact structure 300 and the device gate structure 140 are electrically isolated by the gate sidewall 150.
Along the second direction D2, the source-drain contact structure 300 contacts with the plurality of source-drain doped regions 160 adjacent to the device region 100a, so that interconnection of the source-drain doped regions 160 of the plurality of device regions 100a is realized, and the volume of the source-drain contact structure 300 is increased, thereby reducing the resistance of the source-drain contact structure 300.
The source-drain contact structure 300 is made of a conductive material. In this embodiment, the source-drain contact structure 300 is made of a metal material, and the resistivity of the metal material is low, which is beneficial to further reducing the resistance of the source-drain contact structure 300 and improving the conductivity of the source-drain contact structure 300. For example: the source-drain contact structure 300 is made of one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN.
As an example, the material of the source-drain contact structure 300 is Co. The resistivity of Co is low, which is beneficial to reducing the resistance of the source-drain contact structure 300, and the cobalt has small chemical activity and weak electromigration, which is beneficial to improving the electromigration problem of the source-drain contact structure 300, thereby being beneficial to the size reduction of devices. In addition, co can be formed by an electrochemical plating process, which is beneficial to simplifying the process difficulty of forming the source-drain contact structure 300.
In this embodiment, the first portion 310 and the second portion 320 define a groove 301 therebetween. Specifically, the side wall of the first portion 310 and the top surface of the second portion 320 enclose the groove 301.
It should be noted that the height difference between the second portion 320 and the top surface of the first portion 310 is not too small, nor too large. If the height difference between the second portion 320 and the top surface of the first portion 310 is too small, the effect of reducing the parallel facing area between the source-drain contact structure 300 and the device gate structure 140 is not obvious, and the effect of reducing the parasitic capacitance between the source-drain contact structure 300 and the device gate structure 140 is not obvious; if the height difference between the second portion 320 and the top surface of the first portion 310 is too large, the volume of the source-drain contact structure 300 is easily reduced too significantly, which is not favorable for reducing the resistance of the source-drain contact structure 300. For this reason, in the present embodiment, the height difference between the second portion 320 and the top surface of the first portion 310 is 5nm to 100nm.
In this embodiment, a recess is formed in the isolation layer 130 between the source-drain doped regions 160 adjacent to the device region 100a along the second direction; the second portion 320 also fills in the recess.
Through forming a recess in the isolation layer 130 between the source-drain doped regions 160 adjacent to the device region 100a in the second direction, in the formation process of the source-drain contact structure 300, the source-drain contact structure 300 can be formed in the recess, and when the source-drain contact structure 300 is formed by adopting a process with strong conformal covering capability, because the bottom of the recess is lower relative to the bottom surface of the source-drain contact opening, the top surface of the source-drain contact structure 300 located in the recess can be lower than the top surface of the source-drain contact structure 300 located on the source-drain doped region 160, that is, an additional photomask is not needed, the purpose that the top surface of the second portion 320 is lower than the top surface of the first portion 310 can be realized, and cost saving is facilitated.
In this embodiment, the source-drain contact structure 300 is an integrated structure, which is beneficial to reducing the resistance of the source-drain contact structure 300 and improving the electrical connection performance of the source-drain contact structure 300.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 170 (as shown in fig. 4) is located on the isolation layer 130 at the side of the device gate structure 140 and covers the source/drain doped region 160. The source-drain contact structure 300 is located in the first dielectric layer 170 on both sides of the device gate structure 140 and the gate sidewall spacers 150.
The first dielectric layer 170 is an interlayer dielectric layer (ILD) for isolating adjacent devices. In this embodiment, the first dielectric layer 170 is made of silicon oxide. The material of the first dielectric layer 170 may also be other insulating materials.
In this embodiment, for convenience of illustration and description, only the first dielectric layer 170 is illustrated in a cross-sectional view.
It should be noted that, in this embodiment, the semiconductor structure further includes: and etching barrier layers (not shown) located between the source/drain doped region 160 and the first dielectric layer 170, and between the isolation layer 130 and the first dielectric layer 170.
In the step of forming the source-drain contact structure 300, a source-drain contact opening penetrating through the first dielectric layer 170 above the source-drain doped region 160 is usually formed first, and then the source-drain contact structure 300 is formed in the source-drain contact opening, where the etching stop layer is used to temporarily define the position where etching is stopped in the process of forming the source-drain contact opening, so as to reduce the probability of damage to the source-drain doped region 160 caused by the process of forming the source-drain contact opening.
The etch stop layer is made of a material having an etch selectivity with respect to the first dielectric layer 170 to ensure that the etch stop layer serves to define an etch stop position. As an example, the material of the etching barrier layer is silicon nitride.
It should be noted that, in this embodiment, the source-drain contact structure 300 penetrates through the etching barrier layer and the first dielectric layer 170 on the source-drain doped region 160, so that the source-drain contact structure 300 can be in contact with the source-drain doped region 160, so as to achieve electrical connection with the source-drain doped region 160.
In this embodiment, the first portion 310 and the second portion 320 define a recess 301 therebetween; the semiconductor structure further includes: and the second dielectric layer 360 is filled in the groove 301.
Specifically, in this embodiment, the top surface of the second portion 320 is lower than the top surface of the first portion 310, so that the top surface of the second portion 320 and the side wall of the first portion 310 enclose the groove 301.
The second dielectric layer 360 is filled in the groove 301, so as to provide a flat surface for the formation process of the semiconductor structure.
The material of the second dielectric layer 360 is an electrically insulating material. The second dielectric layer 360 is made of silicon oxide. The material of the second dielectric layer 360 may also be other insulating materials.
Correspondingly, the invention also provides a forming method of the semiconductor structure. Fig. 5 to fig. 15 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
The method for forming the semiconductor structure of the present embodiment is described in detail below with reference to the accompanying drawings.
Referring to fig. 5 to 6, fig. 5 is a schematic perspective view, and fig. 6 is a cross-sectional view taken along a direction D-D2 in fig. 5, providing a substrate 100 and a plurality of protruding structures 200 separated from the substrate 100, wherein the protruding structures 200 extend along a first direction D1 and are arranged at intervals along a second direction D2, and the protruding structures include a protruding portion 110 and a channel structure 120 located on the protruding portion 110; the substrate 100 includes a plurality of device regions 100a arranged in a second direction; an isolation layer 130 surrounding the protrusion 110 is formed on the substrate 100, and the isolation layer 130 exposes the channel structure 120.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
The device region 100a is used to form a transistor.
In this embodiment, the material of the substrate 100 includes: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. As an example, the substrate 100 is a silicon substrate, i.e. the material of the substrate 100 is monocrystalline silicon.
The bump structure 200 includes a bump 110 and a channel structure 120 on the bump 110.
Wherein the protrusion 110 is used to support the channel structure 120. The protrusion 110 is also used to form an isolation layer 130 to provide a space so that the isolation layer 130 can surround the protrusion 110 and expose the channel structure 120, and the isolation layer 130 can isolate the substrate 100 from a device gate structure formed later.
In this embodiment, the protrusion 110 and the substrate 100 are of an integral structure, and the material of the protrusion 110 and the material of the substrate 100 are the same and are both silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
The channel structure 120 is used to provide a conduction channel of a field effect transistor.
In this embodiment, the material of the channel structure 120 includes: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. As an example, the material of the channel structure 120 is monocrystalline silicon.
In this embodiment, taking the formation of the finfet as an example, the protruding structures 200 are fins, and the channel structures 120 are correspondingly effective fins for providing a conductive channel of the finfet. Accordingly, the channel structure 120 and the protrusion 110 are of an integral structure.
In other embodiments, when other types of field effect transistors are formed, the channel structure is correspondingly other types of channel structures.
For example: when a fully-enclosed Gate (GAA) transistor or a nanosheet field effect transistor (NSFET) is formed, the channel structure is arranged on the protruding portion at intervals in a suspended manner, the channel structure comprises one or more channel layers which are sequentially arranged at intervals in a suspended manner, and the stacking direction of the channel layers is perpendicular to the surface of the substrate. The channel layer is used for providing a conductive channel of a fully-enclosed gate transistor or a nanosheet field effect transistor.
In the step of providing the substrate, a sacrificial layer is further formed between the channel structure and the protruding portion, or between adjacent channel layers in the channel structure, and the sacrificial layer is used for supporting the channel layers, so that a process foundation is provided for the subsequent spaced suspension arrangement of the channel layers, and the sacrificial layer is further used for occupying a space position for the subsequent formation of a device gate structure.
The top surface of the isolation layer 130 is lower than the top surface of the bump structure 200.
The isolation layer 130 is used to isolate the adjacent protruding portions 110, and is also used to isolate the substrate 100 from the subsequent device gate structure.
In this embodiment, the isolation layer 130 is made of silicon oxide. The material of the isolation layer 130 may also be other insulating materials, such as: one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon germanium oxide, boron nitride, boron carbonitride, and silicon germanium oxide.
Referring to fig. 7 and 8, fig. 7 is a schematic perspective view, and fig. 8 is a cross-sectional view along the direction d-d2 of fig. 7, forming a device gate structure 140 located on the isolation layer 130 and crossing the channel structure 120, and source-drain doped regions 160 located in the channel structure 120 at two sides of the device gate structure 140.
The device gate structure 140 is used to control the turn-on and turn-off of the conductive channel of the device during device operation. In this embodiment, the device gate structure 140 is used to control the conduction channel of the finfet to be turned on and off, and the device gate structure 140 covers part of the top and part of the sidewall of the fin.
In other embodiments, the device gate structure surrounds the channel layer when forming a fully-wrapped-around gate transistor or a nanosheet field effect transistor.
In this embodiment, the device gate structure 140 is a metal gate structure.
In this embodiment, the device gate structure 140 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used for realizing electric insulation between the gate electrode layer and the conducting channel.
The gate dielectric layer is made of silicon oxide, nitrogen-doped silicon oxide and HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 And Al 2 O 3 One or more of (a).
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the high-k gate dielectric layer is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.
The gate electrode layer is used as an external electrode for electrically connecting the device gate structure 140 to an external circuit. The material of the gate electrode layer comprises: one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.
In a specific embodiment, the gate electrode layer may include: a capping layer (not shown), a work function layer (not shown), a barrier layer (not shown), and a metal electrode layer sequentially stacked on the gate dielectric layer.
A gate sidewall 150 is further formed on the sidewall of the device gate structure 140.
The gate sidewall 150 is used to define the formation position of the source/drain doped region 160, and the gate sidewall 150 is also used to protect the sidewall of the gate structure of the device.
In this embodiment, the material of the gate sidewall 150 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials, and the gate sidewall 150 is a single-layer or stacked-layer structure. As an example, the gate sidewall spacers 150 have a single-layer structure, and the material of the gate sidewall spacers 150 is silicon nitride.
The source-drain doped region 160 is used as a source or a drain of the field effect transistor, and when the field effect transistor works, the source-drain doped region 160 is used for providing a current carrier source for the PMOS device.
In this embodiment, the source-drain doped region 160 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, so as to improve the mobility of carriers.
Specifically, when an NMOS transistor is formed, the source-drain doped region 160 is made of a stress layer doped with N-type ions, the stress layer is made of Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so that carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, as ions or Sb ions.
When a PMOS transistor is formed, the source-drain doped region 160 is made of a stress layer doped with P-type ions, the stress layer is made of Si or SiGe and provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, and the P-type ions are B ions, ga ions or In ions.
It should be noted that the shape of the source/drain doped region 160 is shown as an example. In other embodiments, the source-drain doped region may also have other shapes.
It should be further noted that in the present embodiment, in the step of forming the device gate structure 140 and the source-drain doped region 160, an etching blocking layer (not shown) is formed on the source-drain doped region 160 and the isolation layer 130, and a first dielectric layer 170 covering the etching blocking layer is formed on a side portion of the device gate structure 140.
In the subsequent step of forming the source-drain contact structure, a source-drain contact opening penetrating through the first dielectric layer 170 above the source-drain doped region 160 is usually formed first, and then a source-drain contact structure is formed in the source-drain contact opening, where the etching stop layer is used to temporarily define the position where etching is stopped in the process of forming the source-drain contact opening, so as to reduce the probability of damage to the source-drain doped region 160 caused by the process of forming the source-drain contact opening.
The etch stop layer is made of a material having an etch selectivity with the first dielectric layer 170, so as to ensure the function of the etch stop layer for defining an etch stop position. As an example, the material of the etching barrier layer is silicon nitride.
The first dielectric layer 170 is an interlayer dielectric layer (ILD) for isolating adjacent devices. In this embodiment, the first dielectric layer 170 is made of silicon oxide. The material of the first dielectric layer 170 may also be other insulating materials.
In this embodiment, for convenience of illustration and description, only the first dielectric layer 170 is illustrated in a cross-sectional view.
Referring to fig. 9 to 12, a source-drain contact structure 300 is formed on two sides of the device gate structure 140, and along the second direction D2, the source-drain contact structure 300 contacts with a plurality of source-drain doped regions 160 adjacent to the device region 100a, the source-drain contact structure 300 includes a first portion 310 located on the source-drain doped region 160, and a second portion 320 located on the isolation layer 130 between the adjacent first portions 310 along the second direction D2 and connected to the adjacent first portion 310, and a top surface of the second portion 320 is lower than a top surface of the first portion 310.
Along the second direction D2, the source-drain contact structure 300 is in contact with the source-drain doped regions 160 of the plurality of adjacent device regions 100a, and the top surface of the second portion 320 is lower than the top surface of the first portion 310, so that the parallel facing area between the source-drain contact structure 300 and the device gate structure 140 is reduced, the parasitic capacitance between the source-drain contact structure 300 and the device gate structure 140 is reduced, and the performance of the semiconductor structure is optimized.
The source-drain contact structure 300 is used to electrically connect the source-drain doped region 160 with an external circuit or other interconnect structures.
In this embodiment, in the step of forming the source/drain contact structure 300, the source/drain contact structure 300 is located on two sides of the device gate structure 140 and the gate sidewall 150, so that the source/drain contact structure 300 is electrically isolated from the device gate structure 140 by the gate sidewall 150.
Along the second direction D2, the source-drain contact structure 300 is in contact with the source-drain doped regions 160 of the plurality of adjacent device regions 100a, so that interconnection of the source-drain doped regions 160 of the plurality of device regions 100a is realized, and the volume of the source-drain contact structure 300 is increased, thereby reducing the resistance of the source-drain contact structure 300.
The source-drain contact structure 300 is made of a conductive material. In this embodiment, the source-drain contact structure 300 is made of a metal material, and the resistivity of the metal material is low, which is beneficial to further reducing the resistance of the source-drain contact structure 300 and improving the conductivity of the source-drain contact structure 300. For example: the source-drain contact structure 300 is made of one or more materials selected from Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti and TiN.
As an example, the material of the source-drain contact structure 300 is Co. The resistivity of Co is low, which is beneficial to reducing the resistance of the source-drain contact structure 300, and the cobalt has small chemical activity and weak electromigration, which is beneficial to improving the electromigration problem of the source-drain contact structure 300, thereby being beneficial to the size reduction of devices. In addition, co can be formed by an electrochemical plating process, which is beneficial to simplifying the process difficulty of forming the source-drain contact structure 300.
It should be noted that, in this embodiment, the source-drain contact structure 300 penetrates through the etching barrier layer and the first dielectric layer 170 on the source-drain doped region 160, so that the source-drain contact structure 300 can be in contact with the source-drain doped region 160, so as to achieve electrical connection with the source-drain doped region 160.
In this embodiment, the first portion 310 and the second portion 320 define a groove 301 therebetween. Specifically, the side wall of the first portion 310 and the top surface of the second portion 320 enclose the groove 301.
It should be noted that the height difference between the second portion 320 and the top surface of the first portion 310 is not too small, nor too large. If the height difference between the second portion 320 and the top surface of the first portion 310 is too small, the effect of reducing the parallel facing area between the source-drain contact structure 300 and the device gate structure 140 is not obvious, and further the effect of reducing the parasitic capacitance between the source-drain contact structure 300 and the device gate structure 140 is not obvious; if the height difference between the second portion 320 and the top surface of the first portion 310 is too large, the volume of the source-drain contact structure 300 is easily reduced too significantly, which is not favorable for reducing the resistance of the source-drain contact structure 300. For this reason, in the present embodiment, the height difference between the second portion 320 and the top surface of the first portion 310 is 5nm to 100nm.
The steps for forming the source/drain contact structure 300 in this embodiment will be described in detail below with reference to the accompanying drawings.
As shown in fig. 9 to 10, source/drain contact openings 190 (shown in fig. 10) are formed on two sides of the device gate structure 140, so as to expose the source/drain doped regions 160 of the adjacent device regions 100a along the second direction D2 and the isolation layer 130 between the source/drain doped regions 160 of the adjacent device regions 100a along the second direction D2.
The source-drain contact openings 190 are used to provide a spatial location for forming a source-drain contact structure.
The source-drain contact opening 190 exposes the source-drain doped region 160 of the adjacent device region 100a along the second direction D2 and the isolation layer 130 located between the source-drain doped regions 160 of the adjacent device region 100a along the second direction D2, so that a source-drain contact structure formed in the source-drain contact opening 190 subsequently can be connected to the source-drain doped region 160 of the adjacent device region 100 a.
It should be noted that, in the step of forming the source/drain contact opening 190, a recess 330 is formed in the isolation layer 130 exposed at the bottom of the source/drain contact opening 190.
The recess 330 is formed in the isolation layer 130 exposed from the bottom of the source-drain contact opening 190, so that in the subsequent process of forming a source-drain contact structure, the source-drain contact structure can be formed in the recess 330, and when the source-drain contact structure is formed by adopting a process with strong conformal covering capability, because the bottom of the recess 330 is lower than the bottom surface of the source-drain contact opening 190, the top surface of the source-drain contact structure in the recess 330 can be lower than the top surface of the source-drain contact structure on the source-drain doped region 160, that is, an additional photomask is not needed, the purpose that the top surface of the second part is lower than the top surface of the first part can be realized, and cost saving is facilitated.
Specifically, the step of forming the source-drain contact opening 190 and the recess 330 includes: as shown in fig. 9, performing a main etching process on the source-drain doped region 160 and the first dielectric layer 170 on the isolation layer 130 located between the adjacent source-drain doped regions 160 along the second direction D2 to form an initial opening 195, where the initial opening 195 exposes the etching stop layer (not shown); as shown in fig. 10, performing an over-etching (over etch) process on the etch stop layer exposed by the initial opening 195, and forming the source-drain contact opening 190 in the first dielectric layer 170; during the over-etching process, the isolation layer 130 below the initial opening 195 is also over-etched, and the recess 330 is formed in the isolation layer 130.
The recess 330 is formed by using the over-etching process during the over-etching process of the etch stop layer exposed from the initial opening 195, so that the step of forming the recess 330 is integrated with the process of forming the source/drain contact opening 190, which is beneficial to improving the process integration degree and the process compatibility, and the recess 330 is formed in the isolation layer 130 without using an additional photomask, which is beneficial to saving the cost.
In the step of forming the initial opening 195, the etching barrier layer can be used for defining an etching stop position, so that the probability of damage to the source/drain doped region 160 caused by the process of forming the initial opening 195 is reduced, and the integrity and the formation quality of the source/drain doped region 160 are guaranteed.
In this embodiment, before the initial opening 195 is formed, a hard mask layer 180 is further formed on the first dielectric layer 170, and the hard mask layer 180 is used as an etching mask for forming the initial opening 195.
The hard mask layer 180 is made of a material having an etching selectivity with the material of the first dielectric layer 170, for example: silicon nitride, aluminum oxide, aluminum nitride, tantalum nitride, and the like.
As an embodiment, an anisotropic dry etching process is adopted, and the hard mask layer 180 is used as a mask to perform a main etching process on the source/drain doped regions 160 and the first dielectric layer 170 on the isolation layer 130 located between the adjacent source/drain doped regions 160 along the second direction D2. The anisotropic dry etching process has the characteristic of anisotropic etching, and the etching precision and the process controllability are high, thereby being beneficial to ensuring that the position, the size and the appearance of the initial opening 195 meet the process requirements.
As an embodiment, a wet etching process is used to perform an over-etching (over etch) process on the etch stop layer exposed by the initial opening 195 and the isolation layer 130. The wet etching process has the characteristic of isotropic etching, so that the etching barrier layer on the surface of the source-drain doped region 140 is easily removed, and the wet etching process is easy to realize a larger etching selection ratio, so that the damage to the source-drain doped region 140 is favorably reduced.
In other embodiments, other etching processes (e.g., a dry etching process) may be used to perform an over-etching (over-etching) process on the etching barrier layer and the isolation layer exposed by the initial opening.
As shown in fig. 11 and 12, fig. 11 is a schematic perspective view, and fig. 12 is a schematic sectional view of fig. 11 along a direction d-d2, and the source-drain contact structure 300 is formed in the source-drain contact opening 190.
In this embodiment, in the step of forming the source-drain contact structure 300, the source-drain contact structure 300 is filled in the recess 330 and the source-drain contact opening 190.
As an embodiment, an electrochemical plating process is adopted to form the source-drain contact structure 300 in the recess 330 and the source-drain contact opening 190. The electrochemical plating process forms the source-drain contact structure 300 on the seed layer (not shown) in a Bottom-up growth manner, so that the source-drain contact structure 300 can grow based on the topography of the source-drain contact opening 190 and the recess 330, and the top surface of the second portion 320 in the source-drain contact structure 300 is higher than the top surface of the first portion 310, thereby omitting the step of removing the source-drain contact structure material on the isolation layer 130 between the adjacent source-drain doped regions 160 along the second direction D2, and being beneficial to reducing the probability of generating defects such as voids in the source-drain contact structure 300; in addition, the cost of the electroplating process is low, and in addition, the efficiency of forming the source-drain contact structure 300 is improved by adopting the electroplating process, so that the process time is saved and the production and manufacturing efficiency is improved.
In this embodiment, the source-drain contact structure 300 formed by an electrochemical plating process is taken as an example for description. In other embodiments, other process steps may also be adopted to form the source-drain contact structure.
For example: the step of forming the source-drain contact structure in the source-drain contact opening may further include: filling a conductive material in the source-drain contact opening; and removing part of the thickness of the conductive material on the isolation layer between the source and drain doped regions adjacent to the device region, wherein the residual conductive material on the source and drain doped regions is used as the first part, and the residual conductive material on the isolation layer and connected with the first part is used as the second part.
Wherein the step of forming the conductive material may include one or more of an electrochemical plating process, a chemical vapor deposition process, and a physical vapor deposition process.
In this embodiment, the first portion 310 and the second portion 320 define a recess 301 therebetween; referring to fig. 13, 14 and 15, fig. 13 is a cross-sectional view, fig. 14 is a schematic perspective view, and fig. 15 is a cross-sectional view taken along a direction d-d2 in fig. 14, the method further includes: and filling a second dielectric layer 360 in the groove 301.
The second dielectric layer 360 is filled in the groove 301, so as to provide a flat surface for the subsequent process.
The material of the second dielectric layer 360 is an electrically insulating material. The second dielectric layer 360 is made of silicon oxide. The material of the second dielectric layer 360 may also be other insulating materials.
In this embodiment, the step of forming the second dielectric layer 360 includes: as shown in fig. 13, a dielectric material layer 350 is filled in the groove 301, and the dielectric material layer 350 is further formed on the hard mask layer 180; as shown in fig. 14 and 15, the dielectric material layer 350 above the top surface of the first dielectric layer 170 is removed, and the dielectric material layer 350 filled in the groove 301 is left to serve as the second dielectric layer 360.
Specifically, the dielectric material layer 350 may be formed by one or more of a chemical vapor deposition process, an atomic layer deposition process, a flow-type chemical vapor deposition process, a high aspect ratio deposition process, and a plasma enhanced chemical vapor deposition process.
In this embodiment, a planarization process is used to remove the dielectric material layer 350 above the top surface of the first dielectric layer 170.
In the step of removing the dielectric material layer 350 higher than the top surface of the first dielectric layer 170, the hard mask layer 180 and the source-drain contact structure 300 higher than the top surface of the first dielectric layer 170 are also removed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A semiconductor structure, comprising:
the substrate comprises a substrate and a plurality of protruding structures which are separated from the substrate, wherein the protruding structures extend along a first direction and are arranged at intervals along a second direction, and each protruding structure comprises a protruding part and a channel structure positioned on the protruding part; the substrate comprises a plurality of device regions arranged along a second direction;
the isolation layer is positioned on the substrate, surrounds the bulge part and exposes the channel structure;
a device gate structure located on the isolation layer and crossing the channel structure;
the source-drain doped region is positioned in the channel structures at two sides of the grid structure of the device;
and the source-drain contact structure is positioned on two sides of the device grid structure and is in contact with a plurality of source-drain doped regions adjacent to the device region along the second direction, the source-drain contact structure comprises first parts positioned on the source-drain doped regions and second parts which are positioned on the isolation layers between the adjacent first parts along the second direction and are connected with the adjacent first parts, and the top surfaces of the second parts are lower than the top surfaces of the first parts.
2. The semiconductor structure of claim 1, wherein the source drain contact structure is a unitary structure.
3. The semiconductor structure of claim 1, wherein a material of the source drain contact structure comprises one or more of Co, W, ru, al, ir, rh, os, pd, cu, pt, ni, ta, taN, ti, and TiN.
4. The semiconductor structure of claim 1, further comprising: the first dielectric layer is positioned on the isolation layer at the side part of the device grid structure and covers the source-drain doped region;
the grid side wall is positioned on the side wall of the grid structure of the device;
the source-drain contact structure is positioned in the first dielectric layers on two sides of the grid structure and the grid side wall.
5. The semiconductor structure of claim 1, wherein a recess is defined between the first portion and the second portion; the semiconductor structure further includes: and the second dielectric layer is filled in the groove.
6. The semiconductor structure of claim 1, wherein a recess is formed in the isolation layer between the source and drain doped regions adjacent to the device region along the second direction; the second portion also fills in the recess.
7. The semiconductor structure of claim 1, wherein a height difference between the second portion and a top surface of the first portion is 5nm to 100nm.
8. The semiconductor structure of claim 4, wherein the gate sidewall spacer material comprises: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, boron carbonitride, low k materials, and ultra low k materials.
9. The semiconductor structure of claim 1, wherein the raised structure is a fin and the channel structure is an active fin; the device grid electrode structure covers part of the top and part of the side wall of the fin part;
or the channel structure is arranged on the lug boss at intervals in a hanging manner, the channel structure comprises one or more channel layers which are sequentially arranged at intervals in a hanging manner, and the stacking direction of the channel layers is vertical to the surface of the substrate; the device gate structure surrounds the channel layer.
10. The semiconductor structure of claim 1, wherein the material of the substrate comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;
the material of the convex part comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;
the material of the channel structure comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;
the isolation layer is made of one or more materials selected from silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon germanium oxide, boron nitride and boron carbonitride.
11. The semiconductor structure of claim 1, wherein the device gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.
12. The semiconductor structure of claim 11, wherein the gate dielectric layer comprises a material comprising:
HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2 O 3 、Al 2 O 3 one or more of silicon oxide and nitrogen-doped silicon oxide;
the material of the gate electrode layer comprises: any one or more of TiAl, tiALC, taAlN, tiAlN, moN, taCN, alN, ta, tiN, taN, taSiN, tiSiN, W, co, al, cu, ag, au, pt and Ni.
13. A method of forming a semiconductor structure, comprising:
providing a substrate and a plurality of raised structures separated on the substrate, wherein the raised structures extend along a first direction and are arranged at intervals along a second direction, and each raised structure comprises a raised part and a channel structure positioned on the raised part; the substrate comprises a plurality of device regions arranged along a second direction; an isolation layer surrounding the protruding portion is formed on the substrate, and the isolation layer exposes the channel structure;
forming a device grid structure which is positioned on the isolation layer and crosses the channel structure, and source-drain doped regions which are positioned in the channel structure at two sides of the device grid structure;
and forming source-drain contact structures on two sides of the device gate structure, wherein the source-drain contact structures are in contact with a plurality of source-drain doped regions adjacent to the device regions along the second direction, each source-drain contact structure comprises a first part and a second part, the first parts are positioned on the source-drain doped regions, the second parts are positioned on the isolation layers between the adjacent first parts along the second direction and are connected with the adjacent first parts, and the top surfaces of the second parts are lower than the top surfaces of the first parts.
14. The method for forming a semiconductor structure according to claim 13, wherein the step of forming the source-drain contact structure comprises: forming source-drain contact openings on two sides of the device grid structure, and exposing the source-drain doped regions adjacent to the device region along the second direction and the isolation layer positioned between the source-drain doped regions adjacent to the device region along the second direction;
and forming the source-drain contact structure in the source-drain contact opening.
15. The method for forming a semiconductor structure according to claim 14, wherein in the step of forming the source-drain contact opening, a recess is formed in the isolation layer exposed at the bottom of the source-drain contact opening;
and in the step of forming the source-drain contact structure, the source-drain contact structure is filled in the recess and the source-drain contact opening.
16. The method for forming a semiconductor structure according to claim 15, wherein in the step of forming the device gate structure and the source-drain doped region, an etching barrier layer is formed on the source-drain doped region and the isolation layer, and a first dielectric layer covering the etching barrier layer is formed on a side portion of the device gate structure;
the step of forming the source-drain contact opening and the recess includes: performing main etching treatment on the source-drain doped regions and the first dielectric layer on the isolation layer between the adjacent source-drain doped regions along the second direction to form an initial opening, wherein the etching barrier layer is exposed out of the initial opening; performing over-etching treatment on the etching barrier layer exposed out of the initial opening to form the source-drain contact opening in the first dielectric layer; and in the process of carrying out over-etching treatment, carrying out over-etching treatment on the isolation layer below the initial opening to form the recess in the isolation layer.
17. The method for forming a semiconductor structure according to claim 14 or 15, wherein the step of forming the source-drain contact structure in the source-drain contact opening includes: filling a conductive material in the source-drain contact opening;
and removing part of the thickness of the conductive material on the isolation layer between the source-drain doped regions adjacent to the device region, wherein the residual conductive material on the source-drain doped regions is used as the first part, and the residual conductive material on the isolation layer and connected with the first part is used as the second part.
18. The method for forming a semiconductor structure of claim 13, wherein the process for forming the source drain contact structure comprises an electrochemical plating process.
19. The method of forming a semiconductor structure of claim 13, wherein a recess is defined between the first portion and the second portion; the forming method of the semiconductor structure further comprises the following steps: and filling a second dielectric layer in the groove.
20. The method for forming a semiconductor structure according to claim 13, wherein a gate spacer is further formed on the sidewall of the device gate structure;
in the step of forming the source-drain contact structure, the source-drain contact structure is located on two sides of the device grid structure and the grid side wall.
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