CN111223932B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN111223932B CN111223932B CN201811420138.1A CN201811420138A CN111223932B CN 111223932 B CN111223932 B CN 111223932B CN 201811420138 A CN201811420138 A CN 201811420138A CN 111223932 B CN111223932 B CN 111223932B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 62
- 210000000746 body region Anatomy 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims description 58
- 230000004888 barrier function Effects 0.000 claims description 46
- 238000005468 ion implantation Methods 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 27
- 230000000903 blocking effect Effects 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000002955 isolation Methods 0.000 description 16
- 239000012535 impurity Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000012212 insulator Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- NWLLPIVESIULPG-UHFFFAOYSA-N dysprosium indium Chemical compound [In].[Dy] NWLLPIVESIULPG-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention provides a semiconductor device and a forming method thereof. In the embodiment of the invention, a part of the doped region and a part of the body region below the doped region are etched to form a first source region and a second source region which are separated from each other and a second groove for isolating the first source region and the second source region; forming a pick-up region with opposite doping types to the first source region and the second source region at the bottom of the second groove; and forming metal silicide on the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively and electrically connected with the pickup region. Thereby, the pickup capability of the body region of the semiconductor device can be improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
Semiconductor devices are electronic devices that have electrical conductivity between good electrical conductors and insulators, and that utilize the specific electrical characteristics of semiconductor materials to perform specific functions, and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. The conventional semiconductor device includes: field effect transistors, bipolar transistors, transistor diodes, and the like. Among them, laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) is widely used in power integrated circuits because it is more easily compatible with the logic process of complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductors, CMOS). However, the pickup capability of the body region of the existing semiconductor device is to be improved.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to improve the pickup capability of the semiconductor device.
According to an aspect of an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method including:
providing a semiconductor substrate, wherein a body region, a first drift region and a second drift region are formed in the semiconductor substrate, the first drift region and the second drift region are positioned at two sides of the body region, a gate structure layer is positioned on the body region, and a barrier layer covers the gate structure layer, wherein a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region;
etching the barrier layer and the gate structure layer in a predetermined region to form a first groove exposing the body region and a first gate structure and a second gate structure separated by the first groove;
performing ion implantation on the body region exposed in the first groove to form a doped region in the body region, wherein the doped region has a first doping type;
etching part of the doped region and part of the body region below the doped region to form a first source region and a second source region which are separated from each other and a second groove for isolating the first source region and the second source region;
Ion implantation is carried out on the bottom of the second groove, and a pickup area with a second doping type is formed on the bottom of the second groove;
patterning the barrier layer;
and forming metal silicide through a self-alignment process, wherein the metal silicide at least covers the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively and electrically connected with the pickup region.
Further, the patterning the barrier layer includes: etching the barrier layer over the first gate structure and the second gate structure to form a plurality of holes exposing the first gate structure and a plurality of holes exposing the second gate structure;
the metal silicide formed by the self-aligned process also covers the bottom of the hole.
Further, the patterning the barrier layer further includes: etching the barrier layer above the first drain region and the second drain region to expose the first drain region and the second drain region;
the metal silicide formed through the self-alignment process also covers the first drain region and the second drain region.
Further, the method further comprises:
a floating gate is formed over the blocking layer.
Further, the method further comprises:
Forming contact holes respectively connecting the first drain region, the second drain region, the first gate structure, the second gate structure and the pickup region while forming a floating gate;
and forming an interconnection structure above the contact hole so that the first drain region and the second drain region form an electrical connection.
Further, the method further comprises: before forming the second groove, forming a first side wall covering the side wall of the first grid structure and part of the doped region, and forming a second side wall covering the side wall of the second grid structure and part of the doped region.
Further, the first source region is located below the first side wall, the second source region is located below the second side wall, and the second groove is located between the first side wall and the second side wall.
Further, the first drift region and the second drift region have a first doping type, and the body region has a second doping type.
According to another aspect of an embodiment of the present invention, there is provided a semiconductor device including:
a semiconductor substrate, wherein a body region is formed in the semiconductor substrate, a first drift region and a second drift region are positioned at two sides of the body region, a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region;
A first gate structure covering a portion of the first drift region;
a second gate structure covering a portion of the second drift region;
a first source region and a second source region formed in the body region and separated from each other, the first source region and the second source region having a first doping type;
the body region is provided with a recess, the recess separates a first source region and a second source region, the bottom of the recess is provided with a pickup region, the pickup region is provided with a second doping type, and the side wall of the recess and the surface of the pickup region are provided with metal silicide, so that the first source region and the second source region are respectively electrically connected with the pickup region.
Further, the semiconductor device further includes a barrier layer;
the barrier layer covers the first gate structure and the first drift region, and covers the second gate structure and the second drift region;
wherein a plurality of holes exposing the first gate structure are formed in the blocking layer above the first gate structure, a plurality of holes exposing the second gate structure are formed in the blocking layer above the second gate structure, and metal silicide is formed in the holes.
Further, the semiconductor device further includes:
a floating gate formed over the barrier layer;
the contact holes are respectively connected with the first drain region, the second drain region, the first grid structure, the second grid structure and the pickup region;
and an interconnection structure formed above the contact hole so that the first drain region and the second drain region form an electrical connection.
Further, metal silicide is formed on the first drain region and the second drain region.
Further, the semiconductor device further includes:
the first side wall covers the first grid structure side wall and the first source region;
and the second side wall covers the second grid electrode structure side wall and the second source region.
Further, the recess is located between the first side wall and the second side wall.
In the embodiment of the invention, a part of the doped region and a part of the body region below the doped region are etched to form a first source region and a second source region which are separated from each other and a second groove for isolating the first source region and the second source region; forming a pick-up region with opposite doping types to the first source region and the second source region at the bottom of the second groove; and forming metal silicide on the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively and electrically connected with the pickup region. Thereby, the pickup capability of the body region of the semiconductor device can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic cross-sectional view of a semiconductor device of a comparative example;
fig. 2 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 3 to 14 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 15 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, unless otherwise indicated, "multiple layers" means two or more layers.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Spatially relative terms, such as "under …," "under," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" is intended to encompass both an orientation of above and below. The device may take other orientations (rotated 90 degrees or at other orientations), and the spatial relationship descriptors used herein interpreted accordingly.
The "sidewall" is a surface other than the top and bottom surfaces, and "sidewall covering the gate structure layer" means covering the front, back, left side, and right side of the gate structure layer.
Fig. 1 is a schematic cross-sectional view of a semiconductor device of a comparative example. As shown in fig. 1, the semiconductor device of the comparative example includes: semiconductor substrate 100', first gate structure 31', second gate structure 32', doped region 70', first isolation wall 81', second isolation wall 82', barrier layer 40', metal silicide 90', and contact hole 120'.
The semiconductor substrate 100 'has a body region 10', a first drift region 21 'and a second drift region 22' formed therein on both sides of the body region. Wherein a first drain region 51 'is formed in the first drift region 21', and a second drain region 52 'is formed in the second drift region 22'. The first gate structure 31 'covers a portion of the first drift region 21'. The second gate structure 32 'covers a portion of the second drift region 22'.
The doped region 70 'is formed in the body region 10'. The first isolation wall 81 'covers the sidewall of the first gate structure 31'. The second isolation wall 82 'covers the sidewalls of the second gate structure 32'.
The blocking layer 40 'covers part of the first gate structure 31' and its sidewall and extends to the first drift region 21 'on one side of the first gate structure 31'; and a second drift region 22' covering a portion of the second gate structure 32' and sidewalls thereof and extending to one side of the second gate structure 32 '.
Metal silicide 90' and contact hole 120' for connecting first drain region 51', second drain region 52', first gate structure 31', second gate structure 32', and doped region 70' of the semiconductor device.
In the comparative example, the pickup capability of the doped region 70 'in the body region 10' is not high. Meanwhile, defects are easily formed due to over-etching during the formation of the semiconductor device, which are mainly formed on the side of the first gate structure 31 'near the body region 10' and on the side of the second gate structure 32 'near the body region 10', thereby causing the failure of the semiconductor device.
Fig. 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention, and referring to fig. 2, the method for forming the semiconductor device according to the embodiment of the present invention includes the steps of:
step S100, a semiconductor substrate is provided. The semiconductor substrate is provided with a body region, a first drift region and a second drift region which are positioned at two sides of the body region, a gate structure layer positioned on the body region and a blocking layer covering the gate structure layer, wherein a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region.
Step S200, etching the barrier layer and the gate structure layer in a predetermined region to form a first recess exposing the body region and a first gate structure and a second gate structure separated by the first recess.
And step S300, performing ion implantation on the body region exposed in the first groove, and forming a doped region in the body region. The doped region has a first doping type.
Step S400, etching a portion of the doped region and a portion of the body region to form a first source region and a second source region that are separated and a second recess that isolates the first source region and the second source region.
And S500, performing ion implantation on the bottom of the second groove to form a pickup region with a second doping type at the bottom of the second groove.
Step S600, patterning the barrier layer.
And step S700, forming metal silicide through a self-alignment process. The metal silicide at least covers the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively and electrically connected with the pickup region.
Preferably, the forming method further includes:
step S800, forming a Contact (CT).
And step 900, forming an interconnection structure of the upper layer of the contact hole.
Fig. 3 to 14 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention. An example of forming an LDMOS is illustrated in fig. 3-14. It should be appreciated that the forming steps of embodiments of the present invention may also be used to form other semiconductor devices requiring the provision of a pick-up region. Fig. 3 is a schematic view of a semiconductor substrate, referring to fig. 3, in step S100, a semiconductor substrate 100 is provided, a body region 10 is formed in the semiconductor substrate 100, a first drift region 21 and a second drift region 22 are located at both sides of the body region 10, a gate structure layer 30 is located on the body region, and a barrier layer 40 covers the gate structure layer 30, wherein a first drain region 51 is formed in the first drift region 21, and a second drain region 52 is formed in the second drift region 22.
In an alternative implementation, when the LDMOS formed is a P-type LDMOS, P-type impurity ions are doped in the first drift region 21 and the second drift region 22, P-type impurity ions are doped in the first drain region 51 and the second drain region 52, N-type impurity ions are doped in the body region 10, and P-type impurity ions are doped in the first source region 71 and the second source region 72. The pickup region 83 is doped with N-type impurity ions. In another alternative implementation manner, when the LDMOS formed is an N-type LDMOS, the first drift region 21 and the second drift region 22 are doped with N-type impurity ions, the first drain region 51 and the second drain region 52 are doped with N-type impurity ions, the body region 10 is doped with P-type impurity ions, the pickup region 83 is doped with N-type impurity ions, and the first source region 71 and the second source region 72 are doped with N-type impurity ions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions.
The semiconductor substrate 100 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a silicon-on-epitaxial layer structure substrate, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. The semiconductor substrate can also comprise other materials, such as an epitaxial layer or a multilayer structure of a buried layer, and a plurality of structures such as an epitaxial interface layer or a strain layer can also be formed on the surface of the semiconductor substrate so as to improve the electrical performance of the semiconductor device.
The body region 10, the first drift region 21 and the second drift region 22 within the semiconductor substrate 100 are formed by an ion implantation process. The doping concentration of the first drift region 21 and the second drift region 22 is low, the resistance is high, and the first drift region and the second drift region can bear higher voltage. Meanwhile, the first drift region 21 and the second drift region 22 play a role in buffering between the gate and the drain region, so that the short channel effect of the LDMOS is weakened.
More specifically, the process of forming the first drift region 21 and the second drift region 22 includes: before forming the first drift region 21 and the second drift region 22, a mask layer is formed on the semiconductor substrate 100, the mask layer exposes a region to be implanted, and corresponding ion implantation is performed on the region to be implanted.
The process of forming the body region 10 may include: before forming the body region 10, a mask layer is formed on the semiconductor substrate 100, the mask layer exposing a region to be implanted, and corresponding ion implantation is performed on the region to be implanted.
The gate structure layer 30 covers the body region 10 and the first drift region 21 and the second drift region 22 adjacent to the body region 10, and the gate structure layer 30 includes a gate dielectric layer 301 and a gate electrode layer 302 on the gate dielectric layer 301.
Alternatively, the material of the gate dielectric layer 301 may be silicon dioxide (SiO 2 ) Or high-K dielectric materials, e.g. zirconia (ZrO 2 ) Alumina (Al) 2 O 3 ) Or hafnium oxide (HfO) 2 ) Etc. Preferably, the gate dielectric layer 301 may include a stacked silicon oxide layer and a high-K dielectric material layer. The material of the gate electrode layer 302 may be polysilicon or metal such as tungsten (W), copper (Cu), aluminum (Al), and the like.
Preferably, a protection wall (not shown) covering the sidewall of the gate structure layer 30 is formed around the gate structure layer 30. The protection wall can protect the side wall of the gate structure layer 30 from being damaged during the subsequent process of the drain region ion implantation, and simultaneously isolate the first gate structure formed in the subsequent process from the first drain region and isolate the second gate structure from the second drain region, thereby avoiding short circuit.
The first drain region 51 is formed in the first drift region 21 not covered by the gate structure layer, the second drain region 52 is formed in the second drift region 22 not covered by the gate structure layer, and the first and second drain regions 51 and 52 may be formed by ion implantation.
The barrier layer 40 covers the gate structure layer 30, and the material of the barrier layer 40 may be silicon dioxide (SiO 2 ) Silicon nitride (Si) 3 N 4 ) Silicon-rich silicon dioxide (Silicon Rich Oxide, SRO), silicon oxynitride (SiON), etc., preferably silicon-rich silicon dioxide and silicon nitride (Si) 3 N 4 ). Because silicon-rich silicon dioxide is relative to silicon dioxide (SiO 2 ) Has a high extinction coefficient, and thus can avoid the influence on other structures in the subsequent dry etching process, while silicon nitride (Si 3 N 4 ) Has good compactness and can play an isolating role in the subsequent etching process.
As shown in fig. 4, in an alternative implementation, a Buried Layer (Buried Layer) 101, a reverse ion implantation Layer 102, a first intermediate pressure well region 103, a second intermediate pressure well region 104, and a shallow trench isolation structure 107 are further formed in the semiconductor substrate 100.
The material of the buried layer 101 is typically silicon dioxide (SiO 2 ) The thickness is about 100nm to 1 μm, so the Buried layer 101 is also referred to as a Buried Oxide (BOX). The buried layer 101 can prevent excessive electrons from leaking onto the underlying semiconductor substrate 100.
The reverse ion implantation layer 102 is located under the body region 10, the first drift region 21, and the second drift region 22, and is connected to the body region 10, the first drift region 21, and the second drift region 22. The doping type of the reverse ion implantation layer 102 is opposite to the doping type of the first drift region 21 and the second drift region 22. Therefore, a PN junction is formed between the first drift region 21 and the second drift region 22 of the reverse ion implantation layer 102, and the PN junction can play a role in suppressing leakage current.
The first medium voltage well region 103 is located at the sides of the first drift region 21 and the reverse ion implantation layer 102, and at the sides of the second drift region 22 and the reverse ion implantation layer 102. The doping type of the medium voltage well region 103 is the same as that of the reverse ion implantation layer 102. The medium voltage well region 103 can prevent leakage current from entering the semiconductor substrate 100.
The first intermediate voltage well region 103 is used to connect a control potential for controlling the potential of the intermediate voltage well region 103, thereby further enhancing the ability to prevent current flow into the semiconductor substrate 100.
The second medium voltage well region 104 is located at the side of the first medium voltage well region 103, and a gap is arranged between the first well region 103 and the second well region 104 to form a discontinuous well region, so that the source-drain breakdown voltage of the device is improved, and the performance of the device is further improved.
The second intermediate voltage well region 104 is used to connect a control potential for controlling the potential of the intermediate voltage well region 104, thereby further enhancing the ability to prevent current flow into the semiconductor substrate 100.
A first ohmic contact region 105 is formed on the surface of the first intermediate voltage well region 103, and a second ohmic contact region 106 is formed on the surface of the second intermediate voltage well region 104. The first ohmic contact region 105 and the second ohmic contact region 106 may function to reduce contact resistance.
A shallow trench isolation structure 107 is formed in a region of the first intermediate voltage well region 103 adjacent to the first drift region 21, and a shallow trench isolation structure 107 is formed in a region of the first intermediate voltage well region 103 adjacent to the second drift region 22. The shallow trench isolation structure 107 may enhance the insulation of the region of the first medium voltage well region 103 adjacent to the first drift region 21 and the insulation of the region of the first medium voltage well region 103 adjacent to the second drift region 22.
Referring to fig. 5, in step S200, the barrier layer 40 and the gate structure layer 30 of a predetermined region are etched. To form a first recess 60 exposing the body region 10 and a first gate structure 31 and a second gate structure 32 separated by the first recess 60. The first gate structure 31 includes a first gate dielectric layer 311 and a first gate electrode layer 312 on the first gate dielectric layer 311. The second gate structure 32 includes a second gate dielectric layer 321 and a second gate electrode layer 322 on the second gate dielectric layer 321.
Specifically, photoresist is uniformly coated on the surface of a semiconductor substrate, then the photoresist is patterned to form a mask layer having an opening pattern in a predetermined region, then the predetermined region not covered by the photoresist is etched to expose a body region, and separate first and second gate structures 31 and 32 are formed, and finally the photoresist is removed.
The etching process may be performed by an etching method known to those skilled in the art, such as dry etching, wet etching, etc. Preferably, a dry etching is used to etch the barrier layer 40 and the gate structure layer 30 in predetermined regions, the dry etching may select an etching gas according to a selected material, and CHF may be selected 3 ，SF 6 ，CF 4 ，CF 4 /O 2 And CF (compact F) 4 /H 2 Etc. as an etching gas. In embodiments of the present invention, CHF is preferably used 3 As an etching gas, the etching pressure may be 5 to 300mTorr, preferably 8 to 10mTorr.
By etching the gate structure layer 30, the first gate structure 31 and the second gate structure 32 can be formed simultaneously in one step, which can save the process flow and improve the production efficiency.
Referring to fig. 6, in step S300, ion implantation is performed on the body region 10 exposed in the first recess 60, and a doped region 70 is formed in the body region 10. The doped region 70 has a first doping type.
In an alternative implementation, when the ion implantation impurity ion is one or more of phosphorus (P) ion, arsenic (As) ion and antimony (Te) ion, the implantation angle of ion implantation is 0-5 DEG, and the implantation dosage is 5E13atom/cm 2 ～5E15atom/cm 2 The implantation energy is 6Kev to 50Kev. In another alternative implementation, when the impurity ions implanted by ion implantation are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions, the implantation angle of ion implantation is 0-5 degrees, and the implantation dose is 5E13 atoms/cm 2 ～5E15atom/cm 2 The implantation energy is 12Kev to 50Kev.
It should be appreciated that the process parameters of ion implantation are not limited to the above-described process parameters, but may be adjusted according to different equipment and different semiconductor device structure and performance requirements.
Referring to fig. 7, in step S400, portions of the doped regions 70 and portions of the body region 10 are etched to form discrete first and second source regions 71 and 72 and second recesses 80 isolating the first and second source regions.
The doped region 70 may be etched by coating a photoresist, then patterning the photoresist to form a mask layer having an opening pattern in a predetermined region, then etching the predetermined region not covered by the photoresist, and etching a portion of the body region 10 to extend into the body region 10.
In a preferred implementation, referring to fig. 8 and 9, before etching the doped region 70, a first side wall 81 and a second side wall 82 covering an inner wall of the first groove may be formed in advance, and a forming process of the first side wall 81 and the second side wall 82 includes:
s410, as shown in fig. 8, a sidewall material layer (not labeled in the figure) is deposited. The sidewall material layer covers the barrier layer 40 and the sidewalls of the first recess 60.
S420, etching a preset area of the side wall material layer to form a first side wall 81 and a second side wall 82 as shown in FIG. 9.
Specifically, the first sidewall 81 covers a side surface of the first gate structure 31, and the second sidewall 82 covers a side surface of the second gate structure 32. The first and second side walls 81 and 82 may be made of silicon nitride (Si 3 N 4 ). The first sidewall 81 and the second sidewall 82 can protect the first gate structure 31 and the second gate structure 32 during the subsequent ion implantation process.
Preferably, the first sidewall 81 covers the side surface of the first gate structure 31 and extends to the side surface of the barrier layer 40, and the second sidewall 82 covers the side surface of the second gate structure 32 and extends to the side surface of the barrier layer 40, so that the first gate structure 31 and the second gate structure 32 can be better protected during the subsequent patterning of the barrier layer 40.
Referring to fig. 10, in step S500, ion implantation is performed on the bottom of the second recess 80 to form a pickup region 83 having the second doping type at the bottom of the second recess 80. The doping type of the pickup region 83 is opposite to that of the first source region 71 and the second source region 72. The doping type of the pickup region 83 is the same as the doping type of the body region 10, and the doping concentration of the pickup region 83 is greater than the doping concentration of the body region 10.
Referring to fig. 11 and 12, fig. 12 is a top view of the semiconductor structure shown in fig. 11. In step S600, the barrier layer 40 is patterned. The first drain region 51 and the second drain region 52 are exposed. In an alternative implementation, the patterned barrier layer 40 covers part of the first gate structure 31 and extends to the first drift region 21, and part of the second gate structure 32 and extends to the second drift region 22.
Specifically, patterning the barrier layer 40 includes: uniformly coating photoresist on the surface of a semiconductor substrate, patterning the photoresist to form a mask layer with an opening pattern in a preset area, etching the preset area which is not covered by the photoresist, and finally removing the photoresist. Preferably, the etched barrier layer exposes the first drain region 51 and the second drain region 52. Meanwhile, a hole 41 exposing the first gate structure 31 and the second gate structure 32 is formed in the blocking layer 40 over the first gate structure 31 and the second gate structure 32. Further preferably, the etched barrier layer 40 also exposes the first ohmic contact region 105 and the second ohmic contact region 106.
The hole 41 electrically connects the gate structure to the contact hole during the subsequent formation of the contact hole. Forming the hole 41 over the gate structure instead of forming the groove structure can avoid over etching during etching to damage the edge of the gate structure, thereby causing problems such as short circuit, and reducing the yield of the semiconductor device.
Referring to fig. 13, in step S700, a metal silicide 90 is formed by a self-aligned process. The metal silicide 90 covers at least the sidewalls and bottom of the second recess 80 so that the first source region 71 and the second source region 72 are electrically connected to the pickup region 83, respectively. Preferably, the metal silicide 90 also covers the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 52, the second gate structure 32, the first well region 103 and the second well region 104.
The metal silicide 90 may reduce contact resistance between a subsequently formed contact hole and the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 52, the second gate structure 32, the first well region 103, and the second well region 104.
The Salicide formation process (Salicide) comprises the steps of: first a metal layer, such as nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt) or a combination thereof, is deposited, preferably cobalt (Co). An anneal process, preferably a rapid anneal process (Rapid Thermal Annealing, RTA), is performed to react the deposited metal layer with the silicon to form metal silicide 90. And finally removing redundant metal. Wherein the barrier layer 40 may function as a metal silicide barrier layer (Salicide Block Layer, SAB) without forming a metal silicide during the process of performing the self-alignment.
Metal silicide is formed on the sidewalls and bottom surface of the second recess 80 so that the first source region 71 and the second source region 72 are electrically connected to the pickup region 83, respectively. Therefore, only the contact hole for connecting the pick-up region 83 is required to be formed, so that the drain regions of the two LDMOS transistors can be electrically connected with an external device through the contact hole, namely, the two LDMOS transistors share one drain electrode, and the size of the LDMOS transistor can be reduced. A PN junction is formed between the first source region 71 and the pickup region 83, and reverse breakdown is not formed, which can contribute to uniform current conduction, effectively achieving better performance.
In some comparative examples, the pickup region is located between the first source region and the second source region, adjacent to the first source region and the second source region, and the second recess is not formed, and defects are easily formed during ion implantation, such as a problem that contact resistance between adjacent first source region and pickup region is excessively large. In this embodiment, the pickup area is at the bottom of the second groove and is lower than the first source area and the second source area, the pickup area is isolated from the first source area and the second source area in the forming process, metal silicide is formed in the second groove, and the first source area is electrically connected with the second source area and the pickup area through the metal silicide, so that the pickup area and the first source area and the second source area can be ensured to form better electrical contact, and the problem of overlarge contact resistance is avoided.
Referring to fig. 14, in step S800, the contact hole 120 is formed. The process of forming the contact hole 120 includes:
step S810, forming a dielectric layer 110 covering the semiconductor structure formed in step S700.
Step S820, patterning the dielectric layer 110, and forming a through hole exposing the metal silicide on the surfaces of the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 52, the second gate structure 32, the first well region 103 and the second well region 104 in the dielectric layer 110.
Step S830, forming a conductive material in the through hole.
In an alternative implementation, a dielectric layer 110 is formed to cover the semiconductor substrate 100, the dielectric layer 110 is patterned, and a contact hole 120 is formed in the dielectric layer 110 to connect the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 52, the second gate structure 32, the first well region 103 and the second well region 104.
The contact hole 120 is used to connect the subsequently formed interconnection structure with the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 52, the second gate structure 32, the first well region 103 and the second well region 104, so that the interconnection structure is electrically connected with the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 52, the second gate structure 32, the first well region 103 and the second well region 104 through the contact hole 120.
Further preferably, at the same time of patterning the dielectric layer in step S820 of forming the contact hole 120, a hole exposing the barrier layer 40 is also formed in the dielectric layer 110; step S830 of forming the contact hole 120 deposits a metal in the hole exposing the barrier layer 40 to form the floating gate 130 while depositing a conductive material in the hole.
The floating gate 130 can make the electric field distribution uniform, adjust the lateral electric field of the LDMOS transistor device, and improve the withstand voltage of the semiconductor device.
The material of the dielectric layer 110 may be silicon oxide, silicon oxynitride or silicon oxycarbide, preferably silicon oxide. The dielectric layer 110 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) as is commonly used in the art, such as low temperature chemical vapor deposition (LowTemperature Chemical Vapor Deposition, LTCVD), plasma chemical vapor deposition (Plasma Chemical Vapor Deposition, PCVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).
The patterned dielectric layer 110 may be formed by dry etching or wet etching, etc., to form a via hole exposing the metal silicide on the surfaces of the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 52, the second gate structure 32, the first well region 103, and the second well region 104.
The conductive material may be copper (Cu) or aluminum (Al) or the like having high conductivity. The process of depositing metal in the via hole may be selected from chemical vapor deposition methods commonly used in the art, such as low temperature chemical vapor deposition, plasma chemical vapor deposition process, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.
In step S900, an interconnection structure (not shown) of an upper layer of the contact hole 120 is formed. The forming process of the interconnection structure comprises the following steps:
s910, an isolation layer is formed to cover the dielectric layer 110.
S920, forming a patterned photoresist layer on the upper surface of the isolation layer. To expose the isolation layer of the portion to be etched.
S930, etching the isolation layer to form a patterned groove structure.
S940, forming a conductive material in the groove structure. To form an interconnect structure connected to the contact hole 120.
The conductive material forming the interconnection structure may be a metal material such as copper (Cu) or aluminum (Al) having high conductivity.
The interconnect structure electrically connects the first drain region 51 and the second drain region 52, and electrically connects the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 52, the second gate structure 32, the floating gate 130, the first well region 103, the second well region 104, and the like with external devices.
The first drain region 51 and the second drain region 52 are electrically connected through an interconnection structure; meanwhile, the first gate structure 31 and the second gate structure 32 are electrically connected; in addition, the drain regions of the two LDMOS transistors are electrically connected with the pickup region at the same time, which is equivalent to the two LDMOS transistors sharing one drain. Therefore, the two LDMOS transistors can be connected in parallel, and the breakdown voltage can be further improved.
According to another embodiment of the present invention, there is also provided a semiconductor device including: a semiconductor substrate 100, a first gate structure 31, a second gate structure 32, a first source region 71 and a second source region 72.
The semiconductor substrate 100a has a body region 10a formed therein, a first drift region 21a and a second drift region 22a located on both sides of the body region 10a, wherein the first drift region 21a has a first drain region 51a formed therein, and the second drift region 22a has a second drain region 52a formed therein.
The first gate structure 31a covers a portion of the first drift region 21a; the second gate structure 32a covers a portion of the second drift region 22a.
The first source region 71a and the second source region 72a are formed in the body region 10a and are separated from each other, the first source region 71a and the second source region 72a having a first doping type. A recess 160a is formed in the body region 10a, the recess 160a separating the first source region 71a and the second source region 72a, a pickup region 83a is formed at the bottom of the recess, the pickup region 83a has a second doping type, and a metal silicide 90a is formed on the sidewall of the recess 160a and the surface of the pickup region 83a such that the first source region 71a and the second source region 72a are electrically connected to the pickup region 83a, respectively.
As shown in fig. 15, in a preferred embodiment, the semiconductor device further includes: barrier layer 40a, floating gate 130a, contact hole 120a, interconnect structure (not shown), first sidewall 81a, and second sidewall 82a.
A body region 10a and a first drift region 21a and a second drift region 22a are formed in the semiconductor substrate 100a, wherein the first drift region 21a has a first drain region 51a formed therein, and the second drift region 22a has a second drain region 52a formed therein; wherein a recess 160a is formed in the body region 10a, the recess 160a separates the first source region 71a and the second source region 72a, a pickup region 83a is formed at the bottom of the recess 160a, the pickup region 83a has a second doping type, and a metal silicide is formed on the sidewall of the recess 160a and the surface of the pickup region 83a, so that the first source region 71a and the second source region 72a are electrically connected to the pickup region 83a, respectively.
The semiconductor substrate 100a may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100a may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. The semiconductor substrate can also comprise other materials, such as an epitaxial layer or a multilayer structure of a buried layer, and a plurality of structures such as an epitaxial interface layer or a strain layer can also be formed on the surface of the semiconductor substrate so as to improve the electrical performance of the semiconductor device.
Preferably, the semiconductor substrate 100a further has a buried layer 101a, a reverse ion implantation layer 102a, a first intermediate voltage well region 103a, a second intermediate voltage well region 104a, and a shallow trench isolation structure 107a formed therein.
The material of the buried layer 101a is typically silicon oxide with a thickness of about 100nm to 1 μm, so the buried layer 101a is also referred to as a buried oxide layer. The buried layer 101a can prevent excessive electrons from leaking onto the underlying semiconductor substrate 100a.
The reverse ion implantation layer 102a is located under the body region 10a, the first drift region 21a, and the second drift region 22a, and is connected to the body region 10a, the first drift region 21a, and the second drift region 22 a. The doping type of the reverse ion implantation layer 102a is opposite to the doping type of the first drift region 21a and the second drift region 22 a. Therefore, a PN junction is formed between the first drift region 21a and the second drift region 22a of the reverse ion implantation layer 102a, and the PN junction can play a role in suppressing leakage current.
The first middling region 103a is located at the sides of the first drift region 21a and the reverse ion implantation layer 102a, and at the sides of the second drift region 22a and the reverse ion implantation layer 102 a. The doping type of the medium voltage well region 103 is the same as that of the reverse ion implantation layer 102 a. The medium voltage well region 103a can prevent leakage current from entering the semiconductor substrate 100a.
The first intermediate voltage well region 103a is used to connect a control potential for controlling the potential of the intermediate voltage well region 103a, thereby further enhancing the ability to prevent current from flowing into the semiconductor substrate 100 a.
The second medium voltage well region 104a is located at the side of the first medium voltage well region 103a, and a gap is arranged between the first well region 103a and the second well region 104a to form a discontinuous well region, so that the source-drain breakdown voltage of the device is improved, and the performance of the device is further improved.
The second intermediate voltage well region 104a is used to connect a control potential for controlling the potential of the intermediate voltage well region 104a, thereby further enhancing the ability to prevent current from flowing into the semiconductor substrate 100 a.
A first ohmic contact region 105a is formed on the surface of the first intermediate voltage well region 103a, and a second ohmic contact region 106a is formed on the surface of the second intermediate voltage well region 104 a. The first ohmic contact region 105a and the second ohmic contact region 106a may function to reduce contact resistance.
A shallow trench isolation structure 107 is formed in a region of the first intermediate voltage well region 103a adjacent to the first drift region 21a, and a shallow trench isolation structure 107 is formed in a region of the first intermediate voltage well region 103a adjacent to the second drift region 22 a. The shallow trench isolation structure 107 may enhance the insulation of the region of the first medium voltage well region 103a adjacent to the first drift region 21a and the insulation of the region of the first medium voltage well region 103a adjacent to the second drift region 22 a.
The first gate structure 31a covers a portion of the first drift region 21a. The first gate structure 31a includes a first gate dielectric layer 311a and a first gate electrode layer 312a on the first gate dielectric layer 311 a.
The second gate structure 32a covers a portion of the second drift region 22a. The second gate structure 32a includes a second gate dielectric layer 321a and a first gate electrode layer 322a on the second gate dielectric layer 321 a.
The first source region 71a and the second source region 72a are formed in the body region 10a and are separated from each other, the first source region 71a and the second source region 72a having a first doping type.
A blocking layer 40a, said blocking layer 40a covering the first gate structure 31a and said first drift region 21a and covering the second gate structure 32a and said second drift region 22a. Preferably, a plurality of holes 41a exposing the first gate structure are formed in the blocking layer 40a above the first gate structure, a plurality of holes 41a exposing the second gate structure are formed in the blocking layer 40a above the second gate structure, and a metal silicide is formed in the holes 41 a.
The first sidewall covers the first gate structure sidewall and the first source region. And the second side wall covers the side wall of the second grid electrode structure and the second source region. The recess is located between the first side wall and the second side wall.
The first and second side walls 81a and 82a may be made of silicon nitride (Si) 3 N 4 ). The first sidewall 81a serves to protect the first gate structure 31a during the process of forming the semiconductor substrate. The second sidewall 82a serves to protect the second gate structure 32a during the process of forming the semiconductor substrate.
The floating gate 130a is formed over the blocking layer 40a, and preferably the floating gate 130a is formed over the blocking layer 40a covering the first drift region 21a or the second drift region 22 a. The floating gate can enable electric field distribution to be uniform, adjust the transverse electric field of the LDMOS transistor device and improve withstand voltage of the device.
The contact hole 120a connects the first drain region 51a, the second drain region 52a, the first gate structure 31a, the second gate structure 32a, and the pickup region 83a, respectively. To electrically connect the first drain region 51a, the second drain region 52a, the first gate structure 31a, the second gate structure 32a, and the pickup region 83a with subsequently formed interconnect structures.
An interconnect structure (not shown) is formed over the contact hole such that the first drain region 51a and the second drain region 52a form an electrical connection, and the first gate structure 31a and the second gate structure 32a form an electrical connection. Preferably, the material of the interconnection structure may be a metal material such as copper (Cu) or aluminum (Al) with high conductivity.
Preferably, metal silicide is formed on the first drain region 51a and the second drain region 52 a. The metal silicide 90a is formed on the first ohmic contact region 105a and the second ohmic contact region 106 a. The metal silicide 90a can function to reduce contact resistance and improve the performance of the semiconductor device.
It should be understood that the cross-sectional shapes of the respective regions in the embodiments of the present invention are only exemplary descriptions, and may be irregular shapes or the like formed in actual production processes.
The embodiment of the invention is characterized in that a pit is arranged in a body region between a first source region and a second source region, a pickup region with the doping type opposite to that of the first source region and the second source region is arranged at the bottom of the pit, and metal silicide is formed on the surface of the pit, wherein the pickup region is electrically connected with the first source region and the second source region. Thereby, the pickup capability of the body region of the semiconductor device can be improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a body region, a first drift region and a second drift region are formed in the semiconductor substrate, the first drift region and the second drift region are positioned at two sides of the body region, a gate structure layer is positioned on the body region, and a barrier layer covers the gate structure layer, wherein a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region;
etching the barrier layer and the gate structure layer in a predetermined region to form a first groove exposing the body region and a first gate structure and a second gate structure separated by the first groove;
performing ion implantation on the body region exposed in the first groove to form a doped region in the body region, wherein the doped region has a first doping type;
etching part of the doped region and part of the body region below the doped region to form a first source region and a second source region which are separated from each other and a second groove for isolating the first source region and the second source region;
ion implantation is carried out on the bottom of the second groove, and a pickup area with a second doping type is formed on the bottom of the second groove;
patterning the barrier layer;
Forming metal silicide through a self-alignment process, wherein the metal silicide at least covers the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively electrically connected with the pickup region;
forming a dielectric layer;
and forming a hole exposing the barrier layer in the dielectric layer, and depositing metal in the hole exposing the barrier layer to form the floating gate.
2. The method of claim 1, wherein the patterning the barrier layer comprises:
etching the barrier layer over the first gate structure and the second gate structure to form a plurality of holes exposing the first gate structure and a plurality of holes exposing the second gate structure;
wherein the metal silicide formed by the self-aligned process also covers the bottom of the hole.
3. The method of claim 1 or 2, wherein the patterning the barrier layer further comprises: etching the barrier layer above the first drain region and the second drain region to expose the first drain region and the second drain region;
the metal silicide formed by the self-aligned process also covers the first drain region and the second drain region.
4. The method according to claim 1, wherein the method further comprises:
Forming contact holes respectively connecting the first drain region, the second drain region, the first gate structure, the second gate structure and the pickup region while forming a floating gate;
and forming an interconnection structure above the contact hole so that the first drain region and the second drain region form an electrical connection.
5. The method according to claim 1, wherein the method further comprises: before forming the second groove, forming a first side wall covering the side wall of the first grid structure and part of the doped region, and forming a second side wall covering the side wall of the second grid structure and part of the doped region.
6. The method of claim 5, wherein the first source region is below the first sidewall and the second source region is below the second sidewall, and the second recess is between the first sidewall and the second sidewall.
7. The method of claim 1, wherein the first drift region and the second drift region have a first doping type and the body region has a second doping type.
8. A semiconductor device, comprising:
a semiconductor substrate, wherein a body region is formed in the semiconductor substrate, a first drift region and a second drift region are positioned at two sides of the body region, a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region;
A first gate structure covering a portion of the first drift region;
a second gate structure covering a portion of the second drift region;
a first source region and a second source region formed in the body region and separated from each other, the first source region and the second source region having a first doping type;
a dielectric layer having a hole exposing the barrier layer;
the floating gate is formed above the barrier layer, and the floating gate formed by depositing metal is arranged in the hole exposing the barrier layer; the body region is provided with a recess, the recess separates a first source region and a second source region, the bottom of the recess is provided with a pickup region, the pickup region is provided with a second doping type, and the side wall of the recess and the surface of the pickup region are provided with metal silicide, so that the first source region and the second source region are respectively electrically connected with the pickup region.
9. The semiconductor device of claim 8, further comprising a barrier layer;
the barrier layer covers the first gate structure and the first drift region, and covers the second gate structure and the second drift region;
Wherein a plurality of holes exposing the first gate structure are formed in the blocking layer above the first gate structure, a plurality of holes exposing the second gate structure are formed in the blocking layer above the second gate structure, and metal silicide is formed in the holes.
10. The semiconductor device according to claim 8 or 9, characterized in that the semiconductor device further comprises: the contact holes are respectively connected with the first drain region, the second drain region, the first grid structure, the second grid structure and the pickup region;
and an interconnection structure formed above the contact hole so that the first drain region and the second drain region form an electrical connection.
11. The semiconductor device according to claim 8, wherein a metal silicide is formed on the first drain region and the second drain region.
12. The semiconductor device according to claim 8, wherein the semiconductor device further comprises:
the first side wall covers the first grid structure side wall and the first source region;
and the second side wall covers the second grid electrode structure side wall and the second source region.
13. The semiconductor device of claim 12, wherein the recess is located between the first sidewall and the second sidewall.
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| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN107742645A (en) * | 2016-09-28 | 2018-02-27 | 成都芯源系统有限公司 | Method for manufacturing L DMOS device with self-aligned body region |
| CN107978635A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
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| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN107742645A (en) * | 2016-09-28 | 2018-02-27 | 成都芯源系统有限公司 | Method for manufacturing L DMOS device with self-aligned body region |
| CN107978635A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
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