DE69017803D1 - Verfahren zur Herstellung einer Halbleiterspeicheranordnung. - Google Patents

Verfahren zur Herstellung einer Halbleiterspeicheranordnung.

Info

Publication number
DE69017803D1
DE69017803D1 DE69017803T DE69017803T DE69017803D1 DE 69017803 D1 DE69017803 D1 DE 69017803D1 DE 69017803 T DE69017803 T DE 69017803T DE 69017803 T DE69017803 T DE 69017803T DE 69017803 D1 DE69017803 D1 DE 69017803D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69017803T
Other languages
English (en)
Other versions
DE69017803T2 (de
Inventor
Hiroaki Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69017803D1 publication Critical patent/DE69017803D1/de
Application granted granted Critical
Publication of DE69017803T2 publication Critical patent/DE69017803T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
DE69017803T 1989-08-31 1990-08-30 Verfahren zur Herstellung einer Halbleiterspeicheranordnung. Expired - Fee Related DE69017803T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1225303A JPH0388370A (ja) 1989-08-31 1989-08-31 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
DE69017803D1 true DE69017803D1 (de) 1995-04-20
DE69017803T2 DE69017803T2 (de) 1995-09-28

Family

ID=16827230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69017803T Expired - Fee Related DE69017803T2 (de) 1989-08-31 1990-08-30 Verfahren zur Herstellung einer Halbleiterspeicheranordnung.

Country Status (6)

Country Link
US (1) US5541129A (de)
EP (1) EP0415775B1 (de)
JP (1) JPH0388370A (de)
KR (1) KR930010015B1 (de)
AU (1) AU6630890A (de)
DE (1) DE69017803T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2904341B2 (ja) * 1996-03-06 1999-06-14 日本電気株式会社 半導体装置およびその製造方法
JPH09260613A (ja) * 1996-03-19 1997-10-03 Oki Electric Ind Co Ltd トンネル絶縁膜の膜質評価方法
US5960302A (en) * 1996-12-31 1999-09-28 Lucent Technologies, Inc. Method of making a dielectric for an integrated circuit
US6143608A (en) * 1999-03-31 2000-11-07 Advanced Micro Devices, Inc. Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation
JP3613072B2 (ja) * 1999-06-02 2005-01-26 株式会社デンソー 不揮発性半導体メモリの電荷保持寿命評価方法
KR100546407B1 (ko) * 2004-04-30 2006-01-26 삼성전자주식회사 Ｅｅｐｒｏｍ 셀 제조방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4115914A (en) * 1976-03-26 1978-09-26 Hughes Aircraft Company Electrically erasable non-volatile semiconductor memory
JPS55156371A (en) * 1979-05-24 1980-12-05 Toshiba Corp Non-volatile semiconductor memory device
JPS5955071A (ja) * 1982-09-24 1984-03-29 Hitachi Micro Comput Eng Ltd 不揮発性半導体装置
JPS5966171A (ja) * 1982-10-08 1984-04-14 Hitachi Ltd 半導体装置
JPS6184868A (ja) * 1984-10-02 1986-04-30 Nec Corp 不揮発性半導体記憶装置
JPH0669099B2 (ja) * 1984-12-21 1994-08-31 株式会社東芝 Ｍｉｓ型半導体装置
US4789883A (en) * 1985-12-17 1988-12-06 Advanced Micro Devices, Inc. Integrated circuit structure having gate electrode and underlying oxide and method of making same
JPS6325955A (ja) * 1986-07-18 1988-02-03 Toshiba Corp 半導体装置の製造方法
US5008721A (en) * 1988-07-15 1991-04-16 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
US5017979A (en) * 1989-04-28 1991-05-21 Nippondenso Co., Ltd. EEPROM semiconductor memory device
US5063423A (en) * 1989-04-28 1991-11-05 Nippondenso Co., Ltd. Semiconductor memory device of a floating gate tunnel oxide type
JPH081933B2 (ja) * 1989-12-11 1996-01-10 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
KR910005465A (ko) 1991-03-30
EP0415775A2 (de) 1991-03-06
US5541129A (en) 1996-07-30
AU6630890A (en) 1992-03-30
DE69017803T2 (de) 1995-09-28
JPH0388370A (ja) 1991-04-12
EP0415775A3 (en) 1991-04-03
EP0415775B1 (de) 1995-03-15
KR930010015B1 (ko) 1993-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee