DE3789372T2 - Verfahren zur Herstellung eines Halbleiterbauelements. - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements.

Info

Publication number
DE3789372T2
DE3789372T2 DE3789372T DE3789372T DE3789372T2 DE 3789372 T2 DE3789372 T2 DE 3789372T2 DE 3789372 T DE3789372 T DE 3789372T DE 3789372 T DE3789372 T DE 3789372T DE 3789372 T2 DE3789372 T2 DE 3789372T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3789372T
Other languages
English (en)
Other versions
DE3789372D1 (de
Inventor
David James Coe
Kenneth Ronald Whight
Richard John Tree
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3789372D1 publication Critical patent/DE3789372D1/de
Publication of DE3789372T2 publication Critical patent/DE3789372T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
DE3789372T 1986-12-23 1987-12-17 Verfahren zur Herstellung eines Halbleiterbauelements. Expired - Fee Related DE3789372T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08630814A GB2199694A (en) 1986-12-23 1986-12-23 A method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
DE3789372D1 DE3789372D1 (de) 1994-04-21
DE3789372T2 true DE3789372T2 (de) 1994-09-29

Family

ID=10609539

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3789372T Expired - Fee Related DE3789372T2 (de) 1986-12-23 1987-12-17 Verfahren zur Herstellung eines Halbleiterbauelements.

Country Status (5)

Country Link
US (1) US4904613A (de)
JP (1) JPH084093B2 (de)
KR (1) KR970003846B1 (de)
DE (1) DE3789372T2 (de)
GB (1) GB2199694A (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270359A (ja) * 1988-04-22 1989-10-27 Nec Corp 縦型電界効果トランジスタの製造方法
JP2751612B2 (ja) * 1990-10-01 1998-05-18 株式会社デンソー 縦型パワートランジスタ及びその製造方法
US5798550A (en) * 1990-10-01 1998-08-25 Nippondenso Co. Ltd. Vertical type semiconductor device and gate structure
US5256563A (en) * 1992-04-16 1993-10-26 Texas Instruments Incorporated Doped well structure and method for semiconductor technologies
GB9215653D0 (en) * 1992-07-23 1992-09-09 Philips Electronics Uk Ltd A method of manufacturing a semiconductor device comprising an insulated gate field effect device
US5414283A (en) * 1993-11-19 1995-05-09 Ois Optical Imaging Systems, Inc. TFT with reduced parasitic capacitance
US6724039B1 (en) * 1998-08-31 2004-04-20 Stmicroelectronics, Inc. Semiconductor device having a Schottky diode
US6621107B2 (en) 2001-08-23 2003-09-16 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
JP4793840B2 (ja) * 2003-11-10 2011-10-12 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
US8269287B2 (en) * 2007-05-25 2012-09-18 Cypress Semiconductor Corporation Floating gate memory device with increased coupling coefficient
US7881118B2 (en) * 2007-05-25 2011-02-01 Cypress Semiconductor Corporation Sense transistor protection for memory programming
JP4956351B2 (ja) * 2007-09-28 2012-06-20 オンセミコンダクター・トレーディング・リミテッド Ｄｍｏｓトランジスタの製造方法
DE102014005879B4 (de) * 2014-04-16 2021-12-16 Infineon Technologies Ag Vertikale Halbleitervorrichtung

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1432309A (en) * 1973-03-02 1976-04-14 Signetics Corp Semiconductor structures
US3933541A (en) * 1974-01-22 1976-01-20 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor planar device
US4038107B1 (en) * 1975-12-03 1995-04-18 Samsung Semiconductor Tele Method for making transistor structures
DE2723254A1 (de) * 1976-07-02 1978-01-12 Ibm Halbleiterstruktur mit vom halbleitermaterial isolierten polysiliciumelektroden und verfahren zu ihrer herstellung
DE2930780C2 (de) * 1979-07-28 1982-05-27 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zur Herstellung eines VMOS-Transistors
GB2071413B (en) * 1980-03-10 1983-12-21 Trw Inc Method of adhesion of passivation layer to gold metalization regions in a semiconductor device
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
DE3040775A1 (de) * 1980-10-29 1982-05-13 Siemens AG, 1000 Berlin und 8000 München Mis-gesteuertes halbleiterbauelement
JPS58171832A (ja) * 1982-03-31 1983-10-08 Toshiba Corp 半導体装置の製造方法
AT380974B (de) * 1982-04-06 1986-08-11 Shell Austria Verfahren zum gettern von halbleiterbauelementen
JPS58175846A (ja) * 1982-04-08 1983-10-15 Toshiba Corp 半導体装置の製造方法
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US4470874A (en) * 1983-12-15 1984-09-11 International Business Machines Corporation Planarization of multi-level interconnected metallization system
US4587713A (en) * 1984-02-22 1986-05-13 Rca Corporation Method for making vertical MOSFET with reduced bipolar effects
JPS60182171A (ja) * 1984-02-29 1985-09-17 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS61156882A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 二重拡散形絶縁ゲ−ト電界効果トランジスタ及びその製造方法
US4716126A (en) * 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor

Also Published As

Publication number Publication date
GB8630814D0 (en) 1987-02-04
GB2199694A (en) 1988-07-13
US4904613A (en) 1990-02-27
JPS63169068A (ja) 1988-07-13
JPH084093B2 (ja) 1996-01-17
DE3789372D1 (de) 1994-04-21
KR880008459A (ko) 1988-08-31
KR970003846B1 (en) 1997-03-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee