DE69030709D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents
Verfahren zur Herstellung einer HalbleiteranordnungInfo
- Publication number
- DE69030709D1 DE69030709D1 DE69030709T DE69030709T DE69030709D1 DE 69030709 D1 DE69030709 D1 DE 69030709D1 DE 69030709 T DE69030709 T DE 69030709T DE 69030709 T DE69030709 T DE 69030709T DE 69030709 D1 DE69030709 D1 DE 69030709D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1277929A JP2870054B2 (ja) | 1989-10-25 | 1989-10-25 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69030709D1 true DE69030709D1 (de) | 1997-06-19 |
DE69030709T2 DE69030709T2 (de) | 1997-12-18 |
Family
ID=17590254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69030709T Expired - Fee Related DE69030709T2 (de) | 1989-10-25 | 1990-10-24 | Verfahren zur Herstellung einer Halbleiteranordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5242853A (de) |
EP (1) | EP0424905B1 (de) |
JP (1) | JP2870054B2 (de) |
KR (1) | KR100188896B1 (de) |
DE (1) | DE69030709T2 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69224583T2 (de) * | 1991-10-15 | 1998-07-23 | Canon Kk | Trägermaterial für Flüssigkeitsaufzeichnungskopf, Herstellungsverfahren dafür, Flüssigkeitsaufzeichnungskopf und Flüssigkeitsaufzeichnungsvorrichtung |
US5244827A (en) * | 1991-10-31 | 1993-09-14 | Sgs-Thomson Microelectronics, Inc. | Method for planarized isolation for cmos devices |
US5498565A (en) * | 1991-11-29 | 1996-03-12 | Sony Corporation | Method of forming trench isolation having polishing step and method of manufacturing semiconductor device |
EP0637062B1 (de) * | 1993-07-27 | 1997-06-04 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines Halbleiterschichtaufbaus mit planarisierter Oberfläche und dessen Verwendung bei der Herstellung eines Bipolartransistors sowie eines DRAM |
FR2727768B1 (fr) * | 1994-12-05 | 1997-01-10 | Alcatel Nv | Procede pour former une couche de silice a eliminer ulterieurement et procede pour rapporter un composant en optique integree |
US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
KR100226736B1 (ko) * | 1996-11-07 | 1999-10-15 | 구본준 | 격리영역 형성방법 |
US5858866A (en) * | 1996-11-22 | 1999-01-12 | International Business Machines Corportation | Geometrical control of device corner threshold |
US5721173A (en) * | 1997-02-25 | 1998-02-24 | Kabushiki Kaisha Toshiba | Method of forming a shallow trench isolation structure |
US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
US6046088A (en) * | 1997-12-05 | 2000-04-04 | Advanced Micro Devices, Inc. | Method for self-aligning polysilicon gates with field isolation and the resultant structure |
US6228741B1 (en) | 1998-01-13 | 2001-05-08 | Texas Instruments Incorporated | Method for trench isolation of semiconductor devices |
JPH11233609A (ja) * | 1998-02-13 | 1999-08-27 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6048775A (en) * | 1999-05-24 | 2000-04-11 | Vanguard International Semiconductor Corporation | Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes |
US6261957B1 (en) | 1999-08-20 | 2001-07-17 | Taiwan Semiconductor Manufacturing Company | Self-planarized gap-filling by HDPCVD for shallow trench isolation |
US7554055B2 (en) * | 2005-05-03 | 2009-06-30 | Hitachi Global Storage Technologies Netherlands B.V. | Method for making ohmic contact to silicon structures with low thermal loads |
JP2007173383A (ja) * | 2005-12-20 | 2007-07-05 | Sharp Corp | トレンチ素子分離領域の形成方法、窒化シリコン膜ライナーの形成方法、半導体装置の製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
US4274909A (en) * | 1980-03-17 | 1981-06-23 | International Business Machines Corporation | Method for forming ultra fine deep dielectric isolation |
US4564997A (en) * | 1981-04-21 | 1986-01-21 | Nippon-Telegraph And Telephone Public Corporation | Semiconductor device and manufacturing process thereof |
JPS59942A (ja) * | 1982-06-28 | 1984-01-06 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS6021540A (ja) * | 1983-07-15 | 1985-02-02 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
JPS6053045A (ja) * | 1983-09-02 | 1985-03-26 | Hitachi Ltd | 絶縁分離方法 |
JPS618945A (ja) * | 1984-06-25 | 1986-01-16 | Nec Corp | 半導体集積回路装置 |
US4554728A (en) * | 1984-06-27 | 1985-11-26 | International Business Machines Corporation | Simplified planarization process for polysilicon filled trenches |
JPS622554A (ja) * | 1985-06-27 | 1987-01-08 | Seiko Epson Corp | 半導体装置の製造方法 |
US4666556A (en) * | 1986-05-12 | 1987-05-19 | International Business Machines Corporation | Trench sidewall isolation by polysilicon oxidation |
US4851366A (en) * | 1987-11-13 | 1989-07-25 | Siliconix Incorporated | Method for providing dielectrically isolated circuit |
JP2717549B2 (ja) * | 1988-07-07 | 1998-02-18 | 株式会社興人 | 御影石調人工ソリッド材 |
JPH0294050A (ja) * | 1988-09-30 | 1990-04-04 | Toshiba Corp | インパクトジッタ軽減回路 |
IT1225625B (it) * | 1988-11-03 | 1990-11-22 | Sgs Thomson Microelectronics | Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos. |
-
1989
- 1989-10-25 JP JP1277929A patent/JP2870054B2/ja not_active Expired - Fee Related
-
1990
- 1990-10-24 EP EP90120394A patent/EP0424905B1/de not_active Expired - Lifetime
- 1990-10-24 DE DE69030709T patent/DE69030709T2/de not_active Expired - Fee Related
- 1990-10-25 US US07/603,310 patent/US5242853A/en not_active Expired - Lifetime
- 1990-10-25 KR KR1019900017101A patent/KR100188896B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR910008867A (ko) | 1991-05-31 |
EP0424905A3 (en) | 1992-08-12 |
US5242853A (en) | 1993-09-07 |
KR100188896B1 (ko) | 1999-07-01 |
JPH03139858A (ja) | 1991-06-14 |
EP0424905B1 (de) | 1997-05-14 |
EP0424905A2 (de) | 1991-05-02 |
DE69030709T2 (de) | 1997-12-18 |
JP2870054B2 (ja) | 1999-03-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |