DE69615642D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
DE69615642D1
DE69615642D1 DE69615642T DE69615642T DE69615642D1 DE 69615642 D1 DE69615642 D1 DE 69615642D1 DE 69615642 T DE69615642 T DE 69615642T DE 69615642 T DE69615642 T DE 69615642T DE 69615642 D1 DE69615642 D1 DE 69615642D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69615642T
Other languages
English (en)
Other versions
DE69615642T2 (de
Inventor
Haruhiko Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69615642D1 publication Critical patent/DE69615642D1/de
Application granted granted Critical
Publication of DE69615642T2 publication Critical patent/DE69615642T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S430/00Radiation imagery chemistry: process, composition, or product thereof
    • Y10S430/143Electron beam
DE69615642T 1995-12-11 1996-12-11 Verfahren zur Herstellung einer Halbleiteranordnung Expired - Lifetime DE69615642T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32153595 1995-12-11

Publications (2)

Publication Number Publication Date
DE69615642D1 true DE69615642D1 (de) 2001-11-08
DE69615642T2 DE69615642T2 (de) 2002-08-01

Family

ID=18133654

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615642T Expired - Lifetime DE69615642T2 (de) 1995-12-11 1996-12-11 Verfahren zur Herstellung einer Halbleiteranordnung

Country Status (4)

Country Link
US (1) US5916733A (de)
EP (1) EP0779556B1 (de)
KR (1) KR100225831B1 (de)
DE (1) DE69615642T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6312874B1 (en) * 1998-11-06 2001-11-06 Advanced Micro Devices, Inc. Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
US6218056B1 (en) * 1999-03-30 2001-04-17 International Business Machines Corporation Method of making highly defined bilayer lift-off mask
FR2810447B1 (fr) * 2000-06-16 2003-09-05 Commissariat Energie Atomique Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
US7071121B2 (en) * 2003-10-28 2006-07-04 Hewlett-Packard Development Company, L.P. Patterned ceramic films and method for producing the same
DE102004056369B4 (de) * 2004-11-22 2008-08-28 Renk Ag Betätigungseinrichtung für Fahrzeuggetriebe von Kettenfahrzeugen oder Radfahrzeugen mit Radseitenlenkung
WO2007116362A1 (en) * 2006-04-07 2007-10-18 Nxp B.V. Method of manufacturing a semiconductor device
US8048764B2 (en) * 2009-09-30 2011-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Dual etch method of defining active area in semiconductor device
CN103390584A (zh) * 2012-05-09 2013-11-13 中国科学院微电子研究所 半导体器件的制造方法
US8906244B2 (en) * 2012-10-25 2014-12-09 The United States Of America As Represented By The Secretary Of The Army Method for forming a device having nanopillar and cap structures
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669835A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Method for forming thin film pattern
DE3175019D1 (en) * 1980-04-02 1986-09-04 Hitachi Ltd Method of forming patterns
JPS5968928A (ja) * 1982-10-13 1984-04-19 Pioneer Electronic Corp 半導体装置の製造方法
US4591547A (en) * 1982-10-20 1986-05-27 General Instrument Corporation Dual layer positive photoresist process and devices
US4610948A (en) * 1984-01-25 1986-09-09 The United States Of America As Represented By The Secretary Of The Army Electron beam peripheral patterning of integrated circuits
US4612274A (en) * 1985-11-18 1986-09-16 Motorola, Inc. Electron beam/optical hybrid lithographic resist process in acoustic wave devices
US5194749A (en) * 1987-11-30 1993-03-16 Hitachi, Ltd. Semiconductor integrated circuit device
US5034091A (en) * 1990-04-27 1991-07-23 Hughes Aircraft Company Method of forming an electrical via structure
KR100188508B1 (ko) * 1993-03-26 1999-06-01 세끼사와 다까시 비정질탄소막을 사용하는 패턴형성방법과 에칭방법 및 비정질탄소막 형성방법
GB2284300B (en) * 1993-11-10 1997-11-19 Hyundai Electronics Ind Process for forming fine pattern of semiconductor device

Also Published As

Publication number Publication date
EP0779556A2 (de) 1997-06-18
DE69615642T2 (de) 2002-08-01
EP0779556A3 (de) 1997-07-02
KR100225831B1 (ko) 1999-10-15
US5916733A (en) 1999-06-29
EP0779556B1 (de) 2001-10-04
KR970051945A (ko) 1997-07-29

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Legal Events

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8364 No opposition during term of opposition