DE69416808D1 - Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung

Info

Publication number
DE69416808D1
DE69416808D1 DE69416808T DE69416808T DE69416808D1 DE 69416808 D1 DE69416808 D1 DE 69416808D1 DE 69416808 T DE69416808 T DE 69416808T DE 69416808 T DE69416808 T DE 69416808T DE 69416808 D1 DE69416808 D1 DE 69416808D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
multilayer semiconductor
multilayer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69416808T
Other languages
English (en)
Other versions
DE69416808T2 (de
Inventor
Takeshi Akimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69416808D1 publication Critical patent/DE69416808D1/de
Publication of DE69416808T2 publication Critical patent/DE69416808T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69416808T 1993-12-28 1994-12-27 Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung Expired - Fee Related DE69416808T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5336648A JPH07201986A (ja) 1993-12-28 1993-12-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69416808D1 true DE69416808D1 (de) 1999-04-08
DE69416808T2 DE69416808T2 (de) 1999-10-07

Family

ID=18301344

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69416808T Expired - Fee Related DE69416808T2 (de) 1993-12-28 1994-12-27 Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung

Country Status (4)

Country Link
US (1) US5668053A (de)
EP (1) EP0661736B1 (de)
JP (1) JPH07201986A (de)
DE (1) DE69416808T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996027901A1 (en) * 1995-03-07 1996-09-12 Micron Technology, Inc. Improved semiconductor contacts to thin conductive layers
US5730835A (en) * 1996-01-31 1998-03-24 Micron Technology, Inc. Facet etch for improved step coverage of integrated circuit contacts
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
US5948702A (en) * 1996-12-19 1999-09-07 Texas Instruments Incorporated Selective removal of TixNy
US5929526A (en) * 1997-06-05 1999-07-27 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US6706623B1 (en) * 1997-12-10 2004-03-16 Texas Instruments Incorporated Method and system for avoiding plasma etch damage
US6261934B1 (en) 1998-03-31 2001-07-17 Texas Instruments Incorporated Dry etch process for small-geometry metal gates over thin gate dielectric
US6274486B1 (en) 1998-09-02 2001-08-14 Micron Technology, Inc. Metal contact and process
US6423626B1 (en) 1998-11-02 2002-07-23 Micron Technology, Inc. Removal of metal cusp for improved contact fill
AT409429B (de) * 1999-07-15 2002-08-26 Sez Semiconduct Equip Zubehoer Verfahren zum ätzbehandeln von halbleitersubstraten zwecks freilegen einer metallschicht
TW201103972A (en) 2009-04-01 2011-02-01 Solvay Fluor Gmbh Process for the manufacture of etched items
US10607922B1 (en) * 2018-10-24 2020-03-31 International Business Machines Corporation Controlling via critical dimension during fabrication of a semiconductor wafer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPH0689461B2 (ja) * 1985-07-16 1994-11-09 シチズン時計株式会社 窒化チタン被膜の除去方法
JPS62132359A (ja) * 1985-12-04 1987-06-15 Fujitsu Ltd Ａｌメタル層構造
JP2637969B2 (ja) * 1987-03-30 1997-08-06 ソニー株式会社 エツチング方法
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
JPH02140955A (ja) * 1988-11-22 1990-05-30 Seiko Epson Corp 半導体装置
JPH02270347A (ja) * 1989-04-11 1990-11-05 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0499385A (ja) * 1990-08-18 1992-03-31 Seiko Epson Corp Ｍｏｓ型半導体装置の製造方法
JP3139781B2 (ja) * 1991-08-07 2001-03-05 沖電気工業株式会社 半導体装置およびその製造方法
KR940008323B1 (ko) * 1991-10-16 1994-09-12 삼성전자 주식회사 반도체장치의 층간접속방법
JPH05121378A (ja) * 1991-10-29 1993-05-18 Sony Corp 半導体装置の製造方法
JP3160972B2 (ja) * 1991-11-01 2001-04-25 ソニー株式会社 半導体装置の製造方法
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5449639A (en) * 1994-10-24 1995-09-12 Taiwan Semiconductor Manufacturing Company Ltd. Disposable metal anti-reflection coating process used together with metal dry/wet etch

Also Published As

Publication number Publication date
JPH07201986A (ja) 1995-08-04
US5668053A (en) 1997-09-16
EP0661736A1 (de) 1995-07-05
DE69416808T2 (de) 1999-10-07
EP0661736B1 (de) 1999-03-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee