JPS562654A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS562654A
JPS562654A JP7848779A JP7848779A JPS562654A JP S562654 A JPS562654 A JP S562654A JP 7848779 A JP7848779 A JP 7848779A JP 7848779 A JP7848779 A JP 7848779A JP S562654 A JPS562654 A JP S562654A
Authority
JP
Japan
Prior art keywords
si3n4
psg9
sio2
films
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7848779A
Other languages
Japanese (ja)
Inventor
Haruo Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7848779A priority Critical patent/JPS562654A/en
Publication of JPS562654A publication Critical patent/JPS562654A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain inter layer insulating films having few fear of disconnection and short-circuiting and have a superior water-tightness by a method wherein CVD-SiO2 films are put upon Si3N4 films formed on PSG films. CONSTITUTION:A source, drain or gate electrode 4 and a wiring layer 5, etc., are prepared, openings 10-12 are formed selectvely in PSG9 and Si3N4 20, SiO2 13 are laminated on them. Openings 14-16 are formed in the SiO2 13, but the PSG9 does not etched as the Si3N4 20 acts as a stopper. Then openings are formed in the Si3N4 20, and Al wirings 17-19 are formed selectively. By this method, as the PSG9 dose not gouged by etching, the disconnection in the wiring 19 does not take place. As two-layer film of Si3N4 and SiO2 is laid on the PSG9, it displays the sufficient water-proof effect, the withstanding voltage is elevated by the existence of Si3N4 film and a multilayer wiring structure having a highly reliable inter layer insulating film can be obtained.
JP7848779A 1979-06-21 1979-06-21 Semiconductor device Pending JPS562654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7848779A JPS562654A (en) 1979-06-21 1979-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7848779A JPS562654A (en) 1979-06-21 1979-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS562654A true JPS562654A (en) 1981-01-12

Family

ID=13663329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7848779A Pending JPS562654A (en) 1979-06-21 1979-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS562654A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248239A (en) * 1986-04-22 1987-10-29 Nec Corp Manufacture of semiconductor device
JPH01165143A (en) * 1987-12-22 1989-06-29 Toshiba Corp Formation of direct contact
US4948743A (en) * 1988-06-29 1990-08-14 Matsushita Electronics Corporation Method of manufacturing a semiconductor device
US4985374A (en) * 1989-06-30 1991-01-15 Kabushiki Kaisha Toshiba Making a semiconductor device with ammonia treatment of photoresist
JPH03270256A (en) * 1990-03-20 1991-12-02 Nippon Precision Circuits Kk Semiconductor device
US5081060A (en) * 1989-05-13 1992-01-14 Hyundai Electronics Industries, Co., Ltd. Method for forming a connection device in a semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5252379A (en) * 1976-07-29 1977-04-27 Sony Corp Semiconductor device
JPS5268371A (en) * 1975-12-05 1977-06-07 Nec Corp Semiconductor device
JPS52104087A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts
JPS5455388A (en) * 1977-10-12 1979-05-02 Matsushita Electric Ind Co Ltd Production of mos type semiconductor device
JPS5459889A (en) * 1977-10-21 1979-05-14 Hitachi Ltd Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5268371A (en) * 1975-12-05 1977-06-07 Nec Corp Semiconductor device
JPS52104087A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts
JPS5252379A (en) * 1976-07-29 1977-04-27 Sony Corp Semiconductor device
JPS5455388A (en) * 1977-10-12 1979-05-02 Matsushita Electric Ind Co Ltd Production of mos type semiconductor device
JPS5459889A (en) * 1977-10-21 1979-05-14 Hitachi Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248239A (en) * 1986-04-22 1987-10-29 Nec Corp Manufacture of semiconductor device
JPH01165143A (en) * 1987-12-22 1989-06-29 Toshiba Corp Formation of direct contact
US4948743A (en) * 1988-06-29 1990-08-14 Matsushita Electronics Corporation Method of manufacturing a semiconductor device
US5081060A (en) * 1989-05-13 1992-01-14 Hyundai Electronics Industries, Co., Ltd. Method for forming a connection device in a semiconductor device
US4985374A (en) * 1989-06-30 1991-01-15 Kabushiki Kaisha Toshiba Making a semiconductor device with ammonia treatment of photoresist
JPH03270256A (en) * 1990-03-20 1991-12-02 Nippon Precision Circuits Kk Semiconductor device

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