JPS62248239A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62248239A JPS62248239A JP9360886A JP9360886A JPS62248239A JP S62248239 A JPS62248239 A JP S62248239A JP 9360886 A JP9360886 A JP 9360886A JP 9360886 A JP9360886 A JP 9360886A JP S62248239 A JPS62248239 A JP S62248239A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- film
- nitride film
- forming
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 23
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 6
- 238000007743 anodising Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 239000005360 phosphosilicate glass Substances 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000008034 disappearance Effects 0.000 description 3
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に咲Ｉし、特にパッドま
たはコンタクト孔における開口部の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an opening in a pad or a contact hole.
従来の半導体装置は、シリコン酸化膜またはプラズマ窒
化膜とリン硅酸ガラスとの２層構造からなる絶縁保護膜
を直接開口してパッド電極用または配線間接続用のコン
タクト孔がそれぞれ形成される。In conventional semiconductor devices, contact holes for pad electrodes or interconnections are formed by directly opening an insulating protective film having a two-layer structure of a silicon oxide film or a plasma nitride film and phosphosilicate glass.
しかしながら、かかる構造のコンタクト孔をもつ半導体
装置は使用中パッド１！頂のアルミ部材が変質または消
失したり或いは生産工程中温２層以上のアルミ配線が付
着しＫ＜＜なり配線間のオープン不良を発生するなど信
頼性上および生産歩溜り上きわめて重大な障害をしばし
ば起す。このアルミ部材の変′Ｘまたは消失などの事故
は、通常、コンタクト孔内部への浸水によって生じる。However, in a semiconductor device having a contact hole with such a structure, the pad 1 is in use! This often causes extremely serious failures in terms of reliability and production yield, such as the top aluminum component deteriorating or disappearing, or two or more layers of aluminum wiring adhering to each other during the production process, resulting in open defects between wiring. cause. Accidents such as deformation or disappearance of the aluminum member usually occur due to water intrusion into the contact hole.
すなわち、この障害はコンタクト孔内部に侵入した水分
がアルミ材を直接侵かして水酸化物を形成せしめるか、
または絶縁保護膜に含まれるナトリウム塩素などの不、
捕物イオンＮｎ、ＣＬまたはリン硅酸ガラス層と反応し
てリン硅酸塩イオンＰ０４ を生成し間接的にアルミ部
材を溶解することによって生じるものと推定されている
。従って、この障害の発生は樹脂封止型のものに多く、
また、生産工程中では接続配線を形成する際の高温・多
湿雰囲気がまた深く関係する。実験による検討結果によ
れば、コンタクト孔内への水分の侵入径路には絶縁保護
膜の２層構造そのものが大きく関与する。In other words, this failure is caused by moisture entering the contact hole and directly attacking the aluminum material to form hydroxide.
or non-containing substances such as sodium chloride contained in the insulating protective film.
It is estimated that this is generated by reacting with the trapped ions Nn, CL or the phosphosilicate glass layer to generate phosphosilicate ions P04 and indirectly melting the aluminum member. Therefore, this problem often occurs with resin-sealed types.
Furthermore, during the production process, the high temperature and high humidity atmosphere when forming the connection wiring is also closely related. According to the results of experimental studies, the two-layer structure of the insulating protective film itself is largely involved in the path of moisture intrusion into the contact hole.
すなわち、従来の形成方法によれば形成されたコンタク
ト孔の側壁には異なる２つの絶縁膜の境界層が全て露出
され孔内への水分侵入径路として機能する。従って、外
部からの水分はこの境界層を伝わって孔内に侵入しパッ
ドまたは配線のアルミ材を直接または間接に溶解するこ
ととなる。That is, according to the conventional forming method, the boundary layers of two different insulating films are all exposed on the side wall of a contact hole formed, and function as a path for moisture to infiltrate into the hole. Therefore, moisture from the outside penetrates into the hole through this boundary layer and directly or indirectly dissolves the aluminum material of the pad or wiring.
本発明の目的は、上記の実験結果に基づき、側壁に絶縁
保ｍ腹の境界層を露出せしむることなき構造のコンタク
ト孔を形成し得る半導体装置の製造方法を提供すること
である。An object of the present invention, based on the above experimental results, is to provide a method for manufacturing a semiconductor device that can form a contact hole with a structure that does not expose the boundary layer of the insulation layer on the side wall.
本発明の半導体装置の製造方法は、半導体基板上にアル
ミ配線を形成する段階と、前記アルミ配線を含む半導体
基板全面に異なる材質の絶縁膜を多層構造に積層する絶
縁保護膜形成段階と、前記絶縁保護膜をアルミ配線上で
選択的に除去する絶縁保ｄＩ膜の開口部形成段階と、前
記開口部を含む半導体基板全面にシリコン窒化膜を形成
する段階と、前記シリコン窒化膜を前記開口部側壁の被
覆部位を残しアルミ配線上で選択的に除去するシリコン
窒化膜の開口部形成段階とから成るコンタクト孔形成工
程を含む。The method for manufacturing a semiconductor device of the present invention includes a step of forming an aluminum wiring on a semiconductor substrate, a step of forming an insulating protective film of laminating insulating films of different materials in a multilayer structure over the entire surface of the semiconductor substrate including the aluminum wiring, and A step of forming an opening in the insulating dI film in which the insulating protective film is selectively removed on the aluminum wiring, a step of forming a silicon nitride film over the entire surface of the semiconductor substrate including the opening, and a step of forming the silicon nitride film on the opening. The contact hole forming step includes a step of forming an opening in the silicon nitride film, which is selectively removed on the aluminum wiring, leaving a portion covered on the sidewall.
すなわち、本発明によれば、従来、絶縁保護膜の開口部
の側壁に露出し孔内への水分侵入径路となっていた絶縁
膜境界層は耐湿性にきわめてすぐれるシリコン窒化膜に
よって被覆され孔内への出口が閉塞される。このシリコ
ン窒化膜はプラズマＣＶＤ法によって成長することが望
ましく、また開口手段にはレジストを用いる通常の写真
蝕刻法或いは開口部位を化成膜に変換しエツチング除去
するなどの方法を随時用い得る。That is, according to the present invention, the insulating film boundary layer, which was conventionally exposed on the side wall of the opening of the insulating protective film and served as a path for moisture to infiltrate into the hole, is now covered with a silicon nitride film that has extremely high moisture resistance. The exit to the inside is blocked. This silicon nitride film is preferably grown by the plasma CVD method, and as the opening means, a conventional photolithography method using a resist or a method of converting the opening portion into a chemically formed film and removing it by etching may be used as needed.
このシリコン窒化膜はシリコン酸化膜とはもちろんボリ
ミイド系樹脂との間にも良好な密着性を示すので、無機
、有機の区別なくあらゆる組合せの絶縁保護膜に対して
実施し得る。この際、このシリコン窒化膜は絶縁膜境界
層の露出面に対しパックベージ冒ン膜として機能するの
で、完成品の使用中または製造中の如何なる段階におい
ても外部からコンタクト孔内に水分を侵入せしめること
はない。以下図面を参照して本発明の詳細な説明する。Since this silicon nitride film exhibits good adhesion not only to silicon oxide films but also to borimide resins, it can be applied to any combination of insulating protective films, regardless of whether they are inorganic or organic. At this time, this silicon nitride film functions as a pack-basis attack film on the exposed surface of the insulating film boundary layer, so that moisture can enter the contact hole from the outside at any stage during use or manufacturing of the finished product. Never. The present invention will be described in detail below with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明をポンディング・パッド
部に実施した場合の一実施例を示す工程順序図である。FIGS. 1(a) to 1(d) are process flow diagrams showing one embodiment of the present invention applied to a bonding pad portion.
まず半導体基板上にはフィールド絶縁膜２が形成されつ
いでアルミ配線３とリン硅酸ガラス４およびシリコン酸
化膜５からなる２層構造の絶縁保護膜がそれぞれ形成さ
れる。この２層構造の絶縁保護膜は第１図（ａ）に示す
ように通常の手段で開口されアルミ配線３上に開口部６
を形成する。この開口部６を含む半導体基板全面にはシ
リコン窒化膜７が形成されついでレジスト８がバターニ
ングされる。〔第１回出）〕。このシリコン窒化１７Ｆ
ｉレジスト８をマスクとしてアルミ配線３上で選択的に
除去され開口部９が形成される。第１図（ｅ）にはこの
状態が示されている。この新らたに形成された開口部９
の側壁には開口部６で見られたリン硅酸ガラス膜４およ
びシリコン酸化ｌＡ５の境界層の露出面は完全にシリコ
ン窒化膜７で被覆され表面に現われていない１．すなわ
ち、従来存在していた水分侵入径路の開口部内への出口
は耐湿性の高いシリコン窒化膜７で完全に閉塞される。First, a field insulating film 2 is formed on a semiconductor substrate, and then a two-layer insulating protective film consisting of an aluminum wiring 3, a phosphosilicate glass 4, and a silicon oxide film 5 is formed. As shown in FIG. 1(a), this two-layer insulating protective film is opened by a conventional means, and an opening 6 is formed on the aluminum wiring 3.
form. A silicon nitride film 7 is formed on the entire surface of the semiconductor substrate including this opening 6, and then a resist 8 is patterned. [1st appearance]. This silicon nitride 17F
Using the i-resist 8 as a mask, the aluminum wiring 3 is selectively removed to form an opening 9. This state is shown in FIG. 1(e). This newly formed opening 9
On the side wall of 1., the exposed surfaces of the boundary layer of phosphosilicate glass film 4 and silicon oxide lA 5 seen through opening 6 are completely covered with silicon nitride film 7 and do not appear on the surface. That is, the exit of the conventional moisture intrusion path into the opening is completely blocked by the highly moisture-resistant silicon nitride film 7.
ここで、シリコン酸化膜７の形成手段にはプラズマＣＶ
Ｄ法によるのが最もよい。従って、この開口部９内にボ
ンディングｍ１ｏを圧着し樹脂１１で封止してなる第１
図（ｄ）の如き構造の半導体装置は、シリコン窒化膜７
のパッシベーション作用によって従来のようなパッド部
の変質、消失等の重大事故をおこすことはない。すなわ
ち、信頼性のきわめて高き半導体装置を製造し得る。Here, the means for forming the silicon oxide film 7 is plasma CVD.
It is best to use method D. Therefore, a first
A semiconductor device having a structure as shown in FIG.
Due to the passivation effect, serious accidents such as deterioration or disappearance of the pad part, unlike in the conventional case, do not occur. That is, a highly reliable semiconductor device can be manufactured.
つぎに第２図（ａ）〜（ｅ）は本発明を配線間のコンタ
クト孔形成に実施した場合の一実施例を示す工程順序図
である。Next, FIGS. 2(a) to 2(e) are process flow diagrams showing an embodiment in which the present invention is applied to forming contact holes between interconnections.
本実施例では絶縁保護膜がボリミイド樹脂１２とプラズ
マ・シリコン窒化膜１３との２層構造で形成される。こ
の場合の工程順序は第１図とほとんど変わるところはな
い。すなわち、第２図（ａ）および（′ｂ）に示すよう
に開口部１４を設けＣＶＤシリコン窒化膜７を敷く。つ
いでシリコン窒化膜７を同じように開口する段階に入る
。この段階は前実施例と同様に通常のレジスト法によっ
てもよいが、第２図（ｅ）Ｋ示すようにシリコン窒化膜
７をアルミ配線３を一つの電極として陽極酸化しそのと
きできる化成膜１５を除去する手段によりてもよい。In this embodiment, the insulating protective film is formed with a two-layer structure of a bolimide resin 12 and a plasma silicon nitride film 13. The process order in this case is almost the same as in FIG. That is, as shown in FIGS. 2(a) and 2('b), an opening 14 is provided and a CVD silicon nitride film 7 is laid thereon. Next, a step begins in which openings are made in the silicon nitride film 7 in the same manner. This step may be carried out by the usual resist method as in the previous embodiment, but as shown in FIG. 15 may be used.
この化成ＭＸ１５の除去は酸化膜と窒化膜に高い選択比
をもつプラズマ・エツチング技術を用いればきわめて容
易に行なうことができアルミ配線３上にその開口部１６
が第２図（ｄ）に示すように簡単に形成される。従って
、この開口部１７を介しアルミ配線３と接続するＷＸｚ
層配線１７を形成する工程においてもシリコン窒化膜７
のパッシベーション作用によって水分の影響を受けるこ
となく開口部１７内にも確実に形成される。従って、こ
の工程を経て作られた第２図（０）の如き中間構造にお
いて配線間にこオープン不良をおこすことはない。This chemically formed MX15 can be removed very easily by using plasma etching technology that has a high selectivity between the oxide film and the nitride film.
is easily formed as shown in FIG. 2(d). Therefore, WXz connected to the aluminum wiring 3 through this opening 17
Also in the step of forming the layer wiring 17, the silicon nitride film 7
Due to the passivation effect, the film is reliably formed within the opening 17 without being affected by moisture. Therefore, in the intermediate structure as shown in FIG. 2(0) made through this process, open defects will not occur between the wirings.
以上詳細に説明したようにシリコン窒化膜７で側壁全体
を被覆された開口部６または１６はパッド部または配線
間のコンタクト孔としてきわめて高い耐湿性を備えるこ
とが可能である。従って、本発明によれば従来問題とさ
れたパッド部材の変質または消失或いは生産工程中の配
線間オープン不良の痛°障害を解決することができ、半
導体装置の信頼性を著しく向上せしめることが可能であ
る。As described above in detail, the opening 6 or 16 whose entire side wall is covered with the silicon nitride film 7 can have extremely high moisture resistance as a pad portion or a contact hole between wirings. Therefore, according to the present invention, it is possible to solve the conventional problems of deterioration or disappearance of pad members or open defects between wirings during the production process, and it is possible to significantly improve the reliability of semiconductor devices. It is.
また、シリコン窒化膜の被覆はコンタクト孔の側壁全面
に及んでいるので、絶縁保護膜の材質の種類または積層
数の如何を問わずそれぞれの耐湿性を有効に向上せしめ
得る。Moreover, since the silicon nitride film covers the entire sidewall of the contact hole, the moisture resistance of each insulating protective film can be effectively improved regardless of the type of material or the number of laminated layers.
第１図（ＩＬ）〜（ｄ）は本発明をボンディング・パッ
ド部に実施した場合の一実施例を工程順に示した断面図
、第２図（ａ）〜（ｅ）は本発明を配線間のコンタクト
孔形成に実施した場合の一実施例を工程順に示した断面
図である。
１・・・・・・半導体基板、２・・・・・・フィールド
絶！Ｒ＃、３．１７・・・・・・アルミ配線、４・・・
・・・リン硅酸ガラス膜、５・・・・・・シリコン酸化
膜、６，９，１４，１６・・・・・・開口部、７，１３
・・・・・、ＣＶＤシリコン窒化膜、８・・・・・・レ
ジスト、１ｏ・・・・・・ボンディング線、１１・・・
・・・封止用樹脂、１２・・・・・・ポリミイド系樹脂
、１５・・・・・・シリコン窒化膜の化成膜。
代理人 弁理士 内 原 晋１．′・、′−・？
・。
（Ｃ）
躬２図Figures 1 (IL) to (d) are cross-sectional views showing one embodiment of the present invention applied to a bonding pad portion in the order of steps, and Figures 2 (a) to (e) are cross-sectional views showing the present invention applied to a bonding pad portion. FIG. 3 is a cross-sectional view showing an embodiment in order of steps in the case of forming a contact hole. 1...Semiconductor substrate, 2...Field perfection! R#, 3.17... Aluminum wiring, 4...
... Phosphorsilicate glass film, 5 ... Silicon oxide film, 6, 9, 14, 16 ... Opening, 7, 13
...CVD silicon nitride film, 8...resist, 1o...bonding line, 11...
... Sealing resin, 12 ... Polymide resin, 15 ... Chemical formation of silicon nitride film. Agent: Susumu Uchihara, patent attorney 1. ′・,′−・?
・. (C) Fig. 2
Claims (4)
記アルミ配線を含む半導体基板全面に異なる材質の絶縁
膜を多層構造に積層する絶縁保護膜形成段階と、前記絶
縁保護膜をアルミ配線上で選択的に除去する絶縁保護膜
の開口部形成段階と、前記開口部を含む半導体基板全面
にシリコン窒化膜を形成する段階と、前記シリコン窒化
膜を前記開口部側壁の被覆部位を残しアルミ配線上で選
択的に除去するシリコン窒化膜の開口部形成段階とから
成るコンタクト孔形成工程を含むことを特徴とする半導
体装置の製造方法。(1) A step of forming an aluminum wiring on a semiconductor substrate, a step of forming an insulating protective film in which insulating films of different materials are laminated in a multilayer structure over the entire surface of the semiconductor substrate including the aluminum wiring, and a step of forming an insulating protective film on the aluminum wiring. a step of forming an opening in the insulating protective film, which is selectively removed with a step of forming a silicon nitride film on the entire surface of the semiconductor substrate including the opening, and a step of forming a silicon nitride film on the aluminum wiring, leaving a portion covered on the side wall of the opening. 1. A method of manufacturing a semiconductor device, comprising a step of forming a contact hole, which comprises a step of forming an opening in a silicon nitride film that is selectively removed above.
の無機絶縁膜で形成することを特徴とする特許請求の範
囲第（１）項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), wherein the insulating protective film having the multilayer structure is formed of a plurality of inorganic insulating films made of different materials.
機絶縁膜を含んで形成することを特徴とする特許請求の
範囲第（１）項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim (1), wherein the insulating protective film having a multilayer structure is formed to include at least one organic insulating film.
のアルミ配線を一つの電極とするシリコン窒化膜の陽極
酸化手段と前記陽極酸化手段により形成されるシリコン
窒化膜の化成膜に対する選択的除去手段とから成ること
を特徴とする特許請求の範囲第（１）項記載の半導体装
置の製造方法。(4) The step of forming an opening in the silicon nitride film is the step of forming an opening in the silicon nitride film.
Claim 1, characterized in that it comprises means for anodizing a silicon nitride film using an aluminum wiring as one electrode, and means for selectively removing a chemically formed silicon nitride film formed by the anodic oxidation means. A method for manufacturing a semiconductor device according to item (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360886A JPS62248239A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360886A JPS62248239A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62248239A true JPS62248239A (en) | 1987-10-29 |
Family
ID=14087046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9360886A Pending JPS62248239A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62248239A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01150342A (en) * | 1987-12-07 | 1989-06-13 | Nec Corp | Multilayer interconnection structure and manufacture thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104062A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Production of surface protection film of electronic parts |
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS562654A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Semiconductor device |
| JPS6030153A (en) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-04-22 JP JP9360886A patent/JPS62248239A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104062A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Production of surface protection film of electronic parts |
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS562654A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Semiconductor device |
| JPS6030153A (en) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01150342A (en) * | 1987-12-07 | 1989-06-13 | Nec Corp | Multilayer interconnection structure and manufacture thereof |
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