JPH02188942A - Manufacture of semiconductor device provided with multilayer wiring structure - Google Patents

Abstract

PURPOSE:To prevent a crack reaching the inside of a chip at an interlayer insulating film from being caused by a dicing operation and to make a chip region and a scribing line flat even when the number of wiring layers are increased by a method wherein, simultaneously with a patterning operation of a wiring part to the chip region, a moistureproof ring is formed of a wiring material to be a ring shape around the chip region. CONSTITUTION:Many elements are formed in a chip region 2 on a substrate 1; simultaneously with a patterning operation of a lower-layer wiring part 4 to the chip region 2, a lower-layer moistureproof ring 13 is formed of a wiring material to be a ring shape around the chip region 2. Then, an interlayer insulating film 14 is formed on the chip region 2 and a scribing line 8; after that, an upper-layer wiring part 5 is patterned on the interlayer insulating film 14; and an upper-layer moistureproof ring 15 which is linked to said lower-layer moistureproof ring 13 to be a partition wall shape and which divides the interlayer insulating film 14 into sections is formed. After that, the chip region 2 is covered with a protective film 7; and then, the substrate 1 is cut along the scribing line 8. For example, said upper-layer moistureproof ring 15 is formed; after that, a second interlayer insulating film 16 is formed; an upper-layer wiring part 11 is patterned on it; and an upper-layer moistureproof ring 17 is formed.

Description

[Detailed Description of the Invention] [Required #I] Regarding a method for manufacturing a semiconductor device in which multilayer wiring is formed through a glabellar insulating film, the occurrence of cracks that reach the inside of a chip in the glabellar insulating film due to dicing is prevented from occurring. In order to keep the chip area and scribe lines flat even when the number of wiring layers increases, a large number of elements are formed in the chip area on the substrate, and the lower layer wiring is patterned on the chip area at the same time. A lower layer moisture-resistant ring is formed in a ring shape around the area using a wiring material, and then an interlayer insulating film is formed on the chip area and the scribe line, and then an upper layer wiring is patterned on the glabella insulating film, and a partition wall is formed with the lower layer moisture-resistant ring. After forming an upper moisture-proof ring that continuously divides the glabellar insulating film, the chip area is covered with a protective film, and then the substrate is cut along the scribe line.

[Industrial Field of Application] This invention relates to a method of manufacturing a semiconductor device in which multilayer wiring is formed via an interlayer insulating film.

In recent highly integrated semiconductor devices, a large number of elements are formed on a substrate in the bulk process, and in the subsequent surface process, multilayer wiring is formed on the elements via an insulating film between the eyebrows. Covered with a protective film, the substrate is further cut into a large number of chips along scribe lines in a dicing process.

[Prior Art] Conventionally, in the manufacturing process of a semiconductor device having a multilayer wiring structure, for example, in the two-layer wiring shown in FIG. A first wiring 4 and a second wiring 5 formed of aluminum thereon.
is an interlayer insulating film 6 formed of a PSG film or an S02 film.
A protective film 7 made of a PSG film or the like is formed on the second wiring 5. Then, the interlayer insulating film 6
The protective pA 7 is formed over the entire surface of the substrate 1 and extends up to above the scribe line 8 between each chip region 2.

However, when the substrate 1 formed in this way is cut along the scribe lines 8 in the dicing process, a crack 9 is generated in the interlayer insulating film 6 that extends into the chip 2a, as shown in the figure. This causes a decrease in yield and reliability.

Therefore, if the glabellar insulating film 6 and the protective film 7 on the scribe line 8 are removed by etching as shown in FIG. 3, the generation of cracks in the glabellar insulating film 6 due to dicing can be prevented.

However, in such a structure, the difference in level between the chip area 2 and the scribe line 8 portion becomes large, so the second wiring 5
Alternatively, when applying photoresist during etching of the protective film 7, the photoresist is likely to break at the stepped portions, and if the thickness of the photoresist is increased to prevent this breakage, it becomes difficult to form a fine pattern. .

Further, after etching the interlayer insulating film 6, the second wiring 5 is etched.
When patterning by etching, the wiring material 10 tends to remain on the side wall of the glabella insulating film 6, as shown in FIG.
When the wiring material 10 is etched as shown by the chain line in the figure, the wiring material 10 peels off and becomes particles, and the chip 2
This causes a decrease in yield.

Therefore, as shown in FIG. 5, the protective film 7
Interlayer insulation wA by etching to cover 6
A manufacturing method for preventing peeling of the wiring material 10 remaining on the side wall portion of the culm has been proposed.

[Problems to be Solved by the Invention] However, in the manufacturing method described above, for example, as shown in FIG. ``When the number of m layers is increased, the side wall of the lower interlayer insulating film 6 is covered with the upper glabella insulating film 6,
Furthermore, since the upper interlayer insulating film 6 is covered with the protection wA7, there is a disadvantage that the outer diameter of the chip 2 increases as the number of wiring layers increases. Furthermore, as the number of wiring layers increases, the difference in level between the chip area 2 and the scribe line 8 increases, so there is also the problem that particles are likely to accumulate on the scribe line 8, which has a groove shape.

An object of the present invention is to provide a semiconductor device manufacturing method that prevents the occurrence of cracks that reach the inside of a chip in an interlayer insulating film caused by dicing, and that makes the chip area and scribe line flat even when the number of wiring layers increases. There is something to do.

[Means for Solving the Problems] The above purpose is to form a large number of elements in a chip area on a substrate, and at the same time as patterning the lower layer wiring to the chip area, to form a lower layer moisture-proof ring around the chip area using wiring material. Then, after forming an interlayer insulating film on the chip area and the scribe line, an upper layer wiring is patterned on the interlayer insulating film, and an upper layer moisture-proof ring is connected to the lower layer MH ring like a partition wall and divides the interlayer insulating film. This is achieved by an rH fabrication method in which the chip area is covered with a protective film after formation, and then the substrate is cut along the scribe lines.

[Operation] Since the glabellar insulating film is provided over the entire surface of the substrate and is formed on the chip area and the scribe line, the chip area and the scribe line are flat. The moisture-proof ring prevents cracks that occur in the interlayer insulating film on the scribe lines during dicing from penetrating into the chip.

[Embodiment 1] Hereinafter, an embodiment in which the present invention is embodied in a method of manufacturing a semiconductor device having a three-layer wiring structure will be described with reference to FIG. Note that the same components as those in the conventional example are given the same numbers and detailed explanations will be omitted.

As shown in FIG. 1(a), a large number of openings 3a are formed in the insulation WA3 formed on the substrate 1 prior to the surface process for forming wiring on the substrate 1. Elements 12 are formed in each opening 3a. In this state, the first wiring 4 is first patterned as a lower layer wiring on the insulation M3, and at the same time, the first moisture resistant ring 13 made of the same material as the first wiring 4 is patterned as a lower layer moisture resistant ring in the chip area j1121I. Form. This first moisture-proof ring 13 is formed in an annular shape around the chip region 2 to prevent moisture from entering into the chip 2a, and is formed to cover the boundary between the insulation M3 and the substrate 1. ing.

Subsequently, as shown in FIG. 1(b), a first glabellar insulating film 14 is formed over the entire surface of the substrate 1, and as shown in FIG. 1(c), the first wiring is formed by etching. A through hole 14a is formed at a predetermined position on the first moisture-proof ring 13, and a through hole 14a is formed at a predetermined position on the first moisture-proof ring 13 in the chip area! A contact arm 14b surrounding i2 in an annular shape is formed.

Then, as shown in FIG. 1(d), the second wiring 5 and the second moisture-proof ring 15 are similarly patterned as an upper-layer wiring and an upper-layer moisture-proof ring. Then, the first and second wirings 4.5 are connected through the through hole 14a, and the first and second moisture-proof rings 13.15 are connected over their entire circumferences through the contact groove 14b.

Subsequently, as shown in FIG. 1(e), a second glabellar insulating film 16 is formed over the entire surface of the substrate 1. And Figure 1 (
As shown in FIG.
6b, the third wiring 11 and the third moisture-proof ring 1
7 is patterned as an upper layer wiring and an upper layer moisture-proof ring. At this time, the contact groove 16b is connected to the first glabella insulation l.
By forming the contact groove 14b at a different position from the contact groove 14b formed in the contact groove 8114, the upper surface of the second moisture-proof ring 15 is opened at a flat part, and the second moisture-proof ring 15 and the third moisture-proof ring 17 are connected to each other. The connection is now secure.

Then, as shown in FIG. 1(g), the surface process is completed by forming the protection WA7 in the chip area 2, and when this substrate l is cut along the scribe lines 8 by dicing, as shown in FIG. 1(h). A chip 2a is formed.

Now, in the above manufacturing method, the first and second glabella insulating films 14 and 16 are formed continuously on the scribe line 8 as well as the chip area 2, so even if the number of wiring layers increases, the chip area 2 A large step does not occur between the scribe line 8 and the scribe line 8. Therefore, the patterning or protection of the second and third wirings 5.11 and the second and third moisture-proof rings 15.17 W! Since the thickness of the photoresist applied prior to etching A7 can be made thinner, fine patterns can be easily formed and particles will not accumulate on the scribe line 8. And even if there are many wiring layers, chip 2
The outer diameter of a does not increase.

In addition, moisture-proof rings 13, 15, and 17 for preventing moisture from entering the chip 2 are formed in the shape of a wall surrounding the chip 2, so that dicing is prevented as shown in FIG. 1(h). Even if, for example, a crack 9 occurs in the first glabellar insulating film 14, the second moisture-proof ring 15 can prevent the crack 9 from progressing into the chip 2a. And each moisture resistant ring 13, 15, 17 is placed in each location! 4.5.1
Since they are formed simultaneously during the patterning of step 1, the number of man-hours does not increase.

[Effects of the Invention] As detailed above, the present invention prevents the occurrence of cracks that reach the inside of the chip in the glabellar insulating film caused by dicing, and also prevents the chip area on the substrate and the scribe even if the number of wiring layers is increased. Since the lines can be flattened, this provides an excellent effect of providing a method of manufacturing a semiconductor device that can improve the yield and reliability of chips.

[Brief explanation of the drawing]

FIGS. 1A to 1H are cross-sectional views showing the manufacturing process of a semiconductor device embodying the present invention, and FIGS. 2 to 6 are cross-sectional views showing conventional examples related to the present invention. In the figure, 1 is the substrate, 2 is the chip area, 4 is the first wiring (lower layer wiring), 5 is the second wiring (upper layer wiring), 7 is the protective film,
8 is the scribe line, 11 is the third wiring (upper layer wiring a)
, 13 is a first moisture resistant ring (lower layer moisture resistant link), 14 is a first interlayer insulating film, 15 is a second moisture resistant ring (upper layer moisture resistant ring), 16 is a second interlayer insulating film, and 17 is a third interlayer insulating film. Moisture-resistant link (il) Figure 1: Manufacturing process of the present invention (a) (e) Figure 2: Cross-sectional view of a chip joint made using the conventional M construction method Cross-sectional view Figure 6 Figure 6

Claims (1)

[Claims] 1. Form a large number of elements in the chip area on the substrate, and at the same time as patterning the lower layer wiring to the chip area, form a lower layer moisture-proof ring in an annular shape with wiring material around the chip area, and then place it on the chip area and the scribe line. After forming an interlayer insulating film, patterning an upper layer wiring on the interlayer insulating film, and forming an upper moisture-proof ring that connects with the lower moisture-proof ring in a partition shape and divides the interlayer insulating film, and then covering the chip area with a protective film; 1. A method of manufacturing a semiconductor device having a multilayer wiring structure, the method comprising: then cutting the substrate along the scribe lines.