JP2009076782A - Semiconductor substrate and manufacturing method thereof, and semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate on which more semiconductor chips with high reliability are mounted. <P>SOLUTION: A seal ring portion 22 provided to a chip region 1 and enclosing the chip region 1 comprises a plurality of wiring layers 5, 10, and 11 for seal ring stacked on a silicon wafer 21, where the wiring layer 5 for seal ring as the top layer among the plurality of wiring layers for seal ring is provided extending toward a scribe region 3 more than the other wiring layers 10 and 11 for seal ring, and the wiring layer 5 for seal ring is covered with a surface protection film 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate on which semiconductor chips are arranged, a manufacturing method thereof, and a semiconductor chip.

  When forming semiconductor chips to be mounted / built into various electronic devices, generally, as shown in FIG. 4, elements such as transistors and wirings are formed simultaneously on a silicon wafer (raw substrate). The chip area 1 is formed, and then the scribe area 3 that divides each chip area 1 is diced with a dicing blade or the like to form a cut groove 4 and is divided into individual semiconductor chips.

  Here, due to the mechanical impact at the time of dicing, cracks and chips may occur on the wafer surface starting from the end of the kerf 4, and the wafer surface may propagate to reach the chip region 1. In addition, after the semiconductor chip is mounted on the tape and the resin is sealed between them, if the sealed resin thermally expands and contracts, stress is applied to the semiconductor chip, causing cracks and chips, and even to the chip region. May reach. This crack or chip tends to grow and spread under heat or mechanical stress. For this reason, cracks and chips may spread due to heat or mechanical stress when the semiconductor device (semiconductor chip) is mounted on, for example, a liquid crystal television or the like, and moisture or contaminants may enter the semiconductor chip. Yes, the reliability of the semiconductor chip cannot be maintained.

In order to prevent such cracks and chips from propagating inside the chip region, in a certain semiconductor device, in order to absorb the stress of the resin when the sealed resin is thermally expanded and contracted, In addition, a guard ring is disposed so as to surround the chip region (see, for example, Patent Document 1). Further, in order to prevent cracks during dicing from reaching the chip region, a seal ring is formed that surrounds the chip region of the wafer in order to prevent moisture and contaminants from entering the semiconductor chip, and the region surrounding the seal ring. An electronic device having a stress absorbing wall (guard ring) formed thereon has been developed (see, for example, Patent Document 2). Further, an electronic device in which a stress absorbing groove (slit) is formed in a region surrounding the seal ring has been developed (see, for example, Patent Document 3).
JP 60-18934 A (published January 31, 1985) JP 2006-93407 A (published April 6, 2006) Japanese Laid-Open Patent Publication No. 9-45766 (published February 14, 1997)

  Here, from the production efficiency of semiconductor chips, it is required to increase the number of semiconductor chips (number of chips per semiconductor substrate) that can be cut out from one semiconductor substrate (semiconductor wafer).

  However, as described above, in order to provide the stress absorbing wall or slit around the seal ring, it is necessary to secure a region for forming the stress absorbing wall or slit. For this reason, the number of semiconductor chips per semiconductor substrate cannot be increased.

  That is, in the conventional technology, it is impossible to achieve both the manufacture of a semiconductor chip in which moisture and contaminants do not enter inside and ensure reliability and the increase in the number of semiconductor chips per semiconductor substrate. Also, if a slit is provided to prevent cracks during dicing from reaching the chip area, for example, in an electronic device in which a gold bump is formed on a semiconductor chip by an electroplating method such as a liquid crystal driver, plating is performed at the slit step. As a result, the coverage of the gold film formed by the sputtering method, which becomes the seed layer, deteriorates, and stable plating power supply cannot be performed. As a result, it causes adverse effects such as deterioration of gold bump height variation.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor substrate having a large number of highly reliable semiconductor chips, a manufacturing method thereof, and a semiconductor chip.

  In order to solve the above problems, a semiconductor substrate according to the present invention is a semiconductor substrate in which a plurality of chip regions separated from each other by a scribe region are provided on a raw substrate, and a protective film is formed on the surface. The seal ring is provided in a region and is formed so as to surround each of the chip regions, and the seal ring includes a plurality of seal ring wiring layers stacked on the raw substrate. The uppermost layer of the wiring layers is characterized in that it is provided so as to extend in the direction toward the scribe region from the other sealing ring wiring layers.

  According to the above configuration, the uppermost layer (uppermost layer wiring layer) of the plurality of sealing ring wiring layers is extended in the direction toward the scribe region more than the other sealing ring wiring layers. Here, although the surface of the semiconductor substrate is covered with a protective film, the protective film on the uppermost wiring layer is formed on the side of the scribe region due to the extended portion (extended portion) in the uppermost wiring layer. A step is formed. In addition, this step is close to the scribe region by the amount that the uppermost wiring layer is extended in the direction toward the scribe region with respect to the other seal ring wiring layer formation region. Formed at points. Therefore, when cracks or chips propagate through the substrate surface during dicing, the propagation can be blocked by this step. Further, even when cracks extend toward the raw substrate along this step, the cracks are prevented from propagating to other seal ring wiring layers. Therefore, even if the width of the scribe region is narrowed, propagation of cracks and chips generated during dicing can be prevented. That is, the extended portion and the step can be used as a guard ring. Furthermore, since the seal ring portion is not damaged, the seal ring portion can reliably prevent moisture and contaminants from entering the chip region.

  Further, as described above, since the width of the scribe area can be reduced, the number of chip areas (semiconductor chips) per semiconductor substrate can be increased.

  Therefore, according to the above configuration, it is possible to provide a semiconductor substrate in which the number of mounted semiconductor chips in which moisture and contaminants do not enter the inside and the reliability is ensured is increased.

  A substrate on which an integrated circuit or the like is not built is called a raw substrate.

  Here, the uppermost layer of the plurality of seal ring wiring layers is provided to extend in a direction toward the scribe region in a range of 0.5 to 2 μm from the other seal ring wiring layers. Is preferred. Within this range, it is possible to effectively prevent the occurrence of cracks inside the chip region and increase the number of semiconductor chips per semiconductor substrate.

  In the semiconductor substrate according to the present invention, in addition to the above-described configuration, the plurality of seal ring wiring layers are separated by an interlayer insulating film and connected by via portions provided in the interlayer insulating film. Among the via portions connected to the uppermost layer of the plurality of seal ring wiring layers, the via portion closest to the scribe region is a scribe region side end portion closer to the scribe region in the uppermost layer. It is arranged in a region closer to the chip region side end than an intermediate point with the chip region side end which is the opposite end.

  Of the via portions connected to the uppermost layer (uppermost layer wiring layer) of the plurality of seal ring wiring layers, the via portion closest to the scribe region is directly above when the via portion is formed to be recessed. In other words, a recess in the uppermost wiring layer is induced, thereby forming a recess in the protective film. Therefore, when cracks or chips propagate through the substrate surface during dicing, if the mechanical impact is received at the step formed on the scribe region side of the uppermost wiring layer, the protective film peels off along this recess, and the A part of the upper wiring layer is exposed, and the reliability of the semiconductor chip is impaired. In order to avoid this, the via portion is preferably disposed in a region closer to the end portion on the chip region side than an intermediate point between the end portion on the scribe region side and the end portion on the chip region side in the uppermost wiring layer.

  Further, in order to solve the above problems, a semiconductor substrate manufacturing method according to the present invention is a semiconductor in which a plurality of chip regions separated from each other by a scribe region are provided on a raw substrate and a protective film is formed on the surface. In the substrate manufacturing method, in each of the chip regions, a plurality of seal ring wiring layers are stacked on the raw substrate so as to surround the chip region, and the uppermost layer of the plurality of seal ring wiring layers Including a seal ring forming step of extending in the direction of the scribe region as compared with the other wiring layers for the seal ring.

  According to the above method, the semiconductor substrate having the same effect as the semiconductor substrate according to the present invention described above and having a larger number of semiconductor chips in which moisture and contaminants do not enter and the reliability is ensured is manufactured. be able to. In addition, by forming the seal ring part extended in the direction from the other layer toward the scribe region and the connection wiring of the chip region together (simultaneously), without increasing the new manufacturing process, A seal ring portion in which the uppermost layer of the seal ring wiring layer extends in a direction from the other layers toward the scribe region can be formed.

  The semiconductor chip according to the present invention is obtained by cutting one of the semiconductor substrates along the scribe region.

  According to the above configuration, it is possible to provide a high-quality semiconductor chip with high reliability in which generation of cracks and chips is prevented.

  As described above, the semiconductor substrate according to the present invention includes a seal ring provided in each of the chip regions and surrounding each of the chip regions, and the seal ring is stacked on the raw substrate. It is composed of a plurality of seal ring wiring layers, and the uppermost layer of the plurality of seal ring wiring layers is provided so as to extend in the direction toward the scribe region from the other seal ring wiring layers. .

  Although the surface of the semiconductor substrate is covered with a protective film, the protective film on the uppermost wiring layer has a step on the scribe region side due to the extended portion (extension part) in the uppermost wiring layer. It is formed. In addition, this step is close to the scribe region by the amount that the uppermost wiring layer is extended in the direction toward the scribe region with respect to the other seal ring wiring layer formation region. Formed at points. Therefore, when cracks or chips propagate through the substrate surface during dicing, the propagation can be blocked by this step. Further, even when cracks extend toward the raw substrate along this step, the cracks are prevented from propagating to other seal ring wiring layers. Therefore, even if the width of the scribe region is narrowed, propagation of cracks and chips generated during dicing can be prevented. That is, the extended portion and the step can be used as a guard ring. Furthermore, since the seal ring portion is not damaged, the seal ring portion can reliably prevent moisture and contaminants from entering the chip region.

  Further, as described above, since the width of the scribe area can be reduced, the number of chip areas (semiconductor chips) per semiconductor substrate can be increased.

  Therefore, according to the above configuration, it is possible to provide a semiconductor substrate in which the number of mounted semiconductor chips in which moisture and contaminants do not enter the inside and the reliability is ensured is increased.

  An embodiment of the present invention will be described below with reference to FIGS. Note that the present invention is not limited to this.

(Configuration of semiconductor substrate)
First, the configuration of the semiconductor substrate of this embodiment (a state in which a semiconductor chip is formed on a wafer that is a raw substrate) will be described.

  FIG. 1 is a plan view showing a part of the semiconductor substrate 20 of the present embodiment. Further, as shown in FIG. 1, the semiconductor substrate 20 includes a plurality of chip regions 1 in which an integrated circuit (not shown) and electrode pads 2 are provided on a silicon wafer (raw substrate) 21, and the plurality of chips. There is a scribe region 3 that divides the region 1 into regions. Further, as shown in FIG. 2, a surface protective film 6 is formed on the surface of the semiconductor substrate 20. 2 is a cross-sectional view of the semiconductor substrate 20 of FIG. 3 is an enlarged view of the seal ring portion 22 in the cross-sectional view of FIG.

  FIG. 2 is a view showing the vicinity of the boundary between the scribe area 3 and the chip area 2. That is, on the side (not shown) beyond the scribe center (the right side in FIG. 2), the scribe area extends to the chip edge of another chip area (not shown) adjacent to the chip area shown across the scribe area. It is continuing. The chip edge is a boundary between the chip region 1 and the scribe region 3, and when diced, an end face of the separated semiconductor chip comes to at least the scribe region 3 side from this edge. In other words, a part of the scribe region 3 becomes an end portion of the semiconductor chip. Further, the scribe center is merely the center of the scribe region 3, and at the time of dicing, the semiconductor substrate 20 is cut with a width within the scribe region 3 with the scribe center as a substantial center.

  As shown in FIG. 2, the chip region 1 (semiconductor chip) of the semiconductor substrate 20 is provided so as to surround the chip region 1 in the vicinity of the boundary between the active region in which the integrated circuit is provided and the scribe region 3 in the chip region 1. The seal ring part 22 is provided.

  The seal ring portion 22 is provided in order to prevent moisture and contaminants from entering the chip region 1 and, as shown in FIG. 3, a plurality of seal ring wiring layers 5, 10, 11 and vias (vias). Part) 12,13,14. Here, the sealring wiring layer 5 is the uppermost layer (uppermost wiring layer) among the plurality of sealring wiring layers. Further, a surface protective film 6 is deposited on the sealring wiring layer 5. The via 14 connects the silicon wafer 21 and the seal ring wiring layer 11, the via 13 connects the seal ring wiring layer 11 and the seal ring wiring layer 10, and the via 12 seals The ring wiring layer 10 and the seal ring wiring layer 5 are connected. The vias 12, 13, and 14 are not formed in a hole shape, but are formed in a groove shape that continuously surrounds the outer periphery of the chip region 1. In this embodiment, as shown in FIG. 3, the vias 12, 13, and 14 are provided between the seal ring wiring layers from the top, two, two, and three, but at least the seal ring wiring layers are provided. One or more of each may be provided.

  In addition, an interlayer insulating film is disposed at a location where the vias 12, 13, and 14 do not exist between the seal ring wiring layers 5, 10, and 11. The first interlayer insulating film 23 is between the silicon wafer 21 and the seal ring wiring layer 11, the second interlayer insulating film 8 is between the seal ring wiring layer 11 and the seal ring wiring layer 10, and the third interlayer insulation. The film 7 is disposed between the sealring wiring layer 10 and the sealring wiring layer 5. In the active region of the semiconductor substrate 20, the first wiring 9, the second wiring 15, and the third wiring 16 are respectively formed on the silicon wafer 21 with the first interlayer insulating film 23, the second interlayer insulating film 8, and Wiring is performed via the third interlayer insulating film 7. The first wiring 9, the second wiring 15, and the third wiring 16 are connected by vias (not shown). Further, the first interlayer insulating film 23, the second interlayer insulating film 8, the third interlayer insulating film 7, and the surface protective film 6 are deposited also in the scribe region 3. That is, the first interlayer insulating film 23, the second interlayer insulating film 8, the third interlayer insulating film 7, and the surface protective film 6 are provided as continuous layers in the chip region 1 and the scribe region 3, respectively.

  Here, as shown in FIG. 3, among the plurality of seal ring wiring layers 5, 10, and 11, the seal ring wiring layer 5 that is the uppermost layer is more than the other seal ring wiring layers 10 and 11. , Extending in the direction toward the scribe region 3. In the following description, the portion of the sealring wiring layer 5 that extends in the direction toward the scribe region 3 is referred to as an extended portion. Since the surface protective film 6 is deposited on the sealring wiring layer 5 having such an extended portion, a step 31 is formed in the surface protective film 6 due to the extended portion. The step 31 is extended in a direction in which the seal ring wiring layer 5 is directed to the scribe region 3 more than the other seal ring wiring layers 10 and 11 with respect to the formation region of the other seal ring wiring layers 10 and 11. It is formed at a location close to the scribe region 3 by an amount (extended portion).

  Of the vias 12 connected to the seal ring wiring layer 5, the vias closest to the scribe region 3 are the scribe region side end portion closer to the scribe region 3 and the opposite end portion of the seal ring wiring layer 5. It is arranged in a region closer to the chip region side end than the middle point with the chip region side end. The via closest to the scribe region among the vias 12 connected to the seal ring wiring layer 5 induces a depression of the uppermost seal ring wiring layer 5 when the via is formed to be depressed. A depression of the surface protective film 6 is formed. Therefore, when cracks or chips propagate through the surface of the semiconductor substrate 10 during dicing, if a mechanical shock is received at the step 31 formed on the scribe region 3 side of the sealring wiring layer 5, the surface along the depression The protective film 6 is peeled off, and a part of the seal ring wiring layer 5 is exposed to impair the reliability of the semiconductor chip. In order to avoid this, the via 12 is preferably disposed in a region closer to the chip region side end than an intermediate point between the scribe region side end and the chip region side end in the seal ring wiring layer 5.

  In this embodiment, the seal ring wiring layers 5, 10, and 11 are connected by the vias 12, 13, and 14, but the connection portion between the seal ring wiring layers 5, 10, and 11 is formed in the chip region. As long as it is provided so as to surround 1, it may be formed in any way. For example, the seal ring wiring layer may be laminated as it is without any intervention (in this case, the seal ring wiring layer becomes thick).

  In the present embodiment, SM + 20 μm is set as the scribe half width (SW) with respect to the half width (SM) of the metal material remaining in the scribe region 3. Of course, SW is not limited to this value. In this embodiment, the width of the dicing blade is selected so that all the metal material remaining in the scribe region 3 is removed during dicing. Depending on the width of the dicing blade, the scribe half width (SW) is further reduced. Can be achieved.

  The distance between the chip edge and the active area wiring (SMS) or the distance between the chip edge and the active area (SDS) is 10 μm, but is not limited to this value. In this embodiment, the width (EQSW) of the seal ring wiring layer 5 is 6 μm, the width (ESW) of the other seal ring wiring layers 10 and 11 is 5 μm, and the extension of the seal ring wiring layer 5 is The length is 1 μm, but these values are not limited. When the length of the extended portion of the seal ring wiring layer 5 is in the range of 0.5 to 2 μm, it is possible to effectively prevent the occurrence of cracks on the side of the chip region 1 and The number of semiconductor chips (chip region 1) can be increased.

  Moreover, in this embodiment, although the thickness of the semiconductor substrate 20 is 300-725 micrometers, it is not limited to this range.

  Further, the distance (UHW) from the end portion (chip edge) of the seal ring wiring layer 5 to the via nearest to the scribe region among the vias 12 connected to the seal ring wiring layer 5 is 3. Although it is 5 μm, this value is not limited.

  Here, when the semiconductor substrate 20 is diced along the scribe region 3, a cut groove 4 is formed in the semiconductor substrate 20, and the chip region 1 is cut from each other and separated into semiconductor chips (semiconductor devices). At the time of dicing, impacts or stresses, etc., or chips or cracks resulting from them are generated from the kerfs 4 and propagate in the direction of the chip region 1. These impacts, stresses, cracks, etc. Stopped because there is an extension of. More specifically, it is stopped by the step 31 of the surface protective film 6 formed due to the extended portion of the sealring wiring layer 5. That is, further propagation of these impacts, stresses or cracks in the direction of the chip region 1 is prevented by the extended portion of the seal ring wiring layer 5 and the step 31. The diced cross section is formed without being in contact with the seal ring wiring layers 5, 10, 11. Therefore, even if the width of the scribe region 3 is narrowed, it is possible to prevent the impact, stress, etc. from being propagated to the chip region generated during dicing, and to prevent the propagation of cracks and chips caused by the impact, stress, etc. Can do. That is, the extended portion and the step 31 can be used as a guard ring.

  As a result, the seal ring part 22 is not damaged, so that the function of the seal ring part 22 for preventing moisture, contaminants, etc. from entering the chip region 1 from the outside is maintained. A high semiconductor chip can be manufactured. As described above, since the width of the scribe region 3 can be reduced, the number of chip regions 1 (semiconductor chips) per semiconductor substrate 20 can be increased. Therefore, the semiconductor substrate 20 can increase the number of semiconductor chips in which reliability is ensured without moisture or contaminants entering the inside.

  A dotted line surrounding the semiconductor substrate 20 in FIG. 1 represents a size of a part of the semiconductor substrate when the seal ring wiring layer 5 is not extended. The semiconductor substrate that does not extend the seal ring wiring layer 5 needs to have a certain width of the scribe region 3 in order to prevent the effects of chipping and cracks from being propagated to the chip region 1, and the scribe region 3 cannot be narrowed. Therefore, the number of semiconductor chips cannot be increased as compared with the semiconductor substrate 20 of the first embodiment in which the seal ring wiring layer 5 is extended.

(Semiconductor substrate manufacturing method)
Next, a method for manufacturing the semiconductor substrate 20 will be described with reference to FIG. First, an active region constituting an element such as a transistor is formed in the chip region 1 of the silicon wafer 21. Here, on the silicon wafer 21, between the active region and the region where the seal ring portion 22 is formed, and between the region where the seal ring portion 22 is formed and the chip edge (extension portion of the seal ring wiring layer 5). LOCOS (Local Oxidation of Silicon) may be formed in the region immediately below the uppermost layer.

  Next, after depositing a first interlayer insulating film 23 on the silicon wafer 21, a via hole for forming a via (not shown) in an active region is formed in the first interlayer insulating film 23, and the seal ring portion 22 is formed. A via hole for forming the via 14 is formed. Here, it can be formed using, for example, lithography and dry etching. Here, the via 14 is formed by embedding a conductive film in a groove-like recess continuously surrounding the chip region 1. Each of these vias can be formed by embedding a conductive film in each via hole using, for example, a known method of W deposition / CMP. In this embodiment, the via hole for forming the via in the active region and the via hole for forming the via 14 are simultaneously formed in the first interlayer insulating film 23, but may be formed separately.

  Next, the first wiring 9 in the active region and the seal ring wiring layer 11 in the seal ring portion 22 are wired on the first interlayer insulating film 23. At this time, an accessory wiring serving as a lithography alignment mark or the like may be formed on the first interlayer insulating film 23 in the scribe region 3.

  Next, the second interlayer insulating film 8 is formed on the first interlayer insulating film 23, and the vias and vias 13 in the active region are simultaneously formed in the same manner as described above, and the second wiring 15 and the seal ring portion 22 in the active region are formed simultaneously. The seal ring wiring layer 10 is simultaneously formed. Next, the third interlayer insulating film 7 is formed on the second interlayer insulating film 8, and the vias and vias 12 in the active region are simultaneously formed in the same manner as described above, and the third wiring 16 and the seal ring portion in the active region are formed. Twenty-two seal ring wiring layers 5 are formed simultaneously. Here, of the vias 12 connected to the seal ring wiring layer 5, the via 12 closest to the scribe region 3 is a region closer to the active region than the center of the seal ring wiring layer 5 (of the seal ring wiring layer 5, It is provided in a region closer to the chip region side end than an intermediate point between the scribe region side end closer to the scribe region 3 and the chip region side end opposite to the scribe region end. Further, the seal ring wiring layer 5 is formed so as to extend in the direction toward the scribe region 3 from the other seal ring wiring layers 10 and 11. That is, an extended portion of the seal ring wiring layer 5 is formed here.

  Thereafter, a surface protective film 6 serving as a protective film is deposited on the third wiring 16 and the sealring wiring layer 5 which are the uppermost wiring layers. Here, a step 31 of the surface protective film 6 is formed on the sealring wiring layer 5. Subsequently, the surface protection film 6 on the third wiring 16 is partially opened by lithography and dry etching, for example, and then the electrode pad 2 connected to the third wiring 16 is formed in the opening. Thereby, the semiconductor substrate 20 in which the plurality of chip regions 1 are formed is formed.

  As described above, according to the present embodiment, each via in the active region and each wiring 9, 15, 16 are formed, and at the same time, the vias 12, 13, 14 and the seal ring wiring layers 5, 10, 11 are formed. The seal ring part 22 can be formed. Therefore, the seal ring portion 22 in which the seal ring wiring layer 5 is extended in the direction toward the scribe region 3 from the other seal ring wiring layers 10 and 11 can be formed without increasing a new manufacturing process. .

  In this embodiment, wirings (active region wirings and seal ring wiring layers) are formed in the interlayer insulating film stacked in three layers. However, the number of interlayer insulating films is not limited to three. There may be fewer or more than three depending on the chip structure.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in the embodiments are also included. It is included in the technical scope of the present invention.

  It can be used for semiconductor chips mounted on or incorporated in electronic devices, and can be widely applied from consumer electronics products to industrial electronics products and electronic components. For example, it can be used for portable communication terminals, personal computers, home appliances, medical devices, game devices, and the like.

It is a top view which shows a part of semiconductor substrate of one Embodiment of this invention. It is A-A 'arrow sectional drawing of the semiconductor substrate of FIG. It is an enlarged view of the seal ring part provided in the semiconductor substrate of FIG. It is a top view which shows a part of conventional semiconductor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Chip area | region 2 Electrode pad 3 Scribe area | region 4 Cut groove 5 Wiring layer for seal rings (The uppermost layer of the wiring layers for several seal rings)
6 Surface protective film (protective film)
10, 11 Wiring layer for seal ring (other wiring layers for seal ring)
12, 13, 14 Via (via part)
20 Semiconductor substrate 21 Silicon wafer (raw substrate)
22 Seal ring 31 Level difference

Claims (5)

In a semiconductor substrate in which a plurality of chip regions separated from each other by a scribe region are provided on a raw substrate and a protective film is formed on the surface,
Provided in each of the chip regions, comprising a seal ring portion formed surrounding each of the chip regions,
The seal ring portion is composed of a plurality of seal ring wiring layers stacked on the raw substrate, and the uppermost layer of the plurality of seal ring wiring layers is more than the other seal ring wiring layers, A semiconductor substrate, wherein the semiconductor substrate is provided extending in a direction toward the scribe region.   2. The uppermost layer of the plurality of seal ring wiring layers is provided to extend in a range of 0.5 to 2 μm from the other seal ring wiring layers. The semiconductor substrate as described. The plurality of seal ring wiring layers are separated by an interlayer insulating film and connected by via portions provided in the interlayer insulating film,
The via part is
Among the via portions connected to the uppermost layer of the plurality of seal ring wiring layers, the via portion closest to the scribe region is the scribe region side end portion closer to the scribe region in the uppermost layer and the opposite side thereof. 3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is disposed in a region closer to a chip region side end than an intermediate point with a chip region side end that is an end of the semiconductor substrate. In a method for manufacturing a semiconductor substrate, wherein a plurality of chip regions separated from each other by a scribe region are provided on a raw substrate, and a protective film is formed on the surface.
In each of the chip regions, a plurality of seal ring wiring layers are stacked on the raw substrate so as to surround the chip regions, and the uppermost layer of the plurality of seal ring wiring layers is used as the other seal. A method of manufacturing a semiconductor substrate, comprising: a seal ring portion forming step of extending in a direction of the scribe region from a ring wiring layer.   A semiconductor chip separated by cutting the semiconductor substrate according to any one of claims 1 to 3 along the scribe region.

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