JP2005260059A - Semiconductor device, and method of manufacturing semiconductor wafer and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high reliability semiconductor device by preventing the propagation of cracks and fine exfoliation, occurring at the time of cutting a semiconductor wafer to an active element region, and to provide a method of manufacturing the semiconductor wafer and the semiconductor device. <P>SOLUTION: The semiconductor device comprises a silicon substrate 1 which has a principal plane 1a and has an active element region 101 where a semiconductor element is formed and a cut region 102 extended around the active element region 101, both of which are defined on the principal plane 1a; and an interlayer insulating film 2 formed on the principal plane 1a. In the interlayer insulating film 2, a trench 8 is formed at a part corresponding to the cut region 102. The semiconductor device is also provided with a sacrificial layer 3, containing a non-metal material with which the trench 8 is filled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to a semiconductor device, a semiconductor wafer, and a method for manufacturing a semiconductor device, and more specifically, a semiconductor device, a semiconductor wafer, and a semiconductor device cut out from a semiconductor wafer by cutting using a dicing blade. It relates to a manufacturing method.

  In recent years, there has been a demand for reducing wiring resistance and mutual inductance between wirings for the purpose of reducing the wiring width and wiring distance of a semiconductor device. In order to meet this requirement, copper is generally used as a wiring for reducing wiring resistance, and a material having a low dielectric constant is used as an interlayer insulating film for reducing mutual inductance between wirings.

  Further, in order to prevent fine peeling and cracks generated during the process of cutting the semiconductor wafer from proceeding to the active element region of the semiconductor device, and further to prevent moisture from entering the active element region of the semiconductor device. In addition, a wall structure using a wiring material is provided between the cutting area cut by the dicing blade and the active element area.

  As such a semiconductor device, for example, JP-A-60-216565 discloses a guard ring layer made of aluminum in a cutting region in order to prevent the influence of mechanical distortion such as chipping from reaching the internal element region. A method for dicing a wafer to be formed is disclosed (Patent Document 1). Japanese Patent Laid-Open No. 8-339976 discloses a semiconductor device in which a wall portion is provided on a scribe line for the purpose of preventing cutting into an integrated circuit during dicing (Patent Document 2). ). The wall portion is provided so as to surround the integrated circuit at a position spaced apart from the integrated circuit.

Furthermore, in Japanese Patent Laid-Open No. 5-129430, a metal film composed of two layers of titanium and gold is formed on the boundary between the protective film and the scribe line in order to prevent peeling of the protective film formed on the semiconductor chip. A disclosed semiconductor device is disclosed (Patent Document 3). Furthermore, Japanese Patent Application Laid-Open No. 2002-43356 discloses a semiconductor wafer intended to suppress chipping on the back surface of a semiconductor chip when the semiconductor wafer is cut (Patent Document 4). In the semiconductor wafer disclosed in Patent Document 4, a resin film is provided so as to cover the semiconductor element region. The resin film is formed except for the opening provided in the bonding pad and the boundary region provided for chip separation.
JP-A-60-216565 JP-A-8-339976 JP-A-5-129430 JP 2002-43356 A

  As described above, in the conventional semiconductor device, the wiring is formed from copper, and the interlayer insulating film is formed from a material having a low dielectric constant. However, the corrosiveness of copper is very high compared to aluminum that has been used as a wiring material. For this reason, when copper is exposed to the cut surface when the semiconductor wafer is cut using the dicing blade, there arises a problem that corrosion easily proceeds from the exposed portion. Further, when copper is used as a wiring material, the above-described wall structure is also formed from copper. For this reason, the wall structure itself corrodes and expands, which causes a problem that the moisture resistance of the semiconductor device deteriorates conversely.

  In addition, a material having a low dielectric constant used for the interlayer insulating film is formed in a porous structure in which air is taken in or by a method of sparse molecular structure. Table 1 shows a general interlayer insulating film and its physical characteristics. As can be seen with reference to Table 1, the material having a low dielectric constant decreases from 1/5 to 1/8 in both the modulus of elasticity and hardness as compared with materials conventionally used for interlayer insulating films. . For this reason, these materials have reduced resistance to fine peeling and cracks generated when the semiconductor wafer is cut, and there is an increased risk of exposing copper used for wiring and wall structures.

  In order to solve such a problem, a technique has been studied in which a distance from the cutting region of the semiconductor device to the wall structure is set large, or a wall structure is not provided at the expense of moisture resistance. However, when the former method is adopted, the apparent size of the semiconductor device is increased by setting a wide cutting region, which causes a problem that the productivity of the semiconductor device is lowered. In addition, when the latter method is adopted, the reliability of moisture proof is inevitably lowered.

  In order to prevent the generation of cracks, a method of cutting the semiconductor device with a dicing blade after fusing and removing the interlayer insulating film by laser processing or the like is also conceivable. However, in this case, new problems such as reduction in productivity due to the addition of processes and treatment of gas generated during processing occur. In addition, a new technical problem occurs such that the cutting area must be configured to be capable of laser processing.

  Accordingly, an object of the present invention is to solve the above-described problem, and prevents a crack or fine separation generated when a semiconductor wafer is cut from propagating to an active element region, thereby providing a highly reliable semiconductor device and semiconductor. It is to provide a method for manufacturing a wafer and a semiconductor device.

  A semiconductor device according to the present invention has a main surface, and a semiconductor in which an active element region in which a semiconductor element is formed and an inactive element region extending around the active element region are defined on the main surface A substrate and an interlayer insulating film formed on the main surface are provided. In the interlayer insulating film, a first groove is formed in the inactive element region. The semiconductor device further includes a first sacrificial layer filling the first trench and including a non-metallic material.

  According to the present invention, it is possible to provide a highly reliable semiconductor device, a semiconductor wafer, and a method for manufacturing a semiconductor device by preventing cracks and fine separation that occur during cutting of a semiconductor wafer from propagating to an active element region. Can do.

  Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 1 is drawn with some structures omitted. FIG. 2 is a cross-sectional view of the semiconductor device along the line II-II in FIG.

  1 and 2, semiconductor device 10 includes a silicon substrate 1 having a main surface 1a, an interlayer insulating film 2 deposited on main surface 1a, and a sacrificial layer 3 formed on interlayer insulating film 2. , Wall structure 5 and active wiring 7, and protective film 9 formed on top surface 2 a of interlayer insulating film 2.

  On the main surface 1a, a semiconductor element is formed. An active element region 101 which is an operation region in the semiconductor device 10 and a semiconductor element are not formed. In the semiconductor wafer cutting step which will be described later, the semiconductor device An inactive element region 102 reserved for cutting 10 from the semiconductor wafer is defined. The semiconductor device 10 has a substantially rectangular shape when the main surface 1a is viewed from the front side. The inactive element region 102 extends in a band shape along the substantially rectangular periphery. The active element region 101 is located at a position surrounded by the inactive element region 102, that is, a central portion of a substantially rectangular shape.

Interlayer insulating film 2 is formed on main surface 1a. Interlayer insulating film 2 is composed of interlayer insulating films 2p, 2q, 2r and 2s which are sequentially stacked on main surface 1a. The interlayer insulating film 2 is made of, for example, SiO, SiOC, SiN, SiC, SiO ₂ or SiCN. The interlayer insulating films 2p, 2q, 2r, and 2s may be formed from the same material or different materials. Interlayer insulating film 2 has a top surface 2a extending in parallel to main surface 1a at a distance from main surface 1a, and a side surface 2b continuous from top surface 2a to main surface 1a.

A protective film 9 is formed on the top surface 2 a so as to be located in the active element region 101. The protective film 9 is formed so as to cover a part of the wall structure 5 exposed on the top surface 2a. The protective film 9 is made of, for example, SiO ₂ or polyimide.

  In the interlayer insulating film 2, a groove 8 is formed in the inactive element region 102. The trench 8 opens to the top surface 2a side of the interlayer insulating film 2, and reaches from the top surface 2a to the main surface 1a. The groove 8 extends in a band shape so as to surround the active element region 101. The trench 8 continuously extends without interruption on a line along the side surface 2 b of the interlayer insulating film 2. The bottom surface of the groove 8 is formed by the main surface 1a, and both side surfaces of the groove 8 are formed by the inner wall of the interlayer insulating film 2 extending in a direction that forms an angle with respect to the main surface 1a. In the present embodiment, the groove 8 is configured to reach the main surface 1a from the top surface 2a of the interlayer insulating film 2. However, the present invention is not limited to this, and the bottom surface of the groove 8 is formed in the interlayer insulating film 2. It may be configured.

The groove 8 is filled with the sacrificial layer 3. The sacrificial layer 3 is formed of, for example, a non-metallic material such as SiO, SiOC, SiN, SiC, SiO ₂ and SiCN (including those added with these elements) or a material for insulating between layers or wirings. Yes. The non-metallic material mentioned here does not include a metal material used as a wiring such as aluminum (Al), copper (Cu), or tungsten (W). The sacrificial layer 3 may be formed of the same material as the interlayer insulating film 2 or may be formed of a material different from that of the interlayer insulating film 2.

  In the interlayer insulating film 2, a groove 13 is formed at the boundary between the active element region 101 and the inactive element region 102. The trench 13 extends from the top surface 2a of the interlayer insulating film 2 to the main surface 1a. The groove 13 circulates on the boundary line between the active element region 101 and the inactive element region 102 inside the groove 8. The groove 13 is filled with a metal layer such as aluminum, copper, or tungsten, and the wall structure 5 is constituted by this metal layer. With such a configuration, the wall structure 5 is interposed between the active element region 101 and the inactive element region 102.

  In the interlayer insulating film 2, active wiring 7 is formed in the active element region 101. The active wiring 7 is made of, for example, aluminum, copper or tungsten. The active wiring 7 is electrically connected to the semiconductor elements formed in the active element region 101, and actually functions as a wiring layer of these semiconductor elements.

  By providing the wall structure 5 separately from the active wiring 7 in this way, when the semiconductor device 10 is used in a high temperature and high humidity environment, moisture absorbed from the side surface 2b side of the interlayer insulating film 2 is reduced. Intrusion into the active element region 101 can be prevented. Thereby, since the moisture resistance of the semiconductor device 10 can be improved, the semiconductor element formed in the active element region 101 can function appropriately. When the wall structure 5 is formed of the same metal material as that of the active wiring 7, the wall structure 5 and the active wiring 7 can be formed in the same process. Thereby, the above-mentioned effect by wall structure can be acquired, without increasing a manufacturing process.

  Semiconductor device 10 according to the first embodiment of the present invention has a main surface 1 a, an active element region 101 in which a semiconductor element is formed on main surface 1 a, and inactive extending around active element region 101. A silicon substrate 1 as a semiconductor substrate in which an element region 102 is defined, and an interlayer insulating film 2 formed on a main surface 1a are provided. In the interlayer insulating film 2, a groove 8 as a first groove is formed in the inactive element region 102. The semiconductor device 10 further includes a sacrificial layer 3 as a first sacrificial layer that fills the trench 8 and includes a non-metallic material.

  Interlayer insulating film 2 has a top surface 2a and a side surface 2b connected to top surface 2a. Groove 8 is open to the top surface 2a side and extends parallel to main surface 1a. The trench 8 is defined by the inner wall of the interlayer insulating film 2 extending in a direction that forms an angle with the main surface 1a. The interlayer insulating film 2 is further formed with a groove 13 as a second groove extending at the boundary between the active element region 101 and the inactive element region 102. The semiconductor device 10 further includes a wall structure 5 as a metal layer filling the groove 13. The groove 8 extends continuously on a line extending along the side surface 2b. The groove 8 extends from the top surface 2a to the main surface 1a. The groove 8 is formed so as to surround the active element region 101.

  Next, a method for manufacturing the semiconductor device 10 shown in FIG. 1 will be described. FIG. 3 is a perspective view showing the steps of the method for manufacturing the semiconductor device shown in FIG. Referring to FIG. 3, first, a predetermined semiconductor manufacturing process such as a film forming process and a photolithography process is performed on a wafer-like silicon substrate, and a semiconductor wafer 11 in which a plurality of semiconductor devices 10 shown in FIG. 1 are formed. Is made. A plurality of semiconductor devices 10 arranged in a lattice pattern are formed on the semiconductor wafer 11, and the inactive element region 102 in which the sacrificial layer 3 is formed is located between adjacent semiconductor devices 10. . Between the adjacent semiconductor devices 10, an inactive element region 102 is located and a dicing line 12 extends.

  Next, the semiconductor wafer 11 is cut along the dicing line 12 using the dicing blade 14. A plurality of semiconductor devices 10 are cut out from the semiconductor wafer 11 by this cutting step. The cut surface formed by the dicing blade 14 becomes the side surface 2 b of the interlayer insulating film 2 that forms the outer shape of the semiconductor device 10.

  The manufacturing method of the semiconductor device 10 according to the first embodiment of the present invention includes a step of forming a semiconductor wafer 11 in which a plurality of semiconductor devices 10 are provided side by side. Each of the plurality of semiconductor devices 10 has a main surface 1 a, an active element region 101 in which a semiconductor element is formed on the main surface 1 a, and an inactive element region 102 extending around the active element region 101. Are defined, and an interlayer insulating film 2 formed on the main surface 1a. In the interlayer insulating film 2, a groove 8 is formed in the inactive element region 102. Each of the plurality of semiconductor devices 10 further includes a sacrificial layer 3 that fills the trench 8 and includes a non-metallic material. The manufacturing method of the semiconductor device 10 further cuts the semiconductor wafer 11 along the dicing line 12 located in the inactive element region 102 and extending between the semiconductor devices 10 adjacent to each other. 10 is provided.

  A semiconductor wafer 11 according to the present invention is a semiconductor wafer in which a plurality of semiconductor devices 10 are arranged in a lattice pattern. An inactive element region 102 in which the sacrificial layer 3 is formed is located at a position where the plurality of semiconductor devices 10 are adjacent to each other.

  4 to 15 are cross-sectional views showing the steps of the method for manufacturing the sacrificial layer. The sacrificial layer 3 included in the semiconductor device 10 shown in FIG. 2 can be formed using a manufacturing method described below with reference to FIGS. 4 to 15 show positions corresponding to the cross section shown in FIG.

  Referring to FIG. 4, interlayer insulating film 32 p is formed on top surface 31 a of lower layer film 31. A predetermined photolithography process and etching process are performed on the interlayer insulating film 32p to form a plurality of grooves 34 reaching the top surface 31a from the top surface of the interlayer insulating film 32p. Next, a sputtering process is performed to form a copper film 33m that fills the groove 34 to the middle. Referring to FIG. 5, a copper plating process is performed to form a copper film 33n on the copper film 33m. As a result, the thickness of the copper film 33 m increases, and the groove 34 is filled with the copper film 33.

  Referring to FIG. 6, the top surface of interlayer insulating film 32 p is polished by gliding tool 35 using chemical mechanical polishing (CMP). Referring to FIG. 7, the copper film 33 serving as the active wiring and the wall structure is formed in the interlayer insulating film 32p by the steps so far.

  Referring to FIG. 8, a resist film 38 having an opening 39 is formed on interlayer insulating film 32p. Referring to FIG. 9, interlayer insulating film 32p is etched using resist film 38 as a mask to form trench 40 reaching top surface 31a. Referring to FIG. 10, resist film 38 is removed. The manufacturing steps shown in FIGS. 8 to 10 are steps added to the manufacturing method of the semiconductor device having only the active wiring and the wall structure in order to provide the sacrificial layer.

  Referring to FIG. 11, interlayer insulating film 32q is formed so as to fill trench 40 and cover interlayer insulating film 32p. At this point, a pseudo plug structure is formed in the interlayer insulating film 32p by the interlayer insulating film 32q filling the trench 40. Referring to FIG. 12, a resist film 43 having an opening 44 is formed on interlayer insulating film 32q. Referring to FIG. 13, interlayer insulating film 32q is etched using resist film 43 as a mask to form trench 45 reaching the top surfaces of copper film 33 and interlayer insulating film 32p.

  Referring to FIG. 14, a sputtering process is performed to form a copper film 33m that fills groove 45 to the middle. Subsequently, a process similar to the process described with reference to FIGS. 5 and 6 is performed, and the copper film 33 serving as an active wiring and a wall structure is formed again on the interlayer insulating film 32q.

  Referring to FIG. 15, by repeating the manufacturing process described above, interlayer insulating film 32 formed by stacking interlayer insulating films 32p, 32q, 32r and 32s is formed on top surface 31a of lower layer film 31. The In the interlayer insulating film 32, an active wiring 48 and a wall structure 47 made of a copper film are formed. In each of the interlayer insulating films 32p, 32q, 32r and 32s, a sacrificial layer constituted by the interlayer insulating films 32q, 32r, 32s and 32t is formed. To the top surface 31a of the lower layer film 31 is formed.

  16 to 19 are cross-sectional views showing the steps of another method for manufacturing the sacrificial layer. The sacrificial layer can also be formed by the manufacturing method described below. Referring to FIG. 16, interlayer insulating films 32p, 32q and 32r are laminated to form an interlayer insulating film 32 including an active wiring 48 and a wall structure 47 made of a copper film. Thereafter, a resist film 51 having an opening 52 is formed on the interlayer insulating film 32.

  Referring to FIG. 17, interlayer insulating films 32r, 32q and 32p are sequentially etched using resist film 51 as a mask to form trench 53 reaching top surface 31a. At this time, since the opening width becomes small at a position close to the top surface 31a where the etching depth is deep, it is necessary to make the width of the opening 52 of the resist film 51 sufficiently large. Thereby, the groove | channel 53 can be formed in the state which reached the top surface 31a reliably.

  Referring to FIG. 18, after removing resist film 51, an interlayer insulating film 54 that fills trench 53 and covers the top surface of interlayer insulating film 32r is formed. Referring to FIG. 19, a predetermined semiconductor manufacturing process such as an etching process or a film forming process is performed on interlayer insulating film 54. Thereby, the interlayer insulating films 32p, 32q, 32r and 54 are laminated, and the interlayer insulating film 32 including the active wiring 48 and the wall structure 47 made of a copper film is formed. In the interlayer insulating films 32p, 32q and 32r, a sacrificial layer 55 constituted by the interlayer insulating film 54 filling the trench 53 is formed.

  FIG. 20 is a cross-sectional view for explaining the effects obtained by the semiconductor device shown in FIG. 1 and the manufacturing method thereof. FIG. 20 shows a cross section of the semiconductor device 10 cut out using the dicing blade 14 in the cutting process of the semiconductor device 10 described with reference to FIG.

  Referring to FIG. 20, cracks 16 are generated on side surface 2 b of interlayer insulating film 2 due to vibration, stress, etc. from dicing blade 14 generated during the cutting process. The crack 16 tends to propagate in the direction in which the boundary between these adjacent layers extends (the direction indicated by the arrow 18) rather than in the layers of the interlayer insulating films 2p, 2q, 2r, and 2s. For this reason, the crack 16 tends to progress from the inactive element region 102 toward the active element region 101.

  However, in the present embodiment, the sacrificial layer 3 is formed in the inactive element region 102. Sacrificial layer 3 forms a boundary with interlayer insulating film 2 extending in a direction perpendicular to main surface 1a (the direction indicated by arrow 19). For this reason, the crack 16 that has reached the sacrificial layer 3 propagates while changing its traveling direction in a direction perpendicular to the main surface 1a.

  In addition, the sacrificial layer 3 formed of a non-metallic material generally has a property of being easily brittle fractured compared to a metal material such as aluminum or copper. For this reason, the sacrificial layer 3 absorbs the energy that the crack 16 propagates by being largely destroyed by itself, and attenuates the crack 16. In some cases, the propagation of the crack 16 causes a crack in the sacrificial layer 3, and the active element region 101 is completely separated from the layer in which the crack 16 is generated.

  For the reasons described above, according to the semiconductor device 10 and the manufacturing method thereof and the semiconductor wafer 11 in the present embodiment, it is ensured that the crack 16 generated during the cutting process of the semiconductor wafer 11 propagates to the active element region 101. Can be prevented. One reason for this is that a sacrificial layer 3 that forms a boundary having anisotropy with respect to the boundary is provided on the interlayer insulating film 2 that has formed a boundary parallel to the main surface 1a. Another reason is that the sacrificial layer 3 is not made of a metal material but is made of a non-metal material that is actively destroyed by itself. Further, the crack 16 does not progress to the wall structure 5 by stopping the progress of the crack 16 by the sacrificial layer 3. As a result, it is possible to avoid a situation in which copper or the like constituting the wall structure 5 is exposed and corrosion proceeds from the exposed portion.

  In addition, in the present embodiment, since the groove 8 reaches the main surface 1a from the top surface 2a, the sacrificial layer 3 filling the groove 8 also extends between the top surface 2a and the main surface 1a. Is formed. The groove 8 extends continuously on a line extending along the side surface 2b, and is formed so as to surround the active element region 101. For this reason, the sacrificial layer 3 is also formed so as to continuously extend on a line along the side surface 2 b of the interlayer insulating film 2 and surround the active element region 101. By forming the sacrificial layer 3 in this way, it is possible to prevent the crack 16 generated on the side surface 2b from reaching the active element region 101 without passing through the sacrificial layer 3. Thereby, when the crack 16 arises, the sacrificial layer 3 can be made to function reliably, and the crack 16 can be prevented from reaching the active element region 101.

  In the present embodiment, the wall structure 5 is provided at the boundary between the active element region 101 and the inactive element region 102. However, the wall structure 5 is not essential in the present invention. Even when the wall structure 5 is not present, the effects of the present embodiment described above can be obtained in the same manner. Further, the shape of the groove 8 may be not only when the side surface of the groove extends at right angles to the main surface 1a, but also when the groove 8 is formed by a gentle slope having an inclination with respect to the main surface 1a. .

(Embodiment 2)
FIG. 21 is a plan view showing a semiconductor device according to the second embodiment of the present invention. The semiconductor device shown in FIG. 21 is drawn with some structures omitted. 22 is a cross-sectional view of the semiconductor device along the line XXII-XXII in FIG. The semiconductor device according to the second embodiment of the present invention basically has the same structure as that of the semiconductor device 10 according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  Referring to FIGS. 21 and 22, in this embodiment, interlayer insulating film 2 is formed on main surface 1 a of silicon substrate 1. Interlayer insulating film 2 is composed of interlayer insulating films 2p, 2q, 2r and 2s which are sequentially stacked on main surface 1a. Interlayer insulating film 2 is formed with grooves 63 and 64 located in inactive element region 102 and extending from top surface 2a to main surface 1a. The grooves 63 and 64 extend in strips in two rows at positions spaced from each other. The grooves 63 and 64 continuously extend on the line along the side surface 2b of the interlayer insulating film 2 without interruption. The grooves 63 and 64 are filled with sacrificial layers 61 and 62, respectively.

  In the semiconductor device according to the second embodiment of the present invention, grooves 63 and 64 as the first grooves extend on a plurality of lines extending along side surface 2b.

  According to the semiconductor device configured as described above, the same effects as those described in the first embodiment can be obtained. In addition, in the present embodiment, two sacrificial layers 61 and 62 always exist between the side surface 2 b of the interlayer insulating film 2 and the active element region 101. For this reason, since the propagation energy of the crack that could not be completely attenuated by the sacrificial layer 62 disposed on the outside is small, the progress of the crack is stopped by the sacrificial layer 61 disposed on the inside. be able to.

(Embodiment 3)
FIG. 23 is a plan view showing a semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in FIG. 23 is drawn with some structures omitted. FIG. 24 is a cross-sectional view of the semiconductor device along the line XXIV-XXIV in FIG. The semiconductor device according to the third embodiment of the present invention basically has the same structure as that of the semiconductor device 10 according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  Referring to FIGS. 23 and 24, in the present embodiment, a groove 72 is formed in interlayer insulating film 2 so as to be located in inactive element region 102 and reach from top surface 2a to main surface 1a. The trench 72 extends in a dotted line on a line along the side surface 2 b of the interlayer insulating film 2. The groove 72 is filled with the sacrificial layer 71.

  In the semiconductor device according to the third embodiment of the present invention, groove 72 as the first groove extends in a dotted line shape on a line extending along side surface 2b.

  According to the semiconductor device configured as described above, the same effects as those described in the first embodiment can be obtained. In addition, as compared with the sacrificial layer 3 described in the first embodiment, the sacrificial layer 71 has more boundary portions having anisotropy in the interlayer insulating film 2. For this reason, the distance until the crack generated in the side surface 2b of the interlayer insulating film 2 is attenuated can be increased. Thereby, since the energy consumed when the crack propagates through the sacrificial layer can be increased, the progress of the crack can be stopped more reliably. In addition, restrictions on the manufacturing process due to the properties of the materials used for the interlayer insulating film 2 and the sacrificial layer 71 (mainly restrictions imposed due to the pattern shape being difficult to etch in the etching process) are avoided. can do.

(Embodiment 4)
FIG. 25 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device shown in FIG. 25 is drawn with some structures omitted. 26 is a cross-sectional view of the semiconductor device along the line XXVI-XXVI in FIG. The semiconductor device according to the fourth embodiment of the present invention basically has the same structure as that of the semiconductor device 10 according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  Referring to FIGS. 25 and 26, in the present embodiment, grooves 72 and 74 are formed in interlayer insulating film 2 and are located in inactive element region 102 and extend from top surface 2a to main surface 1a. Yes. The grooves 72 and 74 extend in a band in two rows at positions spaced from each other. The grooves 72 and 74 extend in a dotted line shape on a line along the side surface 2 b of the interlayer insulating film 2. Grooves 72 and 74 are filled with sacrificial layers 71 and 73, respectively.

  According to the semiconductor device configured as described above, the same effects as those described in the first to third embodiments can be obtained.

(Embodiment 5)
FIG. 27 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention. The semiconductor device shown in FIG. 27 is drawn with some structures omitted. 28 is a cross-sectional view of the semiconductor device along the line XXVIII-XXVIII in FIG. The semiconductor device according to the fifth embodiment of the present invention basically has the same structure as that of the semiconductor device 10 according to the first embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  Referring to FIGS. 27 and 28, in this embodiment, grooves 79p, 79q, 79r and 79s are formed in interlayer insulating films 2p, 2q, 2r and 2s, respectively. Grooves 79p and 79r are arranged so as to be projected on main surface 1a, and grooves 79q and 79s are superimposed on main surface 1a at positions different from the positions at which grooves 79p and 79r are projected. Arranged to be projected. The trenches 79p, 79q, 79r, and 79s continuously extend on the line along the side surface 2b of the interlayer insulating film 2 without interruption. The grooves 79p, 79q, 79r, and 79s are filled with sacrificial layers 78p, 78q, 78r, and 78s, respectively.

  In the semiconductor device according to the fifth embodiment of the present invention, interlayer insulating film 2 includes interlayer insulating films 2p, 2q, 2r and 2s as a plurality of layers sequentially stacked on main surface 1a. The grooves 79p, 79q, 79r, and 79s as the first grooves are formed at positions shifted between the adjacent interlayer insulating films 2p, 2q, 2r, and 2s.

  According to the semiconductor device configured as described above, in addition to the effect described in the first embodiment, the same effect as that described in the third embodiment can be obtained.

(Embodiment 6)
FIG. 29 is a plan view showing a semiconductor device according to the sixth embodiment of the present invention. The semiconductor device shown in FIG. 29 is drawn with some structures omitted. 30 is a cross-sectional view showing the semiconductor device along the line XXX-XXX in FIG. The semiconductor device according to the sixth embodiment of the present invention basically has the same structure as that of the semiconductor device according to the fifth embodiment. Hereinafter, the description of the overlapping structure will not be repeated.

  Referring to FIGS. 29 and 30, in the present embodiment, grooves 92p, 92q, 92r and 92s are formed in the same manner as grooves 79p, 79q, 79r and 79s in the fifth embodiment. However, the trenches 92p, 92q, 92r, and 92s extend in a dotted line on a line along the side surface 2b of the interlayer insulating film 2. The grooves 92p, 92q, 92r and 92s are filled with sacrificial layers 91p, 91q, 91r and 91s, respectively.

  According to the semiconductor device configured as described above, the same effects as those described in the fifth embodiment can be obtained.

  The semiconductor device described in the second to sixth embodiments may be manufactured according to the method for manufacturing the semiconductor device described in the first embodiment.

(Embodiment 7)
FIG. 31 is a plan view showing steps of a method for manufacturing a semiconductor device in the seventh embodiment of the present invention. FIG. 32 is a cross-sectional view of the semiconductor device along the line XXXII-XXXII in FIG. The semiconductor device manufacturing method according to the seventh embodiment of the present invention basically includes the same steps as the semiconductor device manufacturing method according to the first embodiment. Hereinafter, description is not repeated about the overlapping process.

  Referring to FIGS. 31 and 32, in the present embodiment, at the time of manufacturing semiconductor wafer 11 in which a plurality of semiconductor devices 10 are formed, sacrificial layer 95 is formed in interlayer insulating film 2 and at the same time in FIG. A groove 97 extending along the dicing line 12 is formed. Then, the groove 97 is filled with the sacrificial layer 96. Next, during the cutting process using the dicing blade 14, the dicing blade 14 is moved while the dicing blade 14 is in contact with the sacrificial layer 96, thereby cutting the semiconductor wafer 11.

  In the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention, a groove 97 as a third groove disposed on dicing line 12 is formed in interlayer insulating film 2. The trench 97 is filled with a sacrificial layer 96 as a second sacrificial layer containing a non-metallic material. The groove 97 extends on the dicing line 12.

  In the semiconductor wafer 11 according to the seventh embodiment of the present invention, the interlayer insulating film 2 has a groove 97 located on the dicing line 12 located in the inactive element region 102 and extending between the adjacent semiconductor devices 10. Is formed. The trench 97 is filled with a sacrificial layer 96 containing a non-metallic material. The groove 97 extends on the dicing line 12.

  According to the semiconductor wafer and semiconductor device manufacturing method configured as described above, the same effects as those described in the first embodiment can be obtained. In addition, by performing the cutting process while the dicing blade 14 is in contact with the sacrificial layer 96, energy due to vibration and stress at the time of cutting can be more actively absorbed into the sacrificial layer. Thereby, it is possible to further reliably prevent cracks generated during cutting from propagating to the active element region 101. Further, such an effect can be obtained more effectively because the dicing blade 14 and the sacrificial layer 96 are always in contact with each other by forming the groove 97 extending on the dicing line 12.

  In the method for manufacturing a semiconductor device in the present embodiment, the sacrificial layer 95 may have any of the sacrificial layer shapes described in the first to sixth embodiments. Further, the groove 97 does not necessarily extend on the dicing line 12, but is formed on the dicing line 12 by a mark such as a vernier for confirming the positional deviation by marks or the like when overlapping the mask. It may be divided.

  In the first to seventh embodiments, the width occupied by the sacrificial layer is estimated to be about 40 μm or less as an example in consideration of the dimensions such as peeling and cracks that are propagated when dicing. However, if the width to be secured as the inactive element region becomes large, it becomes a restriction on the manufacturing process, so that it is preferably about 5 μm or more and 15 μm or less.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a top view which shows the semiconductor device in Embodiment 1 of this invention. It is sectional drawing of the semiconductor device along the II-II line | wire in FIG. FIG. 2 is a perspective view showing a process of the semiconductor device manufacturing method shown in FIG. 1. It is sectional drawing which shows the 1st process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 2nd process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 3rd process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 4th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 5th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 6th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 7th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 8th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 9th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 10th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 11th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 12th process of the manufacturing method of a sacrificial layer. It is sectional drawing which shows the 1st process of another manufacturing method of a sacrificial layer. It is sectional drawing which shows the 2nd process of another manufacturing method of a sacrificial layer. It is sectional drawing which shows the 3rd process of another manufacturing method of a sacrificial layer. It is sectional drawing which shows the 4th process of another manufacturing method of a sacrificial layer. It is sectional drawing for demonstrating the effect acquired by the semiconductor device shown in FIG. 1, and its manufacturing method. It is a top view which shows the semiconductor device in Embodiment 2 of this invention. FIG. 22 is a cross-sectional view of the semiconductor device along the line XXII-XXII in FIG. 21. It is a top view which shows the semiconductor device in Embodiment 3 of this invention. FIG. 24 is a cross-sectional view of the semiconductor device along the line XXIV-XXIV in FIG. 23. It is a top view which shows the semiconductor device in Embodiment 4 of this invention. FIG. 26 is a cross-sectional view of the semiconductor device along the line XXVI-XXVI in FIG. 25. It is a top view which shows the semiconductor device in Embodiment 5 of this invention. FIG. 28 is a cross-sectional view of the semiconductor device along the line XXVIII-XXVIII in FIG. 27. It is a top view which shows the semiconductor device in Embodiment 6 of this invention. FIG. 30 is a cross-sectional view showing the semiconductor device along the line XXX-XXX in FIG. 29. It is a top view which shows the process of the manufacturing method of the semiconductor device in Embodiment 7 of this invention. FIG. 32 is a cross-sectional view of the semiconductor device along the line XXXII-XXXII in FIG. 31.

Explanation of symbols

  1 silicon substrate, 1a main surface, 2, 2p, 2q, 2r, 2s interlayer insulating film, 2a top surface, 2b side surface, 3, 61, 62, 71, 73, 78p, 78q, 78r, 78s, 91p, 91q, 91r, 91s, 95, 96 sacrifice layer, 5 wall structure, 8, 13, 63, 64, 72, 74, 79p, 79q, 79r, 79s, 92p, 92q, 92r, 92s, 97 groove, 10 semiconductor device, 11 Semiconductor wafer, 12 dicing line, 101 active element region, 102 inactive element region.

Claims (18)

A semiconductor substrate having a main surface, wherein an active element region in which a semiconductor element is formed and an inactive element region extending around the active element region are defined on the main surface;
An interlayer insulating film formed on the main surface,
In the interlayer insulating film, a first groove is formed in the inactive element region, and
A semiconductor device comprising a first sacrificial layer that fills the first trench and includes a non-metallic material. The interlayer insulating film has a top surface and a side surface continuous to the top surface,
The semiconductor device according to claim 1, wherein the first groove is open on the top surface side and extends in parallel with the main surface.   The semiconductor device according to claim 1, wherein the first trench is defined by an inner wall of the interlayer insulating film extending in a direction that forms an angle with respect to the main surface. 4. The semiconductor device according to claim 1, wherein the non-metallic material is at least one material selected from the group consisting of SiO, SiOC, SiN, SiC, SiO ₂ and SiCN. The interlayer insulating film further includes a second groove extending at a boundary between the active element region and the inactive element region, and
The semiconductor device according to claim 1, further comprising a metal layer filling the second groove.   The semiconductor device according to claim 2, wherein the first groove extends continuously on a line extending along the side surface.   The semiconductor device according to claim 2, wherein the first groove extends in a dotted line shape on a line extending along the side surface.   The semiconductor device according to claim 2, wherein the first groove extends on a plurality of lines extending along the side surface.   The semiconductor device according to claim 2, wherein the first groove reaches from the top surface to the main surface.   The semiconductor device according to claim 1, wherein the first groove is formed so as to surround the active element region. The interlayer insulating film includes a plurality of layers sequentially stacked on the main surface,
The semiconductor device according to claim 1, wherein the first groove is formed at a position shifted between the layers adjacent to each other. A semiconductor wafer according to any one of claims 1 to 11, wherein a plurality of semiconductor devices are provided side by side in a lattice pattern,
A semiconductor wafer in which the inactive element region in which the first sacrificial layer is formed is located at a position where the plurality of semiconductor devices are adjacent to each other. The interlayer insulating film is formed with a third groove located on the dicing line located between the semiconductor devices adjacent to each other and located in the inactive element region,
The semiconductor wafer of claim 12, wherein the third trench is filled with a second sacrificial layer comprising a non-metallic material.   The semiconductor wafer according to claim 13, wherein the third groove extends on a dicing line. Comprising a step of forming a semiconductor wafer in which a plurality of semiconductor devices are provided side by side;
Each of the plurality of semiconductor devices includes:
A semiconductor substrate having a main surface, wherein an active element region in which a semiconductor element is formed and an inactive element region extending around the active element region are defined on the main surface;
An interlayer insulating film formed on the main surface,
In the interlayer insulating film, a first groove is formed in the inactive element region, and
A first sacrificial layer filling the first groove and comprising a non-metallic material;
further,
A semiconductor device manufacturing method comprising: cutting the semiconductor wafer along a dicing line located between the semiconductor devices adjacent to each other and located in the inactive element region, and cutting the plurality of semiconductor devices from the semiconductor wafer. Method. A third groove disposed on the dicing line is formed in the interlayer insulating film,
The method of manufacturing a semiconductor device according to claim 15, wherein the third groove is filled with a second sacrificial layer containing a nonmetallic material.   The method of manufacturing a semiconductor device according to claim 16, wherein the third groove extends on the dicing line. 18. The method of manufacturing a semiconductor device according to claim 15, wherein the non-metallic material is at least one material selected from the group consisting of SiO, SiOC, SiN, SiC, SiO ₂ and SiCN. .

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