CN111933617B - Cutting channel structure, semiconductor substrate and manufacturing method thereof - Google Patents
Cutting channel structure, semiconductor substrate and manufacturing method thereof Download PDFInfo
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- CN111933617B CN111933617B CN202010796026.7A CN202010796026A CN111933617B CN 111933617 B CN111933617 B CN 111933617B CN 202010796026 A CN202010796026 A CN 202010796026A CN 111933617 B CN111933617 B CN 111933617B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
Abstract
The invention provides a cutting channel structure, a semiconductor substrate and a manufacturing method thereof. The cutting channel structure provided by the invention is provided with the first medium layer, the part of the first medium layer, which is positioned between the action area of the cutting knife and the device area, is provided with the notch, and when the semiconductor substrate is cut along the action area of the cutting knife to form crystal grains, the notch can prevent cracks generated in the cutting process from extending towards the device area so as to prevent the cracks generated in the cutting process from extending to the device area to further damage the device area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a cutting channel structure, a semiconductor substrate and a manufacturing method thereof.
Background
The wafer comprises a device area and a cutting line (scribe line), wherein the device area is used for forming chips, and the cutting line is used for separating the chips. A commonly used method for separating chips is a mechanical dicing separation method, i.e., a dicing blade is used to act on a device region of a wafer to separate the device region by a mechanical stress generated by the dicing blade.
But the mechanical force of cutting can cause tiny cracks to be generated in the structural layer on the cutting path, and the generated cracks can extend to the device area; further, stress damage is inevitably generated in the crystal, and in order to ensure the integrity of the device structure in the device region after cutting, a sealing ring is usually configured between the cutting track and the circuit region to reduce the stress damage.
And along with diminishing gradually of device district size, the cutting street size between device district and the device interval also reduces gradually, and the micro crack that produces in the cutting process can destroy the sealing ring and finally get into inside the chip to lead to the fact fatal injury to chip itself, consequently need provide a neotype cutting street structure and reduce the damage of mechanical force to the chip in the cutting process.
Disclosure of Invention
The invention provides a scribe line structure, a semiconductor substrate and a manufacturing method thereof, and aims to solve the problem that when the scribe line structure of a scribe line region of the semiconductor substrate is cut in the prior art, a crack is generated in the scribe line structure, and the crack extends into a device region, so that the device region is damaged.
In order to solve the above problems, the present invention provides a scribe line structure formed in a scribe line region of a semiconductor substrate, the scribe line region surrounding a periphery of a device region, and the scribe line region having a dicing blade active region defined thereon, the scribe line structure including: the dicing device comprises a first substrate and a first medium layer formed on the surface of the first substrate, wherein at least one groove is formed in a region, located between the dicing blade action region and the device region, of the first medium layer, and the groove extends towards the direction of the first substrate.
Optionally, a second dielectric layer is formed on the other surface of the first substrate away from the first dielectric layer, and the slot extends through the first dielectric layer and the first substrate towards the second dielectric layer.
Optionally, the scribe line structure further includes a second substrate, where the second substrate is located on a side of the second dielectric layer away from the first dielectric layer and is bonded to the second dielectric layer.
Optionally, the trench extends and stops on a surface where the second substrate is bonded to the second dielectric layer.
Optionally, the depth of the groove is 1 um-20 um.
Optionally, the width of the slot is 0.1 um-10 um.
In order to solve the above problem, the present invention further provides a semiconductor substrate, which includes a device region and a scribe line region located at a periphery of the device region, wherein the scribe line region has a scribe line structure according to any one of claims 1 to 6.
Optionally, the trench is disposed around the device region.
Optionally, the trench discontinuity is disposed around the device region.
Optionally, the number of the at least two trenches is at least two, the at least two trenches are sequentially arranged in a direction away from the device region, and depths of the at least two trenches are sequentially increased in a direction toward the device region.
In order to solve the above problems, the present invention further provides another semiconductor substrate, wherein the semiconductor substrate includes a device region and a scribe line region located at a periphery of the device region, and the scribe line region includes a dicing blade action region; the semiconductor substrate further includes:
the cutting device comprises a first substrate, a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are respectively formed on two surfaces of the first substrate; at least one conductive plug is formed in the second dielectric layer in the device region, and at least one connection pad is formed in the first dielectric layer and the first substrate in the device region, wherein the connection pad is in electrical communication with the conductive plug.
Optionally, a blocking structure is disposed in the second dielectric layer between the conductive plug and the dicing blade active region, and the blocking structure is configured to prevent a crack generated when the semiconductor substrate is diced along the dicing blade active region from extending toward the device region.
In order to solve the above problems, the present invention further provides a method for manufacturing a scribe line structure, the method comprising:
providing a first substrate, wherein the first substrate is provided with a device area and a cutting path area surrounding the device area, and the cutting path area is provided with a cutting knife action area;
forming a first dielectric layer on one surface of the first substrate;
and etching the first dielectric layer between the cutting knife action area and the device area to form at least one notch in the first dielectric layer, and enabling the notch to extend towards the direction of the first substrate.
Optionally, before etching the first dielectric layer, the method further includes:
forming a second dielectric layer on the other surface of the first substrate;
and providing a second substrate, and enabling the second substrate to be positioned on one side of the second dielectric layer, which is far away from the first dielectric layer, and to be bonded with the second dielectric layer.
In order to solve the above problems, the present invention also provides a method for manufacturing a semiconductor substrate, including:
providing a first substrate, wherein the first substrate is provided with a device area and a cutting path area positioned at the periphery of the device area, and the cutting path area comprises a cutting knife acting area;
forming a second dielectric layer on the device region and the cutting path region on the surface of the substrate;
forming at least one conductive plug in the second dielectric layer in the device region;
forming a first dielectric layer on the device region and the cutting path region of the other surface of the first substrate, which is far away from the second dielectric layer;
and etching the first dielectric layer between the cutting knife action area and the device area to form at least one notch in the first dielectric layer between the cutting knife action area and the device area, and enabling the notch to extend towards the direction of the first substrate.
Optionally, the first dielectric layer located in the device region is etched while the first dielectric layer located in the cutting blade active region and the device region is etched, so as to form at least one first opening in the first dielectric layer located in the device region, where the first opening is located and stops on the conductive plug.
Optionally, after forming at least one first opening in the first dielectric layer, the method further includes: filling a conductive material in the first opening to form a connection pad in electrical communication with the conductive plug.
Optionally, the method for forming at least one conductive plug in the second dielectric layer includes:
etching the second dielectric layer in the device region to form at least one second opening in the second dielectric layer in the device region;
and filling a metal conductive material in the second opening to form the conductive plug.
Optionally, while or after forming at least one conductive plug in the second dielectric layer, the method further includes: and forming a blocking structure in the second dielectric layer between the conductive plug and the cutting knife action area, wherein the blocking structure is used for preventing the extension of cracks generated when the semiconductor substrate is cut along the cutting knife action area towards the device area.
The cutting channel structure prepared by the cutting channel structure is formed in the cutting channel area on the periphery of a device area of a semiconductor substrate, wherein at least one notch extending towards the direction of a first substrate is formed in an area, located between a cutting knife action area and the device area, in a first dielectric layer in the cutting channel structure. Therefore, when the semiconductor substrate is cut along the cutting blade action area to form the crystal grains, the grooves can prevent the cracks generated in the cutting process from extending towards the device area, so that the cracks generated in the cutting process are prevented from extending to the device area and further damaging the device area.
Drawings
FIG. 1 is a top view of a semiconductor substrate with scribe line structures in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line B1B2 in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line B1B2 in FIG. 1;
FIG. 4 is a flow chart illustrating a method for fabricating a scribe line structure according to an embodiment of the present invention;
FIGS. 5-8 are schematic structural diagrams illustrating a method for fabricating a semiconductor substrate with scribe line structures according to an embodiment of the present invention;
wherein the reference numbers are as follows:
1-a first substrate;
2-a first dielectric layer;
3-a second dielectric layer; 31-a second sub-dielectric layer;
4-a conductive plug;
5-a barrier structure;
6-a second substrate;
7-connection pads;
101-slotting; 102-a first opening;
Detailed Description
The scribe line structure, the semiconductor substrate and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
FIG. 1 is a schematic top view of a semiconductor substrate with scribe line structures according to an embodiment of the present invention; fig. 2 is a schematic cross-sectional view taken along the direction B1B2 in fig. 1. As shown in fig. 1 and 2, the semiconductor substrate of the present embodiment includes a device region a1 and a scribe lane region a2 surrounding the periphery of the device region a1, wherein a scribe lane structure is formed in the scribe lane region a2, and a scribe lane active region A3 is defined on the scribe lane region a 2. The device region a1 is formed with semiconductor devices, the scribe lane region a2 is used to isolate adjacent device regions a1, and when dicing, the dicing tool performs dicing along the dicing saw active region A3 in the scribe lane region a 2.
In this embodiment, the scribe line structure includes: a first substrate 1 and a first dielectric layer 2 formed on the surface of the first substrate 1, and at least one slot 101 is opened in the first dielectric layer 2 between the dicing blade action region A3 and the device region a1, wherein the slot 101 extends towards the first substrate 1.
In the scribe line structure of the present embodiment, the scribe line region a2 is formed in a periphery of the device region a1 of the semiconductor substrate, and at least one notch 101 extending toward the first substrate 1 is formed in a region, located between the dicing blade active region A3 and the device region a1, of the first dielectric layer 2 in the scribe line structure. As such, when the semiconductor substrate is diced along the dicing saw active area A3 to form a die, the grooves 101 may block the cracks generated during the dicing process from extending toward the device area a1, so as to prevent the cracks generated during the dicing process from extending to the device area a1 and further causing the device area a1 to be damaged.
In this embodiment, the substrate 1 may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included. The material of the first dielectric layer 2 may include silicon oxide, silicon nitride, and the like, and is not particularly limited herein.
Further, with continued reference to fig. 1, in the present embodiment, the trench 101 is disposed around the device region a1, wherein the shape of the pattern formed by the trench 101 may be the same as the device region a 1. In this case, the product design is easier. Optionally, the shape of the trench 101 may not be the same as that of the device region a1, which is not specifically limited herein.
In addition, in this embodiment, the distances between the portions of the slit 101 at different positions of the scribe line region a2 and the device region a1 are equal, so that when the adjacent device regions a1 are cut and separated, the scribe line structure in the scribe line active region A3 is stressed uniformly, and the cutting is smoother. Optionally, the distances between the trench 101 and the device region a1 at different positions may also be unequal, and the shape and position of the trench 101 are not specifically limited herein, subject to practical considerations.
Further, in the present embodiment, the trench 101 is disposed around the device region a1, and the trench 101 is disposed completely around the device region a 1. In an alternative, the trench 101 may also be partially disposed around the device region a 1.
And, in the alternative, the trench 101 may intermittently surround the device region a 1. At this time, the trench 101 is discontinuous in a direction surrounding the device region a 1. Therefore, compared with a structure in which the grooves 101 are continuously arranged in the direction surrounding the device region a1, the strength of the corresponding film layer of the discontinuously arranged structure is relatively high, so that the problem that the cutting is poor due to the fact that the region provided with the grooves 101 is cracked in advance during cutting can be solved.
And, in an alternative, at least two trenches 101 are provided, at least two trenches 101 are sequentially arranged in a direction away from the device region a1, and depths of at least two trenches 101 are sequentially increased in a direction toward the device region a 1. Thus, the depth of the slot 101 is made shallower near the dicing blade application region A3 and deeper near the device region a 1. Therefore, when dicing, the cracks generated in the dicing street region a2 can be blocked by the trenches 101 that are sequentially deeper toward the device region a1 according to the generation sequence. Therefore, not only can the cracking caused by cutting be completely prevented, but also the problem that the die layer of the cutting path area A2 is broken due to the stress generated by the cutting process can be prevented.
Further, with reference to fig. 2, in this embodiment, a second dielectric layer 3 is formed on another surface of the first substrate 1 away from the first dielectric layer 2, and the slot 101 extends through the first dielectric layer 2 and the first substrate 1 toward the second dielectric layer 3.
Further, with reference to fig. 2, in this embodiment, the first dielectric layer 2 and the second dielectric layer 3 are respectively formed on two surfaces of the first substrate 1, and the first dielectric layer 2 and the second dielectric layer 3 are located in the device region a1 and the scribe line region a 2. Wherein at least one conductive plug 4 is formed in the second dielectric layer 3 located in the device region a1, and at least one connection pad 6 is formed in the first dielectric layer 2 and the first substrate 1 located in the device region a 1. Wherein the connection pad 6 is in electrical communication with the conductive plug 4. In this embodiment, the conductive plug 4 and the connection pad 6 may be made of a metal or a metal oxide with a relatively high conductivity, such as a metal of aluminum, tungsten, and the like, and an oxide thereof.
In this embodiment, the second dielectric layer 3 includes at least two second sub-dielectric layers 31, and the material of the second sub-dielectric layers 31 may be silicon oxide, silicon nitride, or the like. And a metal layer (not shown) is arranged between at least adjacent second sub-medium layers 31, and the conductive plug 4 is electrically communicated with the metal layer (not shown) so as to conduct the metal layer (not shown) with an external circuit through the conductive plug 4 and the connection pad 6.
With continued reference to fig. 2, in the present embodiment, a barrier structure 5 is further disposed in the second dielectric layer 3 between the conductive plug 4 and the dicing saw active area A3, and the barrier structure 5 is used to prevent cracks generated when the semiconductor substrate is diced along the dicing saw active area A3 from extending toward the device area a 1. The material of the blocking structure 5 may be metal. When the crack generated during dicing extends toward the device region a1, the barrier structure 5 may further block the extension of the crack toward the device region a1, so as to further prevent the crack generated during dicing from extending to the device region a1 and further causing the device region a1 to be damaged.
Fig. 3 is a schematic cross-sectional view taken along the direction B1B2 in fig. 1. As shown in fig. 3, optionally, in this embodiment, the semiconductor substrate further includes a second substrate 6, where the second substrate 6 is located on a side of the second dielectric layer 3 away from the first dielectric layer 2 and is bonded to the second dielectric layer 3.
And both the conductive plug 4 and the barrier structure 5 can penetrate through the second dielectric layer 3 and then contact with the second substrate 6. Optionally, the conductive plug 4 and the blocking structure 5 may also be located in the second dielectric layer 3, that is, the conductive plug 4 and the blocking structure 5 do not protrude from the second sub-dielectric layer 31 close to the second substrate 6. At this time, the second substrate 6 is bonded to the second sub-dielectric layer 31 adjacent to the second substrate 6.
And, in this embodiment, the slot 101 may also extend and stop on the surface where the second substrate 6 is bonded to the second dielectric layer 3. Optionally, in the above embodiment, the depth of the slot is 1um to 20um, and the width of the slot is 0.1um to 10 um. The depth and width of the slot 101 are not limited in this case.
Based on the scribe line structure and the semiconductor substrate as described above, a description is given below of manufacturing methods for forming the scribe line structure and the semiconductor substrate. FIG. 4 is a flow chart illustrating a method for fabricating a scribe line structure according to an embodiment of the present invention; fig. 5 to 8 are schematic structural diagrams illustrating a method for manufacturing a semiconductor substrate with a scribe line structure according to an embodiment of the present invention. The following describes the dicing street structure and the method for manufacturing a semiconductor substrate provided in this embodiment in detail with reference to fig. 4 to 8.
In step S1, referring to fig. 5, a first substrate 1 is provided, the first substrate 1 having a device region a1 and a scribe lane region a2 surrounding the device region a1, the scribe lane region a2 having a scribe knife active region A3.
The substrate may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S2, referring to fig. 7, a first dielectric layer 2 is formed on the surface of the first substrate 1. Wherein the first dielectric layer 2 is formed on the device region a1 and the scribe line region a2 of the first substrate 1.
Further, referring to fig. 5, in this embodiment, before forming the first dielectric layer 2 on the surface of the first substrate 1, the method further includes forming a second dielectric layer 3 on another surface of the first substrate 1.
The second dielectric layer 3 includes at least two second sub-dielectric layers 31, and the second dielectric layer 31 may be made of silicon oxide, silicon nitride, or the like. Wherein a metal layer (not shown) is disposed between at least two adjacent second sub-dielectric layers 31.
In addition, with continuing reference to fig. 5, in this embodiment, after forming the second dielectric layer 3 on the other surface of the first substrate 1, the method further includes: at least one conductive plug 4 is formed in the second dielectric layer 3 in the device region a1, wherein the conductive plug 4 is in electrical communication with the metal layer (not shown).
The method for forming the conductive plug 4 in the second dielectric layer 3 in the device region a1 comprises the following first step and second step:
in step one, the second dielectric layer 3 in the device region a1 is etched to form at least one second opening (not shown) in the second dielectric layer 3 in the device region a 1.
In step two, the second opening (not shown) is filled with a metal conductive material to form the conductive plug 4.
And, with continued reference to fig. 5, simultaneously with or after forming at least one of the conductive plugs 4 in the second dielectric layer 3 located in the device region a1, the method further comprises: forming a barrier structure 5 in the second dielectric layer 3 between the conductive plug 4 and the dicing saw active area A3, the barrier structure 5 being used to prevent cracks generated when the semiconductor substrate is diced along the dicing saw active area A3 from extending toward the device area a 1. The material of the barrier structure 5 may be metal, and the barrier structure 5 may be disposed in a ring shape to surround the device region a 1. In addition, when the barrier structure 5 and the conductive plug 4 are formed simultaneously, the manufacturing method of the semiconductor substrate of the present invention can be simplified in process.
Further, referring to fig. 6, after forming at least one conductive plug 4 in the second dielectric layer 3 in the device region a1, the method further includes: and providing a second substrate 6, and enabling the second substrate 6 to be located on one side of the second dielectric layer 3, which is far away from the first dielectric layer 2, and to be bonded with the second dielectric layer 3.
In step S3, as shown in fig. 7, the first dielectric layer 2 between the dicing blade active region A3 and the device region a1 is etched to form at least one trench 101 in the first dielectric layer 2, and the trench 101 extends toward the first substrate 1.
In the scribe line structure and the method for manufacturing a semiconductor substrate of the present embodiment, at least one notch 101 extending toward the first substrate 1 is formed in the first dielectric layer 2 in the scribe line structure of the scribe line region a2 of the semiconductor substrate in a region between the dicing saw active region A3 and the device region a 1. As such, when the semiconductor substrate is diced along the dicing saw active area A3 to form a die, the grooves 101 may block the cracks generated during the dicing process from extending toward the device area a1, so as to prevent the cracks generated during the dicing process from extending to the device area a1 and further causing the device area a1 to be damaged.
In addition, in this embodiment, the slot 101 may extend through the first dielectric layer 2 to stop in the first substrate 1, may extend through the first substrate to stop in the second dielectric layer 3, or may extend through the first dielectric layer 2, the first substrate 1 and the second dielectric layer 3 to stop on the surface where the second substrate 2 and the second dielectric layer 3 are bonded. The distance that the slot 101 extends is not particularly limited, and only does it need to pass through the second substrate 6, depending on the time situation.
Optionally, in the above embodiment, the depth of the slot is 1um to 20um, and the width of the slot is 0.1um to 10 um. The depth and width of the slot 101 are not limited in this case.
And, in this embodiment, while etching the first dielectric layer 2 between the dicing saw active area A3 and the device area a1, etching the first dielectric layer 2 in the device area a1 to form at least one first opening 102 in the first dielectric layer 2 in the device area a1, the first opening 102 being located and stopping on the conductive plug 4.
In this embodiment, since the etching of the first dielectric layer 2 between the dicing saw active area A3 and the device area a1 to form the trench 101 and the etching of the first dielectric layer 2 in the device area a1 to form the first opening 102 are performed in the same etching step, the manufacturing process of the semiconductor substrate of the present application can be simplified.
And, referring to fig. 8, in this embodiment, after forming at least one first opening 102 in the first dielectric layer 2, the method further includes: filling the first opening 102 with a conductive material to form a connection pad 7, the connection pad 7 being in electrical communication with the conductive plug 4.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (18)
1. A scribe line structure formed in a scribe line region of a semiconductor substrate, the scribe line region surrounding a periphery of a device region, and a scribe line region on which a scribe knife action region is defined, the scribe line structure comprising: the cutting device comprises a first substrate and a first dielectric layer formed on the surface of the first substrate, wherein at least one groove is formed in a region, located between a cutting knife acting region and a device region, of the first dielectric layer, and the groove extends towards the direction of the first substrate; a second dielectric layer is formed on the other surface of the first substrate, which is far away from the first dielectric layer, and the groove extends through the first dielectric layer and the first substrate towards the direction of the second dielectric layer; a metal layer and at least one conductive plug are formed in the second dielectric layer, and the conductive plug is in electrical communication with the metal layer.
2. The scribe line structure of claim 1, further comprising a second substrate located on a side of the second dielectric layer facing away from the first dielectric layer and bonded to the second dielectric layer.
3. The scribe lane structure of claim 2, wherein the trench extends to and stops at a surface of the second substrate to which the second dielectric layer is bonded.
4. The cutting street structure according to any one of claims 1 to 3, characterized in that the depth of the grooves is 1um to 20 um.
5. The scribe line structure of any one of claims 1 to 3, wherein the width of the trench is 0.1um to 10 um.
6. A semiconductor substrate, comprising a device region and a scribe line region located at the periphery of the device region, wherein the scribe line region has the scribe line structure according to any one of claims 1 to 5.
7. The semiconductor substrate of claim 6, wherein the trench is disposed around the device region.
8. The semiconductor substrate of claim 7, wherein the trench discontinuity is disposed around the device region.
9. The semiconductor substrate of claim 6, wherein there are at least two of the trenches, at least two of the trenches are sequentially disposed in a direction away from the device region, and depths of at least two of the trenches are sequentially increased in a direction toward the device region.
10. The semiconductor substrate is characterized by comprising a device area and a cutting path area positioned on the periphery of the device area, wherein the cutting path area comprises a cutting knife acting area; the semiconductor substrate further includes:
the cutting device comprises a first substrate, a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are respectively formed on two surfaces of the first substrate, at least one notch is formed in the first dielectric layer between a cutting knife action area and a device area, and the notch extends through the first dielectric layer and the first substrate towards the direction of the second dielectric layer; a metal layer and at least one conductive plug are formed in the second dielectric layer in the device region, and at least one connection pad is formed in the first dielectric layer and the first substrate in the device region, wherein the connection pad is in electrical communication with the conductive plug and the metal layer.
11. The semiconductor substrate according to claim 10, wherein a barrier structure is disposed in the second dielectric layer between the conductive plug and the dicing blade active region, the barrier structure being configured to prevent a crack generated when the semiconductor substrate is diced along the dicing blade active region from extending toward the device region.
12. A method of fabricating a scribe line structure, the method comprising:
providing a first substrate, wherein the first substrate is provided with a device area and a cutting path area surrounding the device area, and the cutting path area is provided with a cutting knife action area;
forming a first dielectric layer on one surface of the first substrate;
forming a second dielectric layer on the other surface of the first substrate, forming a metal layer and at least one conductive plug in the second dielectric layer, wherein the conductive plug is electrically communicated with the metal layer;
etching the first dielectric layer between the cutting knife action area and the device area to form at least one notch in the first dielectric layer, and enabling the notch to extend through the first dielectric layer and the first substrate towards the direction of the second dielectric layer.
13. The method of claim 12, wherein prior to etching the first dielectric layer, the method further comprises:
and providing a second substrate, and enabling the second substrate to be positioned on one side of the second dielectric layer, which is far away from the first dielectric layer, and to be bonded with the second dielectric layer.
14. A method for manufacturing a semiconductor substrate, comprising:
providing a first substrate, wherein the first substrate is provided with a device area and a cutting path area positioned at the periphery of the device area, and the cutting path area comprises a cutting knife acting area;
forming a second dielectric layer on the device region and the cutting path region on the surface of the substrate;
forming a metal layer and at least one conductive plug in the second dielectric layer in the device region, the conductive plug in electrical communication with the metal layer;
forming a first dielectric layer on the device region and the cutting path region of the other surface of the first substrate, which is far away from the second dielectric layer;
etching the first dielectric layer between the cutting knife action area and the device area to form at least one notch in the first dielectric layer between the cutting knife action area and the device area, and enabling the notch to extend through the first dielectric layer and the first substrate towards the direction of the second dielectric layer.
15. The method of claim 14, wherein the first dielectric layer in the device region is etched while the first dielectric layer in the dicing blade active region and the device region is etched to form at least one first opening in the first dielectric layer in the device region, the first opening being over and stopping on the conductive plug.
16. The method of manufacturing a semiconductor substrate of claim 15, wherein after forming at least one first opening in the first dielectric layer, the method further comprises: filling a conductive material in the first opening to form a connection pad in electrical communication with the conductive plug.
17. The method of manufacturing a semiconductor substrate of claim 16, wherein the method of forming at least one conductive plug in the second dielectric layer comprises:
etching the second dielectric layer in the device region to form at least one second opening in the second dielectric layer in the device region;
and filling a metal conductive material in the second opening to form the conductive plug.
18. The method of manufacturing a semiconductor substrate of claim 14, wherein, while or after forming at least one conductive plug in the second dielectric layer, the method further comprises: and forming a blocking structure in the second dielectric layer between the conductive plug and the cutting knife action area, wherein the blocking structure is used for preventing the extension of cracks generated when the semiconductor substrate is cut along the cutting knife action area towards the device area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010796026.7A CN111933617B (en) | 2020-08-10 | 2020-08-10 | Cutting channel structure, semiconductor substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010796026.7A CN111933617B (en) | 2020-08-10 | 2020-08-10 | Cutting channel structure, semiconductor substrate and manufacturing method thereof |
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