JPH03270256A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03270256A JPH03270256A JP7107890A JP7107890A JPH03270256A JP H03270256 A JPH03270256 A JP H03270256A JP 7107890 A JP7107890 A JP 7107890A JP 7107890 A JP7107890 A JP 7107890A JP H03270256 A JPH03270256 A JP H03270256A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride layer
- layer
- insulating layer
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000010410 layer Substances 0.000 claims abstract description 55
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000011574 phosphorus Substances 0.000 claims abstract description 6
- 239000005368 silicate glass Substances 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 9
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 5
- 229910021529 ammonia Inorganic materials 0.000 abstract description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000003016 phosphoric acids Chemical class 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、層間絶縁層にシリケートガラスを用いた半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device using silicate glass for an interlayer insulating layer.
［従来の技術］
多層配線構造のＭＯＳトランジスタで（詰、層間絶縁層
として、ＰＳＧ （リン シリケート ガラス）やＢＰ
ＳＧ （ホウ素リン シリケート ガラス）が広く用い
られている。このＰＳＧ層やＢＰＳＧ！ｉｉに対しては
、リフロー技術：こよる平坦ｆヒ処理を行う場合がある
（例えば、特開昭６２−１４４４４号公報に開示されて
いる。）。１Ｊフロー処理を行なう場合には、流動性を
よくするために、ＰＳＧやＢＰＳＧ中のリン濃度を数モ
ルレノく一セントに高める必要がある。[Conventional technology] In a MOS transistor with a multilayer wiring structure, PSG (phosphorus silicate glass) or BP is used as an interlayer insulating layer.
SG (boron phosphorus silicate glass) is widely used. This PSG layer and BPSG! For ii, a reflow technique such as a flattening process may be performed (for example, as disclosed in Japanese Patent Laid-Open No. 14444/1983). When performing 1J flow treatment, it is necessary to increase the phosphorus concentration in PSG or BPSG to several molar cents in order to improve fluidity.
［解決しようとする課題］
ＰＳＧやＢＰＳＧ中のリン濃度を高くすると、水分と反
応してリン酸（１（３ＰＯ４）力く生成される。従来は
このリン酸が、配線用金属として用ｌ）られるアルミニ
ウムを腐蝕させ、素子の信頼性を著しく悪化させるとい
う問題点があった。[Problem to be solved] When the phosphorus concentration in PSG or BPSG is increased, it reacts with moisture and generates phosphoric acid (1(3PO4)). Conventionally, this phosphoric acid was used as a wiring metal. There was a problem in that the aluminum used in the process corroded, significantly deteriorating the reliability of the device.
本発明の目的は、層間絶縁層にＰＳＧやＢＰＳＧを用い
たときに、配線用のアルミニウムか腐蝕しないようにす
ることである。An object of the present invention is to prevent aluminum for wiring from corroding when PSG or BPSG is used as an interlayer insulating layer.
［課題を解決するための手段］
本発明は、ＰＳＧ等を用いた層間絶縁層の表面に窒化シ
リコン層を形成したものである。[Means for Solving the Problems] In the present invention, a silicon nitride layer is formed on the surface of an interlayer insulating layer using PSG or the like.
［作用］
窒化シリコン層が水分の侵入を防ぎ、リン酸の生成を押
える。[Function] The silicon nitride layer prevents moisture from entering and suppresses the production of phosphoric acid.
［実施例］
以下、添付図面に基いて本発明の実施例について説明す
る。[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.
第１図は、本発明における第１の実施例を示したもので
ある。FIG. 1 shows a first embodiment of the present invention.
１１はンリコン基板、１２はＬＯＣＯ５構造のフィール
ド絶縁層、１３はゲート絶縁層、１４はソース、１５は
ドレイン、１６はゲート電極である。１７は層間絶縁層
であり、ＰＳＧやＢＰＳＧ（リン濃度２〜８モルパーセ
ント）を用いて形成され、その厚さは５００〜１０００
ナノメータである。１８は窒化シリコン層であり、層間
絶縁層１７を熱窒化したものである。１９ａ、１９ｂ１
および１９ｃは配線層であり、アルミニウムあるいはア
ルミニウムを主成分とした材料（，１！ −Ｓｉ 、Ａ
ｆ−３ｔ−Ｃｕ等）を用いて形成されている。２０はパ
シベーション層である。11 is a silicon substrate, 12 is a field insulating layer of LOCO5 structure, 13 is a gate insulating layer, 14 is a source, 15 is a drain, and 16 is a gate electrode. Reference numeral 17 denotes an interlayer insulating layer, which is formed using PSG or BPSG (phosphorus concentration 2 to 8 mol percent), and has a thickness of 500 to 1000 mol percent.
It is a nanometer. A silicon nitride layer 18 is obtained by thermally nitriding the interlayer insulating layer 17. 19a, 19b1
and 19c are wiring layers made of aluminum or aluminum-based material (,1!-Si, A
f-3t-Cu, etc.). 20 is a passivation layer.
つぎに、第１図（Ａ）〜（Ｄ）に従って、製造工程（Ａ
）〜（Ｄ）の説明をする。Next, the manufacturing process (A
) to (D) will be explained.
工程（Ａ）：シリコン基板１１上に、ＬＯＧＯ３構造の
フィールド絶縁層１２およびゲート絶縁層１３を形成す
る。つぎにゲート電極１６を形成し、このゲート電極１
６をマスクとして不純物のイオン注入を行い、ソース１
４およびドレイン１５を形成する。つぎに、ＣＶＤ法に
より層間絶縁層１７を形成する。Step (A): A field insulating layer 12 and a gate insulating layer 13 having a LOGO3 structure are formed on a silicon substrate 11. Next, a gate electrode 16 is formed, and this gate electrode 1
6 as a mask, impurity ions are implanted, and source 1 is
4 and a drain 15 are formed. Next, an interlayer insulating layer 17 is formed by a CVD method.
工程（Ｂ）：リフロー技術により、層間絶縁層１７の平
坦化処理を行う。Step (B): The interlayer insulating layer 17 is planarized by reflow technology.
工程（Ｃ）：アンモニア（ＮＨ３）雰囲気中でランプ加
熱処理を行う。処理条件は、加熱温度９００〜１１００
度Ｃ１加熱時間１０〜３０秒が好ましい。ランプ加熱処
理により層間絶縁層１７の表面は窒化され、窒化シリコ
ン層１８が形成される。実際には層間絶縁層１７の表面
が完全に窒化シリコンとなるものではなく、窒化シリコ
ン層１８には多くの酸素が含有されている。なお、ラン
プ加熱処理は、Ｎｏ雰囲気中あるいはＮ２０雰囲気中で
行ってもよい。Step (C): Lamp heat treatment is performed in an ammonia (NH3) atmosphere. Processing conditions are heating temperature 900-1100
Degree C1 heating time is preferably 10 to 30 seconds. The surface of the interlayer insulating layer 17 is nitrided by the lamp heat treatment, and a silicon nitride layer 18 is formed. In reality, the surface of the interlayer insulating layer 17 is not completely made of silicon nitride, and the silicon nitride layer 18 contains a large amount of oxygen. Note that the lamp heat treatment may be performed in an NO atmosphere or an N20 atmosphere.
工程（Ｄ）： ＣＨＦ３等のフレオン系ガスを用いてゲ
ート絶縁層１３、層間絶縁層１７、窒化シリコン層１８
をドライエツチングし、ソース１４、ドレイン１５およ
びゲート電極１６上にコンタクト用の開口部を形成する
。つぎにアルミニウムあるいはアルミニウムを主成分と
した材料を堆積し、これをパターニングして配線層１９
ａ、１９ｂおよび１９ｃを形成する。最後にＣＶＤ法に
よりパシベーション層２０を形成する。Step (D): Gate insulating layer 13, interlayer insulating layer 17, and silicon nitride layer 18 are formed using Freon gas such as CHF3.
is dry etched to form contact openings on the source 14, drain 15 and gate electrode 16. Next, aluminum or a material mainly composed of aluminum is deposited and patterned to form a wiring layer 19.
a, 19b and 19c are formed. Finally, a passivation layer 20 is formed by CVD.
第２図は、本発明における第２の実施例を示しｔ二もの
である。FIG. 2 shows a second embodiment of the present invention.
本実施例は第１の実施例に対して製造工程を変えたもの
である。従って、各構成要素は第１の実施例と同様であ
り、同一の構成要素には同一番号を付し、説明は省略す
る。In this embodiment, the manufacturing process is changed from that of the first embodiment. Therefore, each component is the same as in the first embodiment, the same number is given to the same component, and the explanation is omitted.
製造工程については、第１図（Ａ）〜（Ｄ） 、１！：
第２図（Ａ）〜（Ｄ）とを比較すれば明らかなように、
工程（Ａ）と工程（Ｄ）に関しては第１の実施例と同様
である。従って、ここでは工程（Ｂ）および工程（Ｃ）
についてのみ説明する。Regarding the manufacturing process, see Figures 1 (A) to (D), 1! :
As is clear from comparing Figures 2 (A) to (D),
The steps (A) and (D) are the same as in the first embodiment. Therefore, here step (B) and step (C)
I will only explain about.
工程（Ｂ）：アンモニア（ＮＨ３）雰囲気中でランプ加
熱処理を行う。処理条件は、加熱温度９００〜１１００
度Ｃ１加熱時間１０〜３０秒が好ましい。ランプ加熱処
理により層間絶縁層１７の表面は窒化され、窒化シリコ
ン層１８が形成される。実際には層間絶縁層１７の表面
が完全に窒化シリコンとなるものではなく、窒化シリコ
ン層１８には多くの酸素が含有されている。なお、ラン
プ加熱処理は、Ｎｏ雰囲気中あるいはＮ２０雰囲気中で
行ってもよい。Step (B): Lamp heat treatment is performed in an ammonia (NH3) atmosphere. Processing conditions are heating temperature 900-1100
Degree C1 heating time is preferably 10 to 30 seconds. The surface of the interlayer insulating layer 17 is nitrided by the lamp heat treatment, and a silicon nitride layer 18 is formed. In reality, the surface of the interlayer insulating layer 17 is not completely made of silicon nitride, and the silicon nitride layer 18 contains a large amount of oxygen. Note that the lamp heat treatment may be performed in an NO atmosphere or an N20 atmosphere.
工程（Ｃ） リフロー技術により、層間絶縁層１７の
平坦化処理を行う。このとき、同時に窒化シリコン層１
８も平坦化される。Step (C) Planarization of the interlayer insulating layer 17 is performed using reflow technology. At this time, the silicon nitride layer 1
8 is also flattened.
なお、上記工程（Ｂ）において、加熱温度を高くしたり
加熱時間を長くしたりすることにより、同時に平坦化処
理を行うことも可能である。この場合には、上記工程（
Ｃ）を省略してもよい。In addition, in the above step (B), it is also possible to perform planarization treatment at the same time by increasing the heating temperature or lengthening the heating time. In this case, the above step (
C) may be omitted.
［効果］
本発明では、ＰＳＧ等を用いた層間絶縁層の表面に窒化
シリコン層を形成したため、この窒化シリコン層が水分
の侵入を防いでリン酸の生成を押えることができ、素子
の信頼性が向上する。[Effect] In the present invention, since a silicon nitride layer is formed on the surface of an interlayer insulating layer using PSG or the like, this silicon nitride layer can prevent moisture from entering and suppress the generation of phosphoric acid, improving the reliability of the device. will improve.
第１図は本発明の第１の実施例における製造工程を示し
た断面図、第２図は本発明の第２の実施例における製造
工程を示した断面図である。
１７・・・・・・層間絶縁層
１８・・・・・・窒化シリコン層
１９ ａ、 １９ ｂ、 １９ ｃ−・−・配線層以上FIG. 1 is a sectional view showing the manufacturing process in a first embodiment of the invention, and FIG. 2 is a sectional view showing the manufacturing process in the second embodiment of the invention. 17...Interlayer insulating layer 18...Silicon nitride layer 19a, 19b, 19c---Wiring layer or higher
Claims (3)
、層間絶縁層にリンを含んだシリケートガラスを用いた
半導体装置において、 上記層間絶縁層の表面に窒化シリコン層を形成した半導
体装置。(1) A semiconductor device in which a wiring layer is made of a material mainly composed of aluminum and an interlayer insulating layer is made of silicate glass containing phosphorus, in which a silicon nitride layer is formed on the surface of the interlayer insulating layer.
たものである 請求項１に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the silicon nitride layer is obtained by thermally nitriding the interlayer insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7107890A JPH03270256A (en) | 1990-03-20 | 1990-03-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7107890A JPH03270256A (en) | 1990-03-20 | 1990-03-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03270256A true JPH03270256A (en) | 1991-12-02 |
Family
ID=13450129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7107890A Pending JPH03270256A (en) | 1990-03-20 | 1990-03-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03270256A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06169021A (en) * | 1992-11-30 | 1994-06-14 | Nec Corp | Semiconductor device and manufacture thereof |
| US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
| KR100317501B1 (en) * | 1998-12-29 | 2002-02-19 | 박종섭 | A forming method of flash memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562654A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Semiconductor device |
| JPS5980937A (en) * | 1983-08-31 | 1984-05-10 | Hitachi Ltd | Electronic parts |
-
1990
- 1990-03-20 JP JP7107890A patent/JPH03270256A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562654A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Semiconductor device |
| JPS5980937A (en) * | 1983-08-31 | 1984-05-10 | Hitachi Ltd | Electronic parts |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06169021A (en) * | 1992-11-30 | 1994-06-14 | Nec Corp | Semiconductor device and manufacture thereof |
| US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
| US6794286B2 (en) | 1993-10-29 | 2004-09-21 | Kabushiki Kaisha Toshiba | Process for fabricating a metal wiring and metal contact in a semicondutor device |
| KR100317501B1 (en) * | 1998-12-29 | 2002-02-19 | 박종섭 | A forming method of flash memory device |
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