JPH03105916A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03105916A JPH03105916A JP24421389A JP24421389A JPH03105916A JP H03105916 A JPH03105916 A JP H03105916A JP 24421389 A JP24421389 A JP 24421389A JP 24421389 A JP24421389 A JP 24421389A JP H03105916 A JPH03105916 A JP H03105916A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- layer
- film
- silicon substrate
- opening section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- 238000005121 nitriding Methods 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 10
- 150000002367 halogens Chemical class 0.000 claims abstract description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
- 150000002366 halogen compounds Chemical class 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 16
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 5
- 150000004820 halides Chemical class 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 229910052731 fluorine Inorganic materials 0.000 abstract description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 abstract description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011737 fluorine Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 230000001154 acute effect Effects 0.000 abstract 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 5
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- -1 arsenic ions Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 241000238558 Eucarida Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置の製造方法において、シリコン層の表
面又はシリサイド層の表面を窒化する方法として、窒素
(N2)あるいはアンモニア(NH3 )中で1000
℃以上の高温で熱処理する方法や、N2,NH3ガスの
プラズマで窒化する方法が行われてきた。In the conventional manufacturing method of semiconductor devices, the surface of the silicon layer or the surface of the silicide layer is nitrided by nitriding in nitrogen (N2) or ammonia (NH3).
A method of heat treatment at a high temperature of .degree. C. or higher and a method of nitriding with N2 or NH3 gas plasma have been used.
上述した従来の半導体装置の製造方法は、シリコン層の
表面あるいはシリザイド層の表面の窒化法は、窒化処理
の前に、フッ酸(HF)溶液中でシリコン層表面あるい
はシリサイド層表面に形成された自然形成の酸化シリコ
ン膜を除去しウェーハを乾燥した後に行っていた。しが
しながら、従来の方法では、フッ酸(HF)処理後の自
然酸化膜の形戊は避け難くシリコン層表面に均一で安定
な窒化シリコン膜を形成することが非常に困難であると
いう欠点がある。In the conventional semiconductor device manufacturing method described above, the method of nitriding the surface of a silicon layer or the surface of a silicide layer involves forming a layer on the surface of a silicon layer or a silicide layer in a hydrofluoric acid (HF) solution before nitriding. This was done after removing the naturally formed silicon oxide film and drying the wafer. However, conventional methods have the disadvantage that it is difficult to avoid the formation of a native oxide film after hydrofluoric acid (HF) treatment, making it extremely difficult to form a uniform and stable silicon nitride film on the surface of the silicon layer. There is.
本発明の半導体装置の製造方法は、シリコン層又はシリ
サイド層の表面に設けた絶縁膜を選択的にエッチングし
て開孔部を設ける工程と、前記開孔部に露出した前記シ
リコン層又はシリサイド層の表面をハロゲン系化合物で
処理して前記シリコン層又はシリサイド層の表面に存在
するシリコン原子の結合手をハロゲン又はハロゲン化合
物で終端させる工程と、前記シリコン層又はシリサイド
層の表面を窒化処理して前記シリコン層又はシリサイド
層表面のハロゲン又はハロゲン化合物を窒素と置換して
前記シリコン層又はシリサイド層の表面に窒化シリコン
膜を形成する工程とを含んで構或される。The method for manufacturing a semiconductor device of the present invention includes a step of selectively etching an insulating film provided on a surface of a silicon layer or a silicide layer to form an opening, and a step of forming an opening in the silicon layer or silicide layer exposed in the opening. a step of treating the surface of the silicon layer or silicide layer with a halogen-based compound to terminate the bonds of silicon atoms present on the surface of the silicon layer or silicide layer with a halogen or a halogen compound; and nitriding the surface of the silicon layer or silicide layer. The method includes the step of replacing halogen or a halogen compound on the surface of the silicon layer or silicide layer with nitrogen to form a silicon nitride film on the surface of the silicon layer or silicide layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(f)は、本発明の第1の実施例を説明
するための工程順に示した半導体チップの断面図である
。FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
第1図(a)に示すように、シリコン基板1の上にリン
・珪酸ガラスM(以下PSG膜と記す)を0.5μmの
厚さに堆積した後、ボジ型フォトレジスト膜3を塗布し
て写真蝕刻法によりコンタクト孔形成用の1μmX1μ
mのパターンを設け、次に、フォトレジスト膜3をマス
クとしてPSG膜2をCF4/H2ガスを用いたドライ
エッチング法で除去し、開孔部4を形成する。As shown in FIG. 1(a), after depositing phosphorus-silicate glass M (hereinafter referred to as PSG film) to a thickness of 0.5 μm on a silicon substrate 1, a positive photoresist film 3 is applied. 1μm×1μ for contact hole formation by photolithography.
Then, using the photoresist film 3 as a mask, the PSG film 2 is removed by dry etching using CF4/H2 gas to form the openings 4.
次に、第1図(b)に示すように、フォトレジスト膜3
を除去し、開孔部4内に露出したシリコン基板1の表面
を温度3 0 ’Cの大気圧下のフフ化水素(HF)ガ
ス中で30秒間処理する。このとき、開孔部4内に露出
したシリコン基板1の表面は、フッ素(F)と結合し、
0.5nm程度の厚さのSiFx層5が形成される。Next, as shown in FIG. 1(b), the photoresist film 3
is removed, and the surface of the silicon substrate 1 exposed in the opening 4 is treated in hydrogen fluoride (HF) gas at a temperature of 30'C and atmospheric pressure for 30 seconds. At this time, the surface of the silicon substrate 1 exposed in the opening 4 combines with fluorine (F),
A SiFx layer 5 with a thickness of about 0.5 nm is formed.
次に、第1図(c)に示すように、アンモニア(NH3
)ガスのプラズマ中で600℃の温度で窒化処理を行う
。600゜C程度の温度でFはシリコン基板1の表面よ
り解離し、Fの抜けたシリコン基板1の表面は、容易に
プラズマ励起された窒素をとらえ、シリコン基板1の表
面に0. 5nmの厚さの均一な窒化シリコン膜6が形
成される。Next, as shown in Figure 1(c), ammonia (NH3
) Nitriding treatment is performed at a temperature of 600° C. in gas plasma. At a temperature of about 600°C, F dissociates from the surface of the silicon substrate 1, and the surface of the silicon substrate 1 from which F is removed easily captures plasma-excited nitrogen, and 0. A uniform silicon nitride film 6 with a thickness of 5 nm is formed.
次に、第1図(d)に示すように、850℃のH2−0
2中でPSG膜2をリフローして開孔部の鋭角な上端部
を平滑化する。このとき、開孔部4のシリコン基板1の
表面は、窒化シリコン膜6で保護されているのでPSG
膜2を平滑化するための8 5 0 ’Cの82−02
処理で酸化されることがない。Next, as shown in Figure 1(d), H2-0 at 850°C
2, the PSG film 2 is reflowed to smooth the sharp upper end of the opening. At this time, since the surface of the silicon substrate 1 in the opening 4 is protected by the silicon nitride film 6, the PSG
82-02 at 850'C for smoothing membrane 2
It is not oxidized during processing.
次に、第1図(e)に示すように、CF4/H2のドラ
イエッチングで、窒化シリコン膜6を除去する。Next, as shown in FIG. 1(e), the silicon nitride film 6 is removed by CF4/H2 dry etching.
次に、第1図(f)に示すように開孔部4を含む表面に
アルミニム膜7をスバッタ法により堆積してシリコン基
板1と接続する電極を形戒する。Next, as shown in FIG. 1(f), an aluminum film 7 is deposited on the surface including the opening 4 by a sputtering method to form an electrode to be connected to the silicon substrate 1.
ここで、開孔部4のシリコン基板1の表面に存在するシ
リコン原子の結合手をFの代りにC{等のハロゲンある
いはNF2やBF等のハロケン化物で終端させても良い
。又窒化処理はプラズマ励起法の代りに熱的励起法又は
光励起法を用いてもよい。また、シリコン層の代りにシ
リサイド層を用いても良い。Here, the bonds of silicon atoms existing on the surface of the silicon substrate 1 in the opening 4 may be terminated with a halogen such as C{ or a halide such as NF2 or BF instead of F. Further, for the nitriding treatment, a thermal excitation method or an optical excitation method may be used instead of the plasma excitation method. Furthermore, a silicide layer may be used instead of the silicon layer.
第2図は、本発明の第2の実施例の断面図である。FIG. 2 is a cross-sectional view of a second embodiment of the invention.
この実施例では、多結晶シリコン層と硅化モリブデン層
からなるゲート電極を有するnチャネルMOS}−ラン
ジスタに本発明を適用した場合である。In this embodiment, the present invention is applied to an n-channel MOS transistor having a gate electrode made of a polycrystalline silicon layer and a molybdenum silicide layer.
第2図に示すように、ゲート電極を構戒する多結晶シリ
コン層13と硅化モリブデン層14の膜厚は各々0,2
μmである。このトランジスタのゲート酸化膜12は膜
厚が20nmあり、ソース・トレイン用のn+型拡散層
15は、比抵抗1Ω・cmのp型シリコン基板11中に
ヒ素イオンを加速エネルギー50k e V ,ドーズ
量1×1 () 16cm−2でイオン注入して形成さ
れている。As shown in FIG. 2, the film thicknesses of the polycrystalline silicon layer 13 and the molybdenum silicide layer 14 forming the gate electrode are 0 and 2, respectively.
It is μm. The gate oxide film 12 of this transistor has a film thickness of 20 nm, and the n+ type diffusion layer 15 for source/train is made by accelerating arsenic ions into a p-type silicon substrate 11 with a resistivity of 1 Ω·cm at an energy of 50 k e V and a dose amount. It is formed by ion implantation at 1×1 ( ) 16 cm −2 .
ゲート電極を含む表面に堆積した膜厚0、5μmのPS
G膜1つにコンタクト用の開孔部16を設けた後、第1
図(b)〜(c)に示した第1の実施例と同様の工程で
開札部16に露出した硅化モリブデン層14の表面を4
0 0 ’Cで窒化する。次に、窒化処理後、膜厚1
μmのアルミニウム電極配線工8を選択的に設けてゲー
ト電極と接続する。PS with a thickness of 0.5 μm deposited on the surface including the gate electrode
After providing an opening 16 for contact in one G film, the first
The surface of the molybdenum silicide layer 14 exposed in the bid opening part 16 was
Nitrid at 0 0'C. Next, after nitriding, the film thickness is 1
An aluminum electrode wire 8 of .mu.m is selectively provided and connected to the gate electrode.
サイド層表面に均一で1.nm以下の厚さの極めて薄い
シリサイドの窒化物膜を形成した場合、このシリサイド
の窒化物膜はバリア特性が高く、アルミニウム電極配線
とシリサイド層のコンタクト部でシリコンの析出による
コンタクト抵抗の増大を防ぐ効果もある。Uniform on the side layer surface 1. When an extremely thin silicide nitride film with a thickness of less than nm is formed, this silicide nitride film has high barrier properties and prevents an increase in contact resistance due to silicon precipitation at the contact area between the aluminum electrode wiring and the silicide layer. It's also effective.
以上説明したように本発明は、シリコン層あるいはシリ
サイド層の表面に存在するシリコン原子の結合手をハロ
ゲンあるいはハロゲン化物で終端させた後、窒素と置換
することにより、自然酸化膜がシリコン層あるいはシリ
サイド層表面に形成されない状態で窒化処理を行なうの
で均一な窒化シリコン膜あるいは、シリサイドを形成す
る金属の窒化物と窒化シリコン物の混合膜が容易に得ら
れるという効果を有する。そのため、コンタクト用開孔
部のH2−02処理でPSG膜を平滑化しても開孔部に
露出したシリコン層を酸化することなしに十分なりフロ
ーが可能である。また、シリAs explained above, the present invention terminates the bonds of silicon atoms existing on the surface of a silicon layer or silicide layer with halogen or halide, and then replaces them with nitrogen, thereby converting the natural oxide film into a silicon layer or silicide layer. Since the nitriding process is performed without formation on the surface of the layer, a uniform silicon nitride film or a mixed film of metal nitride and silicon nitride that form silicide can be easily obtained. Therefore, even if the PSG film is smoothed by the H2-02 process in the contact opening, sufficient flow is possible without oxidizing the silicon layer exposed in the opening. Also, Siri
第1図(a)〜(f)は本発明の第1の実施例を説明す
るための工程順に示した半導体チ・ンプの断面図、第2
図は本発明の第2の実施例の断面図である。
1・・・シリコン基板、2・・・PSGI1g、3・・
・フォトレジスト膜、4・・・開孔部、5・・・SiF
x層、6・・・窒化シリコン膜、7・・・アルミニウム
膜、11・ P型シリコン基板、l2・・・ゲート酸化
膜、13・・・多結晶シリコン層、14・・・硅化モリ
ブデン層、15・・・N+型拡散層、16・・・開孔部
、17・・・窒化された硅化モリブデン層、18・・・
アルミニウム電極配線、l9・・・PSG膜。1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention;
The figure is a sectional view of a second embodiment of the invention. 1...Silicon substrate, 2...PSGI1g, 3...
・Photoresist film, 4... Opening part, 5... SiF
x layer, 6... silicon nitride film, 7... aluminum film, 11... P-type silicon substrate, l2... gate oxide film, 13... polycrystalline silicon layer, 14... molybdenum silicide layer, 15... N+ type diffusion layer, 16... Opening portion, 17... Nitrided molybdenum silicide layer, 18...
Aluminum electrode wiring, l9...PSG film.
Claims (1)
択的にエッチングして開孔部を設ける工程と、前記開孔
部に露出した前記シリコン層又はシリサイド層の表面を
ハロゲン系化合物で処理して前記シリコン層又はシリサ
イド層の表面に存在するシリコン原子の結合手をハロゲ
ン又はハロゲン化合物で終端させる工程と、前記シリコ
ン層又はシリサイド層の表面を窒化処理して前記シリコ
ン層又はシリサイド層表面のハロゲン又はハロゲン化合
物を窒素と置換して前記シリコン層又はシリサイド層の
表面に窒化シリコン膜を形成する工程とを含むことを特
徴とする半導体装置の製造方法。selectively etching an insulating film provided on the surface of the silicon layer or silicide layer to form an opening, and treating the surface of the silicon layer or silicide layer exposed in the opening with a halogen compound. A step of terminating the bonds of silicon atoms present on the surface of the silicon layer or silicide layer with a halogen or a halogen compound, and nitriding the surface of the silicon layer or silicide layer to remove halogen or halogen on the surface of the silicon layer or silicide layer. A method for manufacturing a semiconductor device, comprising the step of replacing a halogen compound with nitrogen to form a silicon nitride film on the surface of the silicon layer or silicide layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24421389A JPH0810681B2 (en) | 1989-09-19 | 1989-09-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24421389A JPH0810681B2 (en) | 1989-09-19 | 1989-09-19 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03105916A true JPH03105916A (en) | 1991-05-02 |
JPH0810681B2 JPH0810681B2 (en) | 1996-01-31 |
Family
ID=17115435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24421389A Expired - Fee Related JPH0810681B2 (en) | 1989-09-19 | 1989-09-19 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0810681B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6383880B1 (en) * | 2000-10-05 | 2002-05-07 | Advanced Micro Devices, Inc. | NH3/N2-plasma treatment for reduced nickel silicide bridging |
KR100869865B1 (en) * | 2006-06-29 | 2008-11-24 | 도쿄엘렉트론가부시키가이샤 | Substrate processing method and substrate processing apparatus |
-
1989
- 1989-09-19 JP JP24421389A patent/JPH0810681B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6383880B1 (en) * | 2000-10-05 | 2002-05-07 | Advanced Micro Devices, Inc. | NH3/N2-plasma treatment for reduced nickel silicide bridging |
KR100869865B1 (en) * | 2006-06-29 | 2008-11-24 | 도쿄엘렉트론가부시키가이샤 | Substrate processing method and substrate processing apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPH0810681B2 (en) | 1996-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5324974A (en) | Nitride capped MOSFET for integrated circuits | |
JP2978748B2 (en) | Method for manufacturing semiconductor device | |
US20030029839A1 (en) | Method of reducing wet etch rate of silicon nitride | |
JPH03105916A (en) | Manufacture of semiconductor device | |
JP2001210606A (en) | Method of manufacturing semiconductor device | |
US6204547B1 (en) | Modified poly-buffered isolation | |
JPS6261345A (en) | Manufacture of semiconductor device | |
JPH07135247A (en) | Manufacture of semiconductor device | |
JP3376305B2 (en) | Method for manufacturing semiconductor device | |
JPH03155640A (en) | Manufacture of mos type semiconductor device | |
JPH02106971A (en) | Semiconductor integrated circuit device and manufacture thereof | |
JPH0669039B2 (en) | Method for manufacturing semiconductor device | |
JPH02305444A (en) | Manufacture of semiconductor device | |
JPH03270256A (en) | Semiconductor device | |
JPS58158968A (en) | Manufacture of semiconductor device | |
JPH03278576A (en) | Manufacture of mos transistor | |
JPH04208570A (en) | Manufacture of semiconductor device | |
JPH02218164A (en) | Mis type field-effect transistor | |
JPH0427166A (en) | Manufacture of semiconductor nonvolatile memory | |
JPH01109727A (en) | Semiconductor device and manufacture thereof | |
JPS59161070A (en) | Manufacture of semiconductor device | |
JPS59119746A (en) | Manufacture of semiconductor device | |
JPS63257244A (en) | Semiconductor device and manufacture thereof | |
JPH0578193B2 (en) | ||
JPS62202523A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |