JPS6384024A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6384024A JPS6384024A JP22770286A JP22770286A JPS6384024A JP S6384024 A JPS6384024 A JP S6384024A JP 22770286 A JP22770286 A JP 22770286A JP 22770286 A JP22770286 A JP 22770286A JP S6384024 A JPS6384024 A JP S6384024A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- film
- turned
- tisi2
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 2
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229910000765 intermetallic Inorganic materials 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 4
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 229910008332 Si-Ti Inorganic materials 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910006749 Si—Ti Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 101100537266 Caenorhabditis elegans tin-13 gene Proteins 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関する。特に、低抵
抗で信頼性の高いコンタクト特性の得られる配線方法を
提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention provides a wiring method that provides low resistance and highly reliable contact characteristics.
牛４体デバイスの微細化、ジャンクシ盲ンのシャロウ化
に伴い、コンタクト抵抗及び、コンタクトマイグレーシ
１ン、つき抜は等が大きな問題になってくる。これらを
解決する為、種々のバリアメタルが検討されているが、
信頼性の高い構造や、材料は、得られていない。本発明
は、実用的で信頼性の高い、バリアメタルの形成方法に
関するものである。With the miniaturization of four-body devices and the shallowing of contact lenses, contact resistance, contact migration, penetration, etc. are becoming major problems. Various barrier metals are being considered to solve these problems, but
Highly reliable structures and materials have not been obtained. The present invention relates to a practical and highly reliable method for forming barrier metal.
第２図は従来の配線方法を示したものであり、コンタク
ト孔をあけた後’ｒｉｌ ５ 、ＴｉＮ１６ 。FIG. 2 shows a conventional wiring method, in which after contact holes are made, 'ril 5 and TiN16 are applied.
ＡＬ−８ｉ１７．を連続スパッタし、配線用フォトエッ
チをして、拡散層との接続をとっていた。AL-8i17. was continuously sputtered and photo-etched for wiring to make connections with the diffusion layer.
しかし、この構造において、４００〜４５０℃のアニー
ルを行うと、Ｔ１は完全にシリサイド化しない為、Ｔｉ
Ｎ中のピンホール、クラックを通じて、ＡＬと反応し、
同時に、基板Ｓ１とも反応してＡＬ−Ｔｉ−３ｉの全１
！４間化合物を形成する為、基板にリークしてしまうと
いう欠点があった、又、ＴｉとＳｌとの界面接触抵抗も
高く、トータルの７ンタクト抵抗があまり下らないとい
う問題がありた。However, in this structure, when annealing is performed at 400 to 450°C, T1 is not completely silicided, so Ti
Reacts with AL through pinholes and cracks in N,
At the same time, it also reacts with the substrate S1 and all 1 of AL-Ti-3i
! Since a quaternary compound is formed, there is a problem that it leaks into the substrate, and the interfacial contact resistance between Ti and Sl is also high, resulting in a problem that the total contact resistance does not decrease much.
本発明は、これらの欠点を解決するものであり、方法と
効果について、実施例で説明していく。The present invention solves these drawbacks, and the method and effects will be explained in Examples.
第１図は本発明の概略図である。（α）において、１の
８１基板にＬＯＣＯ９２を形成し、ゲート酸化膜３を形
成後、ＰＯ１７Ｓｉ４とＷＳｉ！５より成るゲー１１を
形成する。続いて低濃度拡散層６をイオン打ち込みでつ
くり、Ｓｉｎ、のサイドウオール７を電極端に形成し、
高濃度拡散領域８を形成する。次に第２フイールド膜９
をデボジシランし、コンタクト孔をつくった後、Ｔｉ膜
１０を３ｏｏ１．ＴｔＮ膜１１を１０００又スパツタで
堆檀する。続いて、酸素濃度１１０ＰＰ以下のランプア
ニール炉で窒素雰囲気中により、コンタクト孔部は、Ｓ
ｉとで１が度応してＴｉ５１、層が形成され、Ｓ ｉ
Ｏ，上のＴ１は、ＴｉＮ化される。又コンタクト部のＴ
ｉＮはそのままで焼きしめられ、ＴｉＳｉ、化しながか
ったで１もでＩＮ化することにより、ピンホールのない
Ｔ九Ｎ１３とＴ ｉ Ｓ ｉｔ層が形成される。この熱
処理を経てＡＬ−３ｉｌ’１％）合金膜１４をデボし、
配線用リソグラフィーを行い、１５．１４を同時にエツ
チングして完成する（第１図（ｂ））。FIG. 1 is a schematic diagram of the invention. In (α), after forming the LOCO 92 on the 81 substrate of 1 and forming the gate oxide film 3, PO17Si4 and WSi! A game 11 consisting of 5 is formed. Next, a low concentration diffusion layer 6 is created by ion implantation, and a side wall 7 of Sin is formed at the end of the electrode.
A high concentration diffusion region 8 is formed. Next, the second field film 9
After forming a contact hole by devodisilating the Ti film 10, A TtN film 11 is deposited using a 1000-layer sputtering technique. Subsequently, the contact hole is heated in a nitrogen atmosphere in a lamp annealing furnace with an oxygen concentration of 110 PP or less.
i and 1 correspond to each other to form a layer of Ti51, and S i
T1 above O is made into TiN. Also, the T of the contact part
The iN is baked as it is, and the TiSi layer is turned into an IN layer with no pinholes. After this heat treatment, the AL-3il'1%) alloy film 14 is debossed,
Lithography for wiring is performed, and 15 and 14 are etched at the same time to complete the process (FIG. 1(b)).
この方法によりＳｌと接触したで１はＴ ｉ Ｓ ｉ。 When contacted with Sl by this method, 1 becomes T i S i .
化し、一部未反応ので１もＴｉＮ化する為、ＡＬ及びＳ
ｌと反応し易い、Ｔｉは、消滅するのセ、従来みられた
ＡＬ−３ｉ−Ｔｉの金属間化合物は、形成されず、基板
の３１もバリア中又は、ＡＬ中に、すわれない為シャン
クシランスパイクは生じない。and since some parts remain unreacted, 1 also becomes TiN, so AL and S
Ti, which easily reacts with 1, disappears, but the conventional AL-3i-Ti intermetallic compound is not formed, and the 31 of the substrate does not sit in the barrier or in the AL, so the shank No silane spikes occur.
又、ＴＩＮは実質的に２層となるのでピンホールもな（
、ＡＬと８１と反応を完全にふせげる。ざらにＡＬ−３
ｉ＝ＴｉＮ＝’Ｉ’ｉＳｉ、間の接触抵抗は非常に低く
、各メタル層の比抵抗も低いことから、トータルとして
信頼性が高く、低抵抗のコンタクト抵抗が得られた。Also, since TIN is essentially two layers, there are no pinholes (
, completely suppresses the reaction with AL and 81. Zarani AL-3
Since the contact resistance between i=TiN='I'iSi was very low and the specific resistance of each metal layer was also low, a highly reliable and low contact resistance was obtained as a whole.
本実施例では、Ｎｔ中でのランプアニールであったがＮ
Ｈ，中でも、あるいは、レーザーアニールでも、又酸素
の少ない他のアニール方法でも同等の効果が得られる。In this example, lamp annealing was performed in Nt.
The same effect can be obtained by using H, laser annealing, or other annealing methods using less oxygen.
Ｔｉ−Ｗ膜においてもＮ。N also exists in the Ti-W film.
中でランプアニールすることにより、ＴｉＳｉ。By lamp annealing in TiSi.
とＴｉＮＪ＊が形成され本実施例と同等の効果が得られ
た。and TiNJ* were formed, and the same effect as this example was obtained.
第１図（α）、Ｃｂ）は本発明の半導体装置の製造方法
の概略図を示すものであり、第２図は、在米方法による
概略図である。
１・・・・・・・・・シリコン基板
２・・・・・・・・・ｂｏａｏｓ
３・・・・・・・・・ゲート膜
４・・・・・・・・・ポリシリコン
５・・・・・・・・・ＷＳｉ。
６・・・・・・・・・低濃度拡散層
７・・・・・・・・・サイドウオール
８・・・・・・・・・高濃度拡散層
９・・・・・・・・・第２フイールド酸化膜１０・・・
・・・Ｔ１
１１・・・・・・ＴｉＮ
１２・−・・・ＴｉＳｉ！
１３・・・・・・反応性ＴｉＮ
１４・・・・・・ＡＬ−８ｉ
以 上FIG. 1(α), Cb) shows a schematic diagram of the method of manufacturing a semiconductor device of the present invention, and FIG. 2 is a schematic diagram of the method based in the United States. 1... Silicon substrate 2... Boaos 3... Gate film 4... Polysilicon 5...・・・・・・WSi. 6...Low concentration diffusion layer 7...Side wall 8...High concentration diffusion layer 9... Second field oxide film 10...
...T1 11...TiN 12...TiSi! 13...Reactive TiN 14...AL-8i or more
Claims (2)
形成の後、シリサイド膜／メタル膜の積層膜を形成する
工程と、Ｎ＿２を含む短時間アニール、又は、レーザー
アニール工程を経て、配線用ＡＬ、又はＡＬ合金膜を形
成することを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device, after forming a contact hole, a process of forming a laminated film of a silicide film/metal film, and a short-time annealing process including N_2 or a laser annealing process are performed to form an AL for wiring, Alternatively, a method for manufacturing a semiconductor device, comprising forming an AL alloy film.
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, characterized in that a Ti--W film is formed after forming the contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22770286A JPS6384024A (en) | 1986-09-26 | 1986-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22770286A JPS6384024A (en) | 1986-09-26 | 1986-09-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384024A true JPS6384024A (en) | 1988-04-14 |
Family
ID=16865007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22770286A Pending JPS6384024A (en) | 1986-09-26 | 1986-09-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384024A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01304727A (en) * | 1988-06-02 | 1989-12-08 | Sony Corp | Preparation of semiconductor device |
| JPH02237026A (en) * | 1989-03-09 | 1990-09-19 | Sony Corp | Manufacture of semiconductor device |
| JPH0319331A (en) * | 1989-05-27 | 1991-01-28 | Goldstar Electron Co Ltd | D ram element and method of improving degree of integration of d ram element |
| JPH05190549A (en) * | 1991-07-08 | 1993-07-30 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| JPH0778789A (en) * | 1993-09-08 | 1995-03-20 | Nec Corp | Manufature of semiconductor device |
| DE4329260B4 (en) * | 1992-10-05 | 2007-01-25 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100427A (en) * | 1980-01-16 | 1981-08-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6010717A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Fabrication of contact for semiconductor device |
| JPS61102059A (en) * | 1984-10-25 | 1986-05-20 | Nec Corp | Semiconductor device |
| JPS61142739A (en) * | 1984-12-17 | 1986-06-30 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61174767A (en) * | 1985-01-30 | 1986-08-06 | Nec Corp | Semiconductor element electrode |
-
1986
- 1986-09-26 JP JP22770286A patent/JPS6384024A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100427A (en) * | 1980-01-16 | 1981-08-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6010717A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Fabrication of contact for semiconductor device |
| JPS61102059A (en) * | 1984-10-25 | 1986-05-20 | Nec Corp | Semiconductor device |
| JPS61142739A (en) * | 1984-12-17 | 1986-06-30 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61174767A (en) * | 1985-01-30 | 1986-08-06 | Nec Corp | Semiconductor element electrode |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01304727A (en) * | 1988-06-02 | 1989-12-08 | Sony Corp | Preparation of semiconductor device |
| JPH02237026A (en) * | 1989-03-09 | 1990-09-19 | Sony Corp | Manufacture of semiconductor device |
| JPH0319331A (en) * | 1989-05-27 | 1991-01-28 | Goldstar Electron Co Ltd | D ram element and method of improving degree of integration of d ram element |
| JPH05190549A (en) * | 1991-07-08 | 1993-07-30 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| DE4329260B4 (en) * | 1992-10-05 | 2007-01-25 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
| DE4329260B9 (en) * | 1992-10-05 | 2007-05-24 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
| JPH0778789A (en) * | 1993-09-08 | 1995-03-20 | Nec Corp | Manufature of semiconductor device |
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